PIC12F635-I/SN Microchip Technology, PIC12F635-I/SN Datasheet
PIC12F635-I/SN
Specifications of PIC12F635-I/SN
Available stocks
Related parts for PIC12F635-I/SN
PIC12F635-I/SN Summary of contents
Page 1
... PIC12F635/PIC16F636/639 *8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. © 2007 Microchip Technology Inc. Data Sheet 8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology DS41232D ...
Page 2
... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... PIC12F635/PIC16F636/639 8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers With nanoWatt Technology High-Performance RISC CPU: • Only 35 instructions to learn: - All single-cycle instructions except branches • Operating speed – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Interrupt capability • 8-level deep hardware stack • Direct, Indirect and Relative Addressing modes Special Microcontroller Features: • ...
Page 4
... PIC12F635/PIC16F636/639 Program Memory Device Flash (words) SRAM (bytes) PIC12F635 1024 PIC16F636 2048 PIC16F639 2048 Note 1: Any references to PORTA, RAn, TRISA and TRISAn refer to GPIO, GPn, TRISIO and TRISIOn, respectively the supply voltage of the Analog Front-End section (PIC16F639 only). V DDT this document unless otherwise stated. ...
Page 5
... GP1 6 C1IN- GP2 5 C1OUT (1) GP3 4 — GP4 3 — GP5 2 — — 1 — — 8 — Note 1: Input only. 2: Only when pin is configured for external MCLR. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 GP0/C1IN+/ICSPDAT/ULPWU 2 7 GP1/C1IN-/ICSPCLK 6 3 GP2/T0CKI/INT/C1OUT GP0/CIN+/ICSPDAT/ULPWU 6 GP1/CIN-/ICSPCLK ...
Page 6
... PIC12F635/PIC16F636/639 14-Pin Diagram (PDIP, SOIC, TSSOP) RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/V RC4/C2OUT TABLE 2: 14-PIN SUMMARY (PDIP, SOIC, TSSOP) I/O Pin Comparators RA0 13 C1IN+ RA1 12 C1IN- RA2 11 C1OUT (1) RA3 4 — RA4 3 — RA5 2 — RC0 10 C2IN+ RC1 9 C2IN- RC2 8 — RC3 7 — RC4 6 C2OUT ...
Page 7
... C2OUT RC5 4 — — 16 — — 13 — — 14 — — 15 — Note 1: Input only. 2: Only when pin is configured for external MCLR. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 12 RA0/C1IN+/ICSPDAT/ULPWU 1 RA1/C1IN-/ PIC16F636 10 RA2/T0CKI/INT/C1OUT 3 PP RC0/C2IN Timer Interrupts — IOC — IOC T0CKI INT/IOC — ...
Page 8
... PIC12F635/PIC16F636/639 20-Pin Diagram SSOP RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/V RC4/C2OUT RC3/LFDATA/RSSI/CCLK/SDIO V DDT TABLE 4: 20-PIN SUMMARY I/O Pin Analog Front-End RA0 19 — RA1 18 — RA2 17 — (1) RA3 4 — RA4 3 — RA5 2 — RC0 16 — RC1 15 — RC2 14 ALERT RC3 7 LFDATA/RSSI RC4 6 — RC5 5 — ...
Page 9
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 223 DS41232D-page 7 ...
Page 10
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 8 © 2007 Microchip Technology Inc. ...
Page 11
... T0CKI Cryptographic Module © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Block Diagrams and pinout descriptions of the devices are as follows: • PIC12F635 (Figure 1-1, Table 1-1) • PIC16F636 (Figure 1-2, Table 1-2) • PIC16F639 (Figure 1-3, Table 1-3) 13 Data Bus Program Counter RAM ...
Page 12
... PIC12F635/PIC16F636/639 FIGURE 1-2: PIC16F636 BLOCK DIAGRAM Configuration 13 Flash Program Memory Program 14 Bus Instruction Reg 8 Instruction Decode and Control OSC1/CLKIN Timing Generation OSC2/CLKOUT 8 MHz 31 kHz Internal Internal Oscillator Oscillator Timer0 T0CKI Cryptographic Module C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT DS41232D-page 10 Data Bus ...
Page 13
... Low-voltage Detect 8 MHz 31 kHz Internal Internal Oscillator Oscillator MCLR V Timer0 T0CKI K Module EELOQ C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 8 Data Bus Program Counter RAM 128 8-level Stack bytes (13-bit) File Registers (1) RAM Addr 9 Addr MUX ...
Page 14
... PIC12F635/PIC16F636/639 TABLE 1-1: PIC12F635 PINOUT DESCRIPTIONS Name Function GP0/C1IN+/ICSPDAT/ULPWU GP0 C1IN+ ICSPDAT ULPWU GP1/C1IN-/ICSPCLK GP1 C1IN- ICSPCLK GP2/T0CKI/INT/C1OUT GP2 T0CKI INT C1OUT GP3/MCLR/V GP3 PP MCLR V PP GP4/T1G/OSC2/CLKOUT GP4 T1G OSC2 CLKOUT GP5/T1CKI/OSC1/CLKIN GP5 T1CKI OSC1 CLKIN Legend Analog input or output ...
Page 15
... Legend Analog input or output HV = High Voltage TTL = TTL compatible input © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Input Output Type Type TTL — General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin. AN — Comparator 1 input – positive. ...
Page 16
... PIC12F635/PIC16F636/639 TABLE 1-3: PIC16F639 PINOUT DESCRIPTIONS Name Function LCCOM LCCOM LCX LCX LCY LCY LCZ LCZ RA0/C1IN+/ICSPDAT/ULPWU RA0 C1IN+ ICSPDAT ULPWU RA1/C1IN-/V /ICSPCLK RA1 REF C1IN- V REF ICSPCLK RA2/T0CKI/INT/C1OUT RA2 T0CKI INT C1OUT RA3 RA3/MCLR/V PP MCLR V PP RA4 RA4/T1G/OSC2/CLKOUT T1G ...
Page 17
... Legend Analog input or output HV = High Voltage TTL = TTL compatible input © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Input Output Type Type TTL CMOS General purpose I/O. — CMOS Digital output representation of analog input signal to LC pins. — Current Received signal strength indicator. Analog current that is proportional to input amplitude. — ...
Page 18
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 16 © 2007 Microchip Technology Inc. ...
Page 19
... Program Memory Organization The PIC12F635/PIC16F636/639 devices have a 13-bit program counter capable of addressing program memory space. Only the first (0000h-03FFh, for the PIC12F635) and (0000h-07FFh, for the PIC16F636/639) is physically implemented. Accessing a location above these boundaries will cause a wraparound within the first space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1) ...
Page 20
... PIC12F635/PIC16F636/639 2.2.1 GENERAL PURPOSE REGISTER The register file is organized for the PIC12F635 and 128 x 8 for the PIC16F636/639. Each register is accessed, either directly or indirectly, through the File Select Register, FSR (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 ...
Page 21
... FIGURE 2-3: PIC12F635 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR GPIO 05h TRISIO 06h 07h 08h 09h PCLATH 0Ah PCLATH INTCON 0Bh INTCON PIR1 0Ch ...
Page 22
... PIC12F635/PIC16F636/639 FIGURE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA 06h PORTC 07h TRISC 08h 09h PCLATH 0Ah PCLATH INTCON 0Bh ...
Page 23
... TABLE 2-1: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bit 5 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module Register 02h PCL Program Counter’s (PC) Least Significant Byte ...
Page 24
... PIC12F635/PIC16F636/639 TABLE 2-2: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RAPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte 83h ...
Page 25
... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatch exists. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Bit 4 Bit 3 Bit 2 TO ...
Page 26
... PIC12F635/PIC16F636/639 TABLE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RAPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte 83h ...
Page 27
... TABLE 2-5: PIC12F635/PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2 Addr Name Bit 7 Bit 6 Bank 2 10Ch — Unimplemented 10Dh — Unimplemented 10Eh — Unimplemented 10Fh — Unimplemented 110h CRCON GO/DONE ENC/DEC (2) 111h CRDAT0 Cryptographic Data Register 0 (2) 112h CRDAT1 Cryptographic Data Register 1 (2) ...
Page 28
... PIC12F635/PIC16F636/639 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (GPR and SFR) The STATUS register can be the destination for any instruction, like any other register. If the STATUS ...
Page 29
... Microchip Technology Inc. PIC12F635/PIC16F636/639 Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting the PSA bit of the OPTION register to ‘1’. See Section 5.1.3 “Software Programmable Prescaler”. R/W-1 ...
Page 30
... PIC12F635/PIC16F636/639 2.2.2.3 INTCON Register The INTCON register is a readable and writable register which contains the various enable and flag bits for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts. REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 GIE ...
Page 31
... TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: PIC16F636/639 only. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 ...
Page 32
... PIC12F635/PIC16F636/639 2.2.2.5 PIR1 Register The PIR1 register contains the interrupt flag bits, as shown in Register 2-5. REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0 R/W-0 R/W-0 EEIF LVDIF CRIF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ...
Page 33
... BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: BOREN<1:0> the Configuration Word register for this bit to control the BOR. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 R/W-1 R/W-x U-0 (1) SBOREN — ...
Page 34
... Table Read” (DS00556). DS41232D-page 32 2.3.2 STACK The PIC12F635/PIC16F636/639 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...
Page 35
... FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F635/PIC16F636/639 Direct Addressing From Opcode 6 RP1 RP0 Bank Select Location Select 00h Data Memory 7Fh Bank 0 Note: For memory map detail, see Figure 2-2. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 0 IRP Bank Select 180h Bank 1 Bank 2 Bank 3 ...
Page 36
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 34 © 2007 Microchip Technology Inc. ...
Page 37
... OSC2 Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 The Oscillator module can be configured in one of eight clock modes – External clock with I/O on OSC2/CLKOUT – 32 kHz Low-Power Crystal mode – Medium Gain Crystal or Ceramic Resonator Oscillator mode. ...
Page 38
... PIC12F635/PIC16F636/639 3.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure 3-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: • Frequency selection bits (IRCF) • Frequency Status bits (HTS, LTS) • System clock control bits (OSTS, SCS) ...
Page 39
... Upon restarting the external clock, the device will resume operation time had elapsed. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 3.4 External Clock Modes 3.4.1 OSCILLATOR START-UP TIMER (OST) ...
Page 40
... PIC12F635/PIC16F636/639 3.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 3-3). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier ...
Page 41
... The user also needs to take into account variation due to tolerance of external RC components used. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 3.5 Internal Clock Modes The Oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source ...
Page 42
... PIC12F635/PIC16F636/639 3.5.2.1 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-2). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. REGISTER 3-2: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 ...
Page 43
... OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 3.5.5 HF AND LF INTOSC CLOCK SWITCH TIMING When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power (see Figure 3-6) ...
Page 44
... PIC12F635/PIC16F636/639 FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING ( HFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC LFINTOSC IRCF <2:0> 0 System Clock Note 1: When going from LF to HF. HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC LFINTOSC IRCF <2:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time 2-cycle Sync HFINTOSC IRCF < ...
Page 45
... OSTS bit of the OSCCON register to remain clear. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 When the Oscillator module is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.4.1 “Oscillator Start-up Timer (OST)”). The OST will suspend program execution until 1024 oscillations are counted ...
Page 46
... PIC12F635/PIC16F636/639 3.7.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 3-7: TWO-SPEED START-UP ...
Page 47
... The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 3.8.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or toggling the SCS bit of the OSCCON register ...
Page 48
... PIC12F635/PIC16F636/639 FIGURE 3-9: FSCM TIMING DIAGRAM Sample Clock System Clock Output Clock Monitor Output (Q) OSFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES ...
Page 49
... RA<5:4,1:0> ;as outputs © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 4.2 Additional Pin Functions Every PORTA pin on the PIC12F635/PIC16F636/639 has an interrupt-on-change option and a weak pull-up/pull-down option. RA0 has an Ultra Low-Power Wake-up option. The next three sections describe these functions. 4.2.1 WEAK PULL-UP/PULL-DOWN Each of the PORTA pins, except RA3, has an internal weak pull-up and pull-down ...
Page 50
... PIC12F635/PIC16F636/639 REGISTER 4-1: PORTA: PORTA REGISTER U-0 U-0 R/W-x — — RA5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA<5:0>: PORTA I/O Pin bit 1 = Port pin is > Port pin is < V ...
Page 51
... WPUDA5 bit can be written if INTOSC is enabled and T1OSC is disabled; otherwise, the bit can not be written and reads as ‘1’. WPUDA4 bit can be written if not configured as OSC2; otherwise, the bit can not be written and reads as ‘1’ © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 R/W-1 U-0 ...
Page 52
... PIC12F635/PIC16F636/639 4.2.2 INTERRUPT-ON-CHANGE Each of the PORTA pins is individually configurable as an interrupt-on-change pin. Control bits, IOCAx, enable or disable the interrupt function for each pin. Refer to Register 4-5. The interrupt-on-change is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTA. The ‘ ...
Page 53
... Programmable Low-Voltage Detect or temperature sensor. Note: For more information, refer to the Application Note AN879, “Using the Microchip Ultra Low-Power Wake-up Module” (DS00879). © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 EXAMPLE 4-2: BANKSEL PORTA BSF PORTA,0 MOVLW H’7’ MOVWF ...
Page 54
... PIC12F635/PIC16F636/639 4.2.4 PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, such as the comparator, refer to the appropriate section in this data sheet. FIGURE 4-1: ...
Page 55
... RD PORTA To Comparator Note 1: Comparator mode determines Analog Input mode. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 4.2.4.3 Figure 4-3 shows the diagram for this pin. The RA2 pin is configurable to function as one of the following: • a general purpose I/O • the clock input for Timer0 • ...
Page 56
... PIC12F635/PIC16F636/639 4.2.4.4 RA3/MCLR/V PP Figure 4-4 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset with weak pull-up • a high-voltage detect for Program mode entry FIGURE 4-4: BLOCK DIAGRAM OF RA3 ...
Page 57
... Oscillator modes are XT, HS, LP, LPTMR1 and CLKOUT Enable. 2: With CLKOUT option. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 4.2.4.6 Figure 4-6 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following: • a general purpose I/O • a Timer1 clock input • ...
Page 58
... PIC12F635/PIC16F636/639 TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Name Bit 7 Bit 6 Bit 5 PORTA — — RA5 INTCON GIE PEIE T0IE TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register ...
Page 59
... Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISC<5:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated PORTC pin configured as an output © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 EXAMPLE 4-3: INITIALIZING PORTC BANKSEL PORTC CLRF PORTC MOVLW 07h ...
Page 60
... PIC12F635/PIC16F636/639 4.3.1 RC0/C2IN+ Figure 4-7 shows the diagram for this pin. The RC0 pin is configurable to function as one of the following: • a general purpose I/O • an analog input to the comparator 4.3.2 RC1/C2IN- Figure 4-7 shows the diagram for this pin. The RC1 pin is configurable to function as one of the following: • ...
Page 61
... RC5 CMCON0 C2OUT C1OUT C2INV TRISC — — TRISC5 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 V DD I/O pin V SS Bit 4 Bit 3 Bit 2 Bit 1 RC4 RC3 RC2 ...
Page 62
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 60 © 2007 Microchip Technology Inc. ...
Page 63
... T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register. 3: WDTE bit is in the Configuration Word register. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 5.1.1 ...
Page 64
... PIC12F635/PIC16F636/639 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. ...
Page 65
... TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ...
Page 66
... PIC12F635/PIC16F636/639 6.0 TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 3-bit prescaler • Optional LP oscillator • Synchronous or asynchronous operation • Timer1 gate (count enable) via comparator or T1G pin • ...
Page 67
... Without CLKOUT T1OSCEN Note 1: ST Buffer is low power type when using LP osc, or high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 TMR1ON To C2 Comparator Module Timer1 Clock ( TMR1L 1 ...
Page 68
... PIC12F635/PIC16F636/639 6.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples determined by the Timer1 prescaler. CY 6.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. ...
Page 69
... Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 6.9 Comparator Synchronization The same clock used to increment Timer1 can also be used to synchronize the comparator output. This feature is enabled in the Comparator module ...
Page 70
... PIC12F635/PIC16F636/639 6.10 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 6-1: T1CON: TIMER 1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 (1) (2) T1GINV TMR1GE T1CKPS1 bit 7 Legend Readable bit ...
Page 71
... Holding Register for the Least Significant Byte of the 16-bit TMR1 Register T1CON T1GINV TMR1GE T1CKPS1 Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: PIC16F636/639 only. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Bit 4 Bit 3 Bit 2 Bit 1 — — — T1GSS INTE RAIE ...
Page 72
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 70 © 2007 Microchip Technology Inc. ...
Page 73
... the output of the comparator is a digital high level. IN The PIC12F635 contains a single comparator as shown in Figure 7-2. The PIC16F636/639 devices contains two comparators as shown in Figure 7-3 and Figure 7-4. The comparators are not independently configurable. FIGURE 7-1: ...
Page 74
... PIC12F635/PIC16F636/639 FIGURE 7-3: COMPARATOR C1 OUTPUT BLOCK DIAGRAM (PIC16F636/639) C1INV C1 Note 1: Q1 and Q3 are phases of the four-phase system clock ( held high during Sleep mode. FIGURE 7-4: COMPARATOR C2 OUTPUT BLOCK DIAGRAM (PIC16F636/639) C2INV C2 Note 1: Comparator output is latched on falling edge of Timer1 clock source and Q3 are phases of the four-phase system clock ( held high during Sleep mode ...
Page 75
... Analog Voltage Threshold Voltage T © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Note 1: When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. . The analog SS 2: Analog levels on any pin defined as a and V ...
Page 76
... Analog function (A): digital input buffer is disabled • Digital function (D): comparator digital output, overrides port function • Normal port function (I/O): independent of comparator FIGURE 7-6: COMPARATOR I/O OPERATING MODES (PIC12F635) Comparator Reset (POR Default Value – low power) CM<2:0> = 000 A CIN- A ...
Page 77
... A IN C2IN C2IN+ Legend Analog Input, ports always reads ‘0’ I/O = Normal port I/O Note 1: Reads as ‘0’, unless CxINV = 1. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Two Independent Comparators CM<2:0> = 100 A C1IN- (1) Off A C1IN+ A C2IN- (1) Off A C2IN+ One Independent Comparator CM< ...
Page 78
... DS41232D-page 76 7.4.3 COMPARATOR INPUT SWITCH The inverting input of the comparators may be switched between two analog pins in the following modes: PIC12F635 • CM<2:0> = 101 • CM<2:0> = 110 PIC16F636/639 • CM<2:0> = 001 (Comparator C1 only) • CM<2:0> = 010 (Comparators C1 and C2) In the above modes, both pins remain in Analog mode regardless of which pin is selected as the input ...
Page 79
... See the Comparator and Voltage Specifications in Section 15.0 “Electrical Specifications” for more details. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 7.6 Comparator Interrupt Operation The comparator interrupt flag is set whenever there is a change in the output value of the comparator. Changes ...
Page 80
... PIC12F635/PIC16F636/639 FIGURE 7-8: COMPARATOR INTERRUPT TIMING W/O CMCON0 READ CxOUT Set CxIF (level) CxIF FIGURE 7-9: COMPARATOR INTERRUPT TIMING WITH CMCON0 READ CxOUT Set CxIF (level) CxIF cleared by CMCON0 read reset by software Note change in the CMCON0 register (CxOUT) should occur when a read ...
Page 81
... The instruction following the Sleep instruction always executes following a wake from Sleep. If the GIE bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine. REGISTER 7-1: CMCON0: COMPARATOR CONFIGURATION REGISTER (PIC12F635) U-0 R-0 U-0 — COUT — ...
Page 82
... PIC12F635/PIC16F636/639 REGISTER 7-2: CMCON0: COMPARATOR CONFIGURATION REGISTER (PIC16F636/639) R-0 R-0 R/W-0 C2OUT C1OUT C2INV bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 C2OUT: Comparator 2 Output bit When C2INV = > < When C2INV = < > bit 6 C1OUT: Comparator 1 Output bit ...
Page 83
... See the Comparator Block Diagram (Figure 7-2) and the Timer1 Block Diagram (Figure 6-1) for more information. Note: References to the comparator in this section specifically are Comparator C2 on the PIC16F636/639. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 referring to referring to DS41232D-page 81 ...
Page 84
... PIC12F635/PIC16F636/639 REGISTER 7-3: CMCON1: COMPARATOR CONFIGURATION REGISTER (PIC12F635) U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-2 Unimplemented: Read as ‘0’ bit 1 T1GSS: Timer1 Gate Source Select bit 1 = Timer1 Gate Source is T1G pin (pin should be configured as digital input) ...
Page 85
... REF The full range cannot be realized due the construction of the module. See Figure 7-10. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 7.11.3 OUTPUT CLAMPED TO V The CV output voltage can be set to Vss with no REF power consumption by configuring VRCON as follows: • VREN = 0 • VRR = 1 • ...
Page 86
... PIC12F635/PIC16F636/639 REGISTER 7-5: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 U-0 R/W-0 VREN — VRR bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 VREN: CV Enable bit REF circuit powered on REF circuit powered down REF bit 6 Unimplemented: Read as ‘0’ ...
Page 87
... TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 VRCON VREN — VRR Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used for comparator. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Bit 4 Bit 3 Bit 2 Bit 1 CINV CIS CM2 CM1 — — ...
Page 88
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 86 © 2007 Microchip Technology Inc. ...
Page 89
... DD PLVD Trip Point LVDIF Set by Hardware © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 The PLVD module includes the following capabilities: • Eight programmable trip points • Interrupt on falling V • Stable reference indication • Operation during Sleep A Block diagram of the PLVD module is shown in Figure 8-1 ...
Page 90
... PIC12F635/PIC16F636/639 8.1 PLVD Operation To setup the PLVD for operation, the following steps must be taken: • Enable the module by setting the LVDEN bit of the LVDCON register. • Configure the trip point by setting the LVDL<2:0> bits of the LVDCON register. • Wait for the reference voltage to become stable. ...
Page 91
... C2IF C1IF LVDCON — — IRVST Legend unknown unimplemented read as ‘0’. Shaded cells are not used by the PLVD module. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 R/W-0 U-0 R/W-1 (1) LVDEN — LVDL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 92
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 90 © 2007 Microchip Technology Inc. ...
Page 93
... EEDAT • EEADR EEDAT holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. PIC16F636/639 has 256 bytes of data EEPROM and the PIC12F635 has 128 bytes. REGISTER 9-1: EEDAT: EEPROM DATA REGISTER R/W-0 R/W-0 ...
Page 94
... PIC12F635/PIC16F636/639 9.1 EECON1 AND EECON2 Registers EECON1 is the control register with four low-order bits physically implemented. The upper four bits are non-implemented and read as ‘0’s. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation ...
Page 95
... EECON1,WR ;Start the write BSF INTCON,GIE ;Enable INTS © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 9.4 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM should be verified (see Example 9-3) to the desired value to be written. ...
Page 96
... PIC12F635/PIC16F636/639 9.5 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (nominal 64 ms duration) prevents EEPROM write ...
Page 97
... L Encoder License EE OQ Agreement”. ® The “K L Encoder License Agreement” may accessed through the Microchip web site located at www.microchip.com Further information may obtained by contacting your local Microchip Sales Representative. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 DS41232D-page 95 ...
Page 98
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 96 © 2007 Microchip Technology Inc. ...
Page 99
... The signal levels from all 3 channels are combined such that the limiter attenuates all 3 channels uniformly, in respect to the channel with the strongest signal. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 11.2 Modulation Circuit The modulation circuit consists of a modulation transistor (FET), internal tuning capacitors and external LC antenna components ...
Page 100
... PIC12F635/PIC16F636/639 11.6 AGC Control The AGC controls the variable attenuator to limit the internal signal voltage to avoid saturation of internal amplifiers and demodulators (Refer to Section 11.4 “Variable Attenuator”). The signal levels from all 3 channels are combined such that AGC attenuates all 3 channels uniformly in respect to the channel with the strongest signal ...
Page 101
... If the noise source is ignored, the AFE can return to a lower standby current draw state. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 The timer is reset when the: • CS pin is low (any SPI command). • Output enable filter is disabled. ...
Page 102
... PIC12F635/PIC16F636/639 FIGURE 11-1: FUNCTIONAL BLOCK DIAGRAM – ANALOG FRONT-END LCX Tune X RF Mod Lim LCCOM LCY Tune Y RF Mod Lim LCCOM LCZ Tune Z RF Mod Lim LCCOM AGC Preserve To Modulation Transistors To Tuning Cap X To Tuning Cap Y To Tuning Cap Z DS41232D-page 100 ...
Page 103
... FIGURE 11-2: LC INPUT PATH © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 DS41232D-page 101 ...
Page 104
... PIC12F635/PIC16F636/639 FIGURE 11-3: BIDIRECTIONAL PASSIVE KEYLESS ENTRY (PKE) SYSTEM APPLICATION EXAMPLE LED UHF Receiver LF Transmitter/ Receiver Base Station FIGURE 11-4: PASSIVE KEYLESS ENTRY (PKE) TRANSPONDER CONFIGURATION EXAMPLE +3V 315 MHz RF Circuitry (UHF TX) LFDATA/RSSI/CCLK/SDIO +3V air-core coil DS41232D-page 102 Ant. X Ant. Y Ant Data LED ...
Page 105
... Missing cycles may result in failing the output enable condition. FIGURE 11-5: OUTPUT ENABLE FILTER TIMING T STAB ( AGC PAGC Demodulator Output AFE Wake-up and AGC Stabilization © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 ) and OEH . OEH Required Output Enable Sequence T GAP t T OEH AGC Gap Pulse t T OET Data Packet ...
Page 106
... PIC12F635/PIC16F636/639 FIGURE 11-6: OUTPUT ENABLE FILTER TIMING EXAMPLE (DETAILED) 3.5 ms Low Current T AGC Standby (AGC settling time) Mode T STAB (AFE Stabilization) Legend AGC stabilization time AGC T = Time element of pulse AGC stabilization gap GAP T = Minimum output enable filter high time OEH T = Minimum output enable filter low time ...
Page 107
... OET - or T > T OEL OET • A Soft Reset SPI command is received. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 If the filter resets due to a long high (T high-pulse timer will not begin timing again until after a gap of T and another low-to-high transition occurs OET the demodulator output ...
Page 108
... PIC12F635/PIC16F636/639 TABLE 11-2: INPUT SENSITIVITY VS. MODULATED SIGNAL STRENGTH SETTING (AGCSIG <7>) AGCSIG<7> (Config. Register 5) Disabled – the AFE passes signal of any amplitude level it is capable of 0 detecting (demodulated data and carrier clock). Enabled – No output until AGC Status = 1 (i.e (demodulated data and carrier clock). ...
Page 109
... The 75% setting can reduce the bit errors caused by noise, but gives the least demodulation sensitivity. See Table 11-3 for minimum modulation depth requirement settings. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 TABLE 11-3: SETTING FOR MINIMUM MODULATION DEPTH REQUIREMENT MODMIN Bits (Config ...
Page 110
... PIC12F635/PIC16F636/639 FIGURE 11-7: MODULATION DEPTH EXAMPLES (a) Modulation Depth Definition Amplitude (b) LFDATA Output vs. Input vs. Minimum Modulation Depth Setting Amplitude Amplitude 0 DS41232D-page 108 Modulation Depth (%) = Coil Input Strength PP Modulation Depth (%) = t Input signal with modulation depth = 30% Demodulated LFDATA Output when MODMIN Setting = 25% (LFDATA output = toggled) ...
Page 111
... Configuration Register 5 1 Configuration Register 6 1 (Column Parity Register) © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 11.25 Error Detection of AFE Configuration Register Data The AFE’s Configuration registers are volatile memory. Therefore, the contents of the registers can be corrupted or cleared by any electrical incidence such as battery disconnect ...
Page 112
... PIC12F635/PIC16F636/639 11.26 Factory Calibration Microchip calibrates the AFE to device-to-device variation in standby current, internal timing and sensitivity, as well as channel-to-channel sensitivity variation. 11.27 De-Q’ing of Antenna Circuit When the transponder is close to the base station, the transponder coil may develop coil voltage higher than ...
Page 113
... Register 1 (Register 11-2) for more details. 11.31.1 DEMODULATOR OUTPUT The demodulator output is the default configuration of the output selection. This is the output of an envelope detection circuit. See Figure 11-9 for the demodulator output. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 ) For a clean data output or to save operating power, the input channels can be individually enabled or disabled ...
Page 114
... PIC12F635/PIC16F636/639 Case I. When Output Enable Filter is disabled: Demodulated output is available immediately after the AGC stabilization time (T ). Figure 11-10 shows an example of demodulated output when the Output Enable Filter is disabled. AGC FIGURE 11-10: INPUT SIGNAL AND DEMODULATOR OUTPUT WHEN THE OUTPUT ENABLE FILTER IS DISABLED ...
Page 115
... FILTER IS ENABLED AND INPUT MEETS FILTER TIMING REQUIREMENTS) Input Signal FIGURE 11-12: NO DEMODULATOR OUTPUT (WHEN OUTPUT ENABLE FILTER IS ENABLED BUT INPUT DOES NOT MEET FILTER TIMING REQUIREMENTS) Input Signal © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 LFDATA Output No LFDATA Output DS41232D-page 113 ...
Page 116
... PIC12F635/PIC16F636/639 11.31.2 CARRIER CLOCK OUTPUT When the Carrier Clock output is selected, the LFDATA output is a square pulse of the input carrier clock and available as soon as the AGC stabilization time (T completed. There are two Configuration register options for the carrier clock output: (a) clock divide-by one or (b) clock divide-by four, depending on bit DATOUT< ...
Page 117
... FIGURE 11-13: CARRIER CLOCK OUTPUT EXAMPLES (A) CARRIER CLOCK OUTPUT WITH CARRIER/1 OPTION Carrier Clock Output Carrier Input (B) CARRIER CLOCK OUTPUT WITH CARRIER/4 OPTION Carrier Clock Output Carrier Input © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 DS41232D-page 115 ...
Page 118
... PIC12F635/PIC16F636/639 11.31.3 RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) OUTPUT An analog current is available at the LFDATA pin when the Received Signal Strength Indicator (RSSI) output is selected for the AFE’s Configuration register. The analog current is linearly proportional to the input signal strength (see Figure 11-15). ...
Page 119
... FIGURE 11-15: RSSI OUTPUT CURRENT VS. INPUT SIGNAL LEVEL EXAMPLE © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Input Voltage ( DS41232D-page 117 ...
Page 120
... PIC12F635/PIC16F636/639 11.31.3.1 ANALOG-TO-DIGITAL DATA CONVERSION OF RSSI SIGNAL The AFE’s RSSI output is an analog current. It needs an external Analog-to-Digital (ADC) data conversion device for digitized output. The ADC data conversion can be accomplished by using a stand-alone external ADC device or by firmware utilizing MCU’s internal comparator along with a few external resistors and a capacitor ...
Page 121
... Clock in 16-bit SPI Write sequence - command, address, data and parity bit. • Command, address, data and parity bit. 5. Change LFDATA/RSSI/CCLK/SDIO connected pin to input. 6. Raise CS to complete the SPI Write. 7. Change SCLK/ALERT back to input. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 16 Clocks for Write Command, Address and Data 1/F SCLK T ...
Page 122
... PIC12F635/PIC16F636/639 FIGURE 11-18: SPI READ SEQUENCE Clocks for Read Command, T CSSC Address and Dummy Data T HI SCLK/ALERT MSb SCLK ALERT 1/F (input) (output LFDATA/RSSI/ CCLK/SDIO 3 LFDATA SDI (output) (input) MCU SPI Read Details: 1. Drive the AFE’s open collector ALERT output low. ...
Page 123
... Note: ‘P’ denotes the row parity bit (odd parity) for the respective data byte. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 The AFE operates in SPI mode 0,0. In mode 0,0 the clock idles in the low state (Figure 11-19). SDI data is loaded into the AFE on the rising edge of SCLK and SDO data is clocked out on the falling edge of SCLK ...
Page 124
... PIC12F635/PIC16F636/639 FIGURE 11-19: DETAILED SPI INTERFACE TIMING (AFE SCLK MSb SDIO Command 11.32.2.1 Clamp On Command This command results in activating (turning on) the modulation transistors of all enabled channels; channels enabled in Configuration Register 0 (Register 11-1). 11.32.2.2 Clamp Off Command This command results in de-activating (turning off) the modulation transistors of all channels ...
Page 125
... Enabled bit 1 LCXEN: LCX Enable bit 1 = Disabled 0 = Enabled bit 0 R0PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Bit 7 Bit 6 Bit 5 Bit 4 OEH OEL ALRTIND Channel X Tuning Capacitor ...
Page 126
... PIC12F635/PIC16F636/639 REGISTER 11-2: CONFIGURATION REGISTER 1 R/W-0 R/W-0 R/W-0 DATOUT1 DATOUT0 LCXTUN5 bit 8 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 8-7 DATOUT<1:0>: LFDATA Output type bit 00 = Demodulated output 01 = Carrier Clock output 10 = RSSI output 11 = RSSI output bit 6-1 LCXTUN< ...
Page 127
... R4PAR: Register Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits Note 1: Assured monotonic increment (or decrement) by design. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 R/W-0 R/W-0 R/W-0 LCZTUN4 LCZTUN3 LCZTUN2 U = Unimplemented bit, read as ‘0’ ...
Page 128
... PIC12F635/PIC16F636/639 REGISTER 11-6: CONFIGURATION REGISTER 5 R/W-0 R/W-0 R/W-0 AUTOCHSEL AGCSIG MODMIN1 bit 8 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 8 AUTOCHSEL: Auto Channel Select bit 1 = Enabled – AFE selects channel(s) that has demodulator output “high” at the end of T channel(s Disabled – ...
Page 129
... Soft Reset Executed 0 Legend unchanged Note 1: See Section 11.20 “Soft Reset” and Section 11.32.2.4 “Soft Reset Command” for the condition of Soft Reset execution. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 R-0 R-0 R-0 AGCACT WAKEZ WAKEY U = Unimplemented bit, read as ‘0’ ...
Page 130
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 128 © 2007 Microchip Technology Inc. ...
Page 131
... SPECIAL FEATURES OF THE CPU The PIC12F635/PIC16F636/639 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Wake-up Reset (WUR) - Power-up Timer (PWRT) ...
Page 132
... PIC12F635/PIC16F636/639 REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER — — — bit 15 CPD CP MCLRE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘1’ bit 12 WURE: Wake-up Reset Enable bit 1 = Standard wake-up and continue enabled ...
Page 133
... Reset The PIC12F635/PIC16F636/639 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) Wake-up Reset (WUR) c) WDT Reset during normal operation d) WDT Reset during Sleep e) MCLR Reset during normal operation f) MCLR Reset during Sleep g) Brown-out Reset (BOR) Some registers are not affected in any Reset condition; ...
Page 134
... MCLR pin, rather than pulling this pin directly to V 12.5 MCLR PIC12F635/PIC16F636/639 has a noise filter in the MCLR Reset path. The filter will ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. See Figure 12-2 for the recommended MCLR circuit ...
Page 135
... FIGURE 12-2: RECOMMENDED MCLR CIRCUIT V DD PIC12F635/PIC16F636/639 greater) MCLR C1 0.1 F (optional, not critical) © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 DS41232D-page 133 ...
Page 136
... PIC12F635/PIC16F636/639 12.6 Brown-out Reset (BOR) The BOREN0 and BOREN1 bits in the Configuration Word register select one of four BOR modes. Two modes have been added to allow software or hardware control of the BOR enable. When BOREN<1:0> = 01, the SBOREN bit of the PCON register enables/disables the BOR allowing controlled in software. By selecting BOREN< ...
Page 137
... MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more PIC12F635/PIC16F636/639 device operating in parallel. Table 12-5 shows the Reset conditions for some special registers, while Table 12-4 shows the Reset conditions for all the registers. TABLE 12-1: ...
Page 138
... PIC12F635/PIC16F636/639 FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR ...
Page 139
... See Table 12-5 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit PIC16F636/639 only. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 MCLR Reset WDT Reset (1) Brown-out Reset Wake-up Reset uuuu uuuu xxxx xxxx ...
Page 140
... PIC12F635/PIC16F636/639 TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep Wake-up Reset Legend unchanged unknown, – = unimplemented bit, reads as ‘0’. ...
Page 141
... Interrupts The PIC12F635/PIC16F636/639 has multiple interrupt sources: • External Interrupt RA2/INT • Timer0 Overflow Interrupt • PORTA Change Interrupts • 2 Comparator Interrupts • Timer1 Overflow Interrupt • EEPROM Data Write Interrupt • Fail-Safe Clock Monitor Interrupt The Interrupt Control register (INTCON) and Peripheral Interrupt Request Register 1 (PIR1) record individual interrupt requests in flag bits ...
Page 142
... PIC12F635/PIC16F636/639 12.9.2 TIMER INTERRUPT An overflow (FFh 00h) in the TMR0 register will set the T0IF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing T0IE bit of the INTCON register. See Section 5.0 “Timer0 Module” for operation of the Timer0 module. FIGURE 12-7: ...
Page 143
... IOCA5 PIR1 EEIF LVDIF CRIF PIE1 EEIE LVDIE CRIE Legend unknown unchanged, – = unimplemented, read as ‘0’ value depends upon condition. Shaded cells are not used by the Interrupt module. Note 1: PIC16F636/639 only. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 (1) (2) Interrupt Latency Inst ( — ...
Page 144
... W and STATUS registers). This must be implemented in software. Since the lower 16 bytes of all banks are common in the PIC12F635/PIC16F636/639 (see Figure 2-2), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here. These 16 locations do not require banking and therefore, make it easier to context save and restore ...
Page 145
... Watchdog Timer (WDT) The PIC12F635/PIC16F636/639 WDT is code and functionally compatible with other PIC16F WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to have a scaler value for the WDT and TMR0 at the same time. In addition, the WDT time-out value can be extended to 268 seconds ...
Page 146
... PIC12F635/PIC16F636/639 REGISTER 12-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate ...
Page 147
... Interrupt-on-change. 6. External Interrupt from INT pin. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Other peripherals cannot generate interrupts, since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction ( prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
Page 148
... PIC12F635/PIC16F636/639 FIGURE 12-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT OSC1 (4) CLKOUT INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW Instruction Inst(PC) = Sleep Inst( Fetched Instruction Sleep Inst(PC – 1) Executed Note 1: XT Oscillator mode assumed 1024 T (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. ...
Page 149
... In-Circuit Serial Programming The PIC12F635/PIC16F636/639 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for: • Power • Ground • Programming Voltage This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product ...
Page 150
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 148 © 2007 Microchip Technology Inc. ...
Page 151
... INSTRUCTION SET SUMMARY The PIC12F635/PIC16F636/639 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction ...
Page 152
... PIC12F635/PIC16F636/639 TABLE 13-2: PIC12F635/PIC16F636/639 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW – Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ ...
Page 153
... Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 BCF Syntax: k Operands: Operation: Status Affected: Description: ...
Page 154
... PIC12F635/PIC16F636/639 BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands 127 0 b < 7 Operation: skip if (f<b> Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next ...
Page 155
... Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 INCFSZ Increment f, Skip if 0 Syntax: [ label ] Operands: 0 ...
Page 156
... PIC12F635/PIC16F636/639 MOVF Move f Syntax: [ label ] MOVF f,d Operands 127 d [0,1] Operation: (f) (dest) Status Affected: Z Description: The contents of register f is moved to a destination dependent upon the status destination is W register the destination is file register f itself useful to test a file register since status flag Z is affected ...
Page 157
... Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 RETLW Return with literal in W Syntax: [ label ] Operands Operation: k (W); TOS Status Affected: None Description: The W register is loaded with the eight-bit literal ‘ ...
Page 158
... PIC12F635/PIC16F636/639 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d Operands 127 d [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. ...
Page 159
... The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 XORLW Syntax: Operands: Operation: Status Affected: Description: f< ...
Page 160
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 158 © 2007 Microchip Technology Inc. ...
Page 161
... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 14.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 162
... PIC12F635/PIC16F636/639 14.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
Page 163
... Microchip Technology Inc. PIC12F635/PIC16F636/639 14.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, ...
Page 164
... PIC12F635/PIC16F636/639 14.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins. ...
Page 165
... Maximum LC Input Voltage (LCX, LCY, LCZ) Maximum LC Input Voltage (LCX, LCY, LCZ) Maximum Input Current (rms) into device per LC Channel Human Body ESD rating ........................................................................................................................ 4000 (min.) V Machine Model ESD rating ...................................................................................................................... 400 (min.) V Note 1: Power dissipation for PIC12F635/PIC16F636/639 (AFE section not included) is calculated as follows: - ∑ ∑ {( ...
Page 166
... PIC12F635/PIC16F636/639 FIGURE 15-1: PIC12F635/16F636 VOLTAGE-FREQUENCY GRAPH, -40°C 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Cross-hatched area is for HFINTOSC and EC modes only. FIGURE 15-2: PIC16F639 VOLTAGE-FREQUENCY GRAPH, -40°C T 5.5 5.0 4.5 4 ...
Page 167
... FIGURE 15-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE V 125 -40 2.0 2.5 © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 ± 5% ± 2% ± 1% 3.0 3.5 4.0 4.5 V (V) DD AND TEMPERATURE DD 5.0 5.5 DS41232D-page 165 ...
Page 168
... PIC12F635/PIC16F636/639 15.1 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) PIC12F635/PIC16F636-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Supply Voltage DD D001 D001A D001B D001C D002 V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 S V Rise Rate to ensure VDD DD internal Power-on Reset ...
Page 169
... DC Characteristics: PIC12F635/PIC16F636-I (Industrial) DC CHARACTERISTICS Param Sym Device Characteristics No. (1,2) D010 I Supply Current DD D011 D012 D013 D014 D015 D016 D017 D018 D019 † Data in “Typ” column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested. ...
Page 170
... PIC12F635/PIC16F636/639 15.2 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) (Continued) DC CHARACTERISTICS Param Sym Device Characteristics No. D020 I Power-down Base PD (4) Current D021 D022A D022B D023 D024A D024B D025 † Data in “Typ” column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested. ...
Page 171
... DC Characteristics: PIC12F635/PIC16F636-E (Extended) DC CHARACTERISTICS Param Sym Device Characteristics No. (1,2) D010E I Supply Current DD D011E D012E D013E D014E D015E D016E D017E D018E D019E † Data in “Typ” column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested. ...
Page 172
... PIC12F635/PIC16F636/639 15.3 DC Characteristics: PIC12F635/PIC16F636-E (Extended) (Continued) DC CHARACTERISTICS Param Sym Device Characteristics No. D020 I Power-down Base PD (4) Current D021 D022A D022B D023 D024A D024B D025 † Data in “Typ” column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested. ...
Page 173
... DC Characteristics: PIC12F635/PIC16F636-I (Industrial) PIC12F635/PIC16F636-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Input Low Voltage IL I/O ports: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (RC mode) D033 OSC1 (XT and LP modes) (1) D033A OSC1 (HS mode) V Input High Voltage IH I/O ports: ...
Page 174
... PIC12F635/PIC16F636/639 15.4 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) PIC12F635/PIC16F636-E (Extended) (Continued) DC CHARACTERISTICS Param Sym Characteristic No. V Output High Voltage OH D090 I/O ports D092 OSC2/CLKOUT (RC mode) D100 I Ultra Low-power Wake-up ULP Current Capacitive Loading Specs on Output Pins D101 COSC2 OSC2 pin D101A C All I/O pins ...
Page 175
... Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which V DD © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C Min Typ† Max Units 2.0 — ...
Page 176
... PIC12F635/PIC16F636/639 15.6 DC Characteristics: PIC16F639-I (Industrial) DC CHARACTERISTICS Param Sym Device Characteristics No. (1,2,3) D010 I Supply Current DD D011 D012 D013 D014 D015 D016 D017 D020 I Power-down Base Current PD D021 IWDT D022A IBOR D022B ILVD D023 ICMP D024A IV REFHS D024B IV REFLS D025 IT1OSC D026 I Active Current of AFE only ...
Page 177
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 9.4.1 “Using the Data EEPROM” for additional information © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C Supply Voltage 2 ...
Page 178
... PIC12F635/PIC16F636/639 15.7 DC Characteristics: PIC16F639-I (Industrial) (Continued) DC CHARACTERISTICS Param Sym Characteristic No. V Output High Voltage OH D090 I/O ports D092 OSC2/CLKOUT (RC mode) Digital Output High Voltage D093 LFDATA/SDIO for Analog Front-End (AFE) Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin D101 C All I/O pins ...
Page 179
... QFN 4x0.9mm package PIC16F639 108.1 °C/W 20-pin SSOP package 41.2 °C/W 8-pin PDIP package 38.8 °C/W 8-pin SOIC package PIC12F635 3.0 °C/W 8-pin DFN 4x4x0.9 mm package 3.0 °C/W 8-pin DFN-S 6x5 mm package 32.5 °C/W 14-pin PDIP package 31.0 ° ...
Page 180
... PIC12F635/PIC16F636/639 15.9 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings Fall ...
Page 181
... AC Characteristics: PIC12F635/PIC16F636/639 (Industrial, Extended) FIGURE 15-5: CLOCK TIMING Q4 OSC1/CLKIN OSC2/CLKOUT (LP, XT, HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 15-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C T Param Sym Characteristic No. OS01 F External CLKIN Frequency OSC (1) Oscillator Frequency ...
Page 182
... PIC12F635/PIC16F636/639 TABLE 15-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristic No. OS06 T Internal Oscillator Switch WARM (3) when running OS07 T Fail-Safe Sample Clock SC (1) Period OS08 HF Internal Calibrated OSC HFINTOSC Frequency OS09* LF Internal Uncalibrated OSC LFINTOSC Frequency ...
Page 183
... These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output Includes OSC2 in CLKOUT mode. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Fetch Read Q1 Q2 OS11 OS20 ...
Page 184
... PIC12F635/PIC16F636/639 FIGURE 15-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out OSC Start-Up Time (1) Internal Reset Watchdog Timer (1) Reset I/O pins Note 1: Asserted low. FIGURE 15-8: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) ...
Page 185
... OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices design. 3: Period of the slower clock ensure these voltage tolerances, V possible. 0.1 F and 0.01 F values in parallel are recommended. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 +125°C Min Typ† Max Units 2 — — 5 — ...
Page 186
... PIC12F635/PIC16F636/639 FIGURE 15-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI T1CKI TMR0 or TMR1 TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristic No. 40 T0CKI High Pulse Width T 41 T0CKI Low Pulse Width ...
Page 187
... Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’. 2: See Section 7.11 “Comparator Voltage Reference” for more information. TABLE 15-8: PIC12F635/PIC16F636 PLVD CHARACTERISTICS: DC CHARACTERISTICS Sym. Characteristic V PLVD LVDL<2:0> = 001 ...
Page 188
... PIC12F635/PIC16F636/639 TABLE 15-9: PIC16F639 PLVD CHARACTERISTICS: DC CHARACTERISTICS Sym. Characteristic V PLVD LVDL<2:0> = 001 PLVD Voltage LVDL<2:0> = 010 LVDL<2:0> = 011 LVDL<2:0> = 100 LVDL<2:0> = 101 LVDL<2:0> = 110 LVDL<2:0> = 111 *T PLVD Settling time PLVDS * These parameters are characterized but not tested † Data in “Typ” column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 189
... Required output enable filter high time must account for input path analog delays (= T 2: Required output enable filter low time must account for input path analog delays (= T © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Standard Operating Conditions (unless otherwise stated) Supply Voltage 2. ...
Page 190
... PIC12F635/PIC16F636/639 15.11 AC Characteristics: Analog Front-End for PIC16F639 (Industrial) (Continued) AC CHARACTERISTICS Param Sym. Characteristic No. AF14 T R Rise time of LFDATA LFDATA AF15 T F Fall time of LFDATA LFDATA AF16 T AGC initialization time AGC AF17 T High time after AGC settling time PAGC AF18 T AGC stabilization time plus high ...
Page 191
... Required output enable filter high time must account for input path analog delays (= T 2: Required output enable filter low time must account for input path analog delays (= T © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Standard Operating Conditions (unless otherwise stated) Supply Voltage 2. ...
Page 192
... PIC12F635/PIC16F636/639 15.12 SPI Timing: Analog Front-End (AFE) for PIC16F639 AC CHARACTERISTICS Param Sym Characteristic F SCLK Frequency AF33 SCLK Tcssc AF34 CS fall to first SCLK edge setup time T SDI setup time AF35 SU T SDI hold time AF36 HD T SCLK high time AF37 HI T SCLK low time ...
Page 193
... Typical: Statistical Mean @25°C 3.0 Maximum: Mean (Worst Case Temp (-40°C to 125°C) 2.5 2.0 1.5 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 vs. F OVER V (EC MODE) OSC DD 6 MHz 8 MHz 10 MHz 12 MHz F OSC 5.5V 5.0V 4 ...
Page 194
... PIC12F635/PIC16F636/639 FIGURE 16-2: MAXIMUM I DD 4.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp 3.5 (-40°C to 125°C) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz FIGURE 16-3: TYPICAL I DD 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst Case Temp (-40° ...
Page 195
... Maximum: Mean (Worst Case Temp (-40°C to 125°C) 700 600 500 400 300 200 100 0 2.0 2.5 © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 vs. F OVER V (HS MODE) OSC DD Maximum IDD vs FOSC Over Vdd HS Mode 4.0V 3.5V 3.0V 10 MHz 16 MHz F OSC vs ...
Page 196
... PIC12F635/PIC16F636/639 FIGURE 16-6: MAXIMUM I DD 1,400 Typical: Statistical Mean @25°C 1,200 Maximum: Mean (Worst Case Temp (-40°C to 125°C) 1,000 800 600 400 200 0 2.0 2.5 FIGURE 16-7: TYPICAL I DD 800 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp 700 (-40° ...
Page 197
... OVER Typical: Statistical Mean @25°C 70 Maximum: Mean (Worst Case Temp (-40°C to 125° 2.0 2.5 © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 vs. V OVER F (EXTRC MODE) DD OSC EXTRC Mode 4 MHz 1 MHz 3.0 3.5 4.0 V (V) DD (LFINTOSC MODE, 31 kHz) OSC LFINTOSC Mode, 31KHZ ...
Page 198
... PIC12F635/PIC16F636/639 FIGURE 16-10: I vs. V OVER Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp (-40°C to 125° 2.0 2.5 FIGURE 16-11: TYPICAL I DD 1,600 Typical: Statistical Mean @25°C 1,400 Maximum: Mean (Worst Case Temp (-40°C to 125°C) 1,200 1,000 800 600 ...
Page 199
... Maximum: Mean (Worst Case Temp (-40°C to 125°C) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.0 2.0 2.5 © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 vs. F OVER V (HFINTOSC MODE) OSC DD HFINTOSC 500 kHz 1 MHz 2 MHz F OSC vs. V (SLEEP MODE, ALL PERIPHERALS DISABLED) ...
Page 200
... PIC12F635/PIC16F636/639 FIGURE 16-14: MAXIMUM I PD 18.0 Typical: Statistical Mean @25°C Maximum: Mean + 3 16.0 Maximum: Mean (Worst Case Temp (-40°C to 125°C) 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 2.0 2.5 FIGURE 16-15: COMPARATOR I 180 160 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp (-40° ...