AT89C2051-24PU Atmel, AT89C2051-24PU Datasheet - Page 5

IC MCU 2K FLASH 24MHZ 20-DIP

AT89C2051-24PU

Manufacturer Part Number
AT89C2051-24PU
Description
IC MCU 2K FLASH 24MHZ 20-DIP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C2051-24PU

Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
UART/USART
Peripherals
LED
Number Of I /o
15
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
UART
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
15
Number Of Timers
2
Operating Supply Voltage
2.7 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Package
20PDIP
Device Core
8051
Family Name
89C
Maximum Speed
24 MHz
Cpu Family
89C
Device Core Size
8b
Frequency (max)
24MHz
Total Internal Ram Size
128Byte
# I/os (max)
15
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
6V
Operating Supply Voltage (min)
4V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
20
Package Type
PDIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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6. Special Function Registers
Table 6-1.
0368H–MICRO–6/08
0D8H
0D0H
0C8H
0C0H
0F8H
0F0H
0E8H
0E0H
0B8H
0B0H
0A8H
0A0H
98H
90H
88H
80H
XXX00000
0XX00000
00000000
00000000
00000000
11111111
00000000
11111111
00000000
SCON
TCON
PSW
ACC
P3
P1
IP
IE
B
AT89C2051 SFR Map and Reset Values
XXXXXXXX
00000000
00000111
TMOD
SBUF
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in
the table below.
Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-
mented on the chip. Read accesses to these addresses will in general return random data, and
write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future
products to invoke new features. In that case, the reset or inactive values of the new bits will
always be 0.
SP
00000000
00000000
DPL
TL0
00000000
00000000
DPH
TL1
00000000
TH0
00000000
TH1
AT89C2051
0XXX0000
PCON
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
97H
8FH
87H
5

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