IC MCU 2K FLASH 24MHZ 20-DIP

AT89C2051-24PU

Manufacturer Part NumberAT89C2051-24PU
DescriptionIC MCU 2K FLASH 24MHZ 20-DIP
ManufacturerAtmel
Series89C
AT89C2051-24PU datasheet
 


Specifications of AT89C2051-24PU

Core Processor8051Core Size8-Bit
Speed24MHzConnectivityUART/USART
PeripheralsLEDNumber Of I /o15
Program Memory Size2KB (2K x 8)Program Memory TypeFLASH
Ram Size128 x 8Voltage - Supply (vcc/vdd)4 V ~ 6 V
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-DIP (0.300", 7.62mm)Processor SeriesAT89x
Core8051Data Bus Width8 bit
Data Ram Size128 BInterface TypeUART
Maximum Clock Frequency24 MHzNumber Of Programmable I/os15
Number Of Timers2Operating Supply Voltage2.7 V to 6 V
Maximum Operating Temperature+ 85 CMounting StyleThrough Hole
3rd Party Development ToolsPK51, CA51, A51, ULINK2Minimum Operating Temperature- 40 C
Package20PDIPDevice Core8051
Family Name89CMaximum Speed24 MHz
Cpu Family89CDevice Core Size8b
Frequency (max)24MHzTotal Internal Ram Size128Byte
# I/os (max)15Number Of Timers - General Purpose2
Operating Supply Voltage (typ)5VOperating Supply Voltage (max)6V
Operating Supply Voltage (min)4VInstruction Set ArchitectureCISC
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
MountingThrough HolePin Count20
Package TypePDIPLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
Page 6/19

Download datasheet (382Kb)Embed
PrevNext
7. Restrictions on Certain Instructions
The AT89C2051 and is an economical and cost-effective member of Atmel’s growing family of
microcontrollers. It contains 2K bytes of Flash program memory. It is fully compatible with the
MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However,
there are a few considerations one must keep in mind when utilizing certain instructions to pro-
gram this device.
All the instructions related to jumping or branching should be restricted such that the destination
address falls within the physical program memory space of the device, which is 2K for the
AT89C2051. This should be the responsibility of the software programmer. For example, LJMP
7E0H would be a valid instruction for the AT89C2051 (with 2K of memory), whereas LJMP 900H
would not.
7.1
Branching Instructions
LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR – These unconditional branching
instructions will execute correctly as long as the programmer keeps in mind that the destination
branching address must fall within the physical boundaries of the program memory size (loca-
tions 00H to 7FFH for the 89C2051). Violating the physical space limits may cause unknown
program behavior.
CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ – With these conditional branching
instructions the same rule above applies. Again, violating the memory boundaries may cause
erratic execution.
For applications involving interrupts the normal interrupt service routine address locations of the
80C51 family architecture have been preserved.
7.2
MOVX-related Instructions, Data Memory
The AT89C2051 contains 128 bytes of internal data memory. Thus, in the AT89C2051 the stack
depth is limited to 128 bytes, the amount of available RAM. External DATA memory access is
not supported in this device, nor is external PROGRAM memory execution. Therefore, no MOVX
[...] instructions should be included in the program.
A typical 80C51 assembler will still assemble instructions, even if they are written in violation of
the restrictions mentioned above. It is the responsibility of the controller user to know the physi-
cal features and limitations of the device being used and adjust the instructions used
correspondingly.
8. Program Memory Lock Bits
On the chip are two lock bits which can be left unprogrammed (U) or can be programmed (P) to
obtain the additional features listed in the
Table 8-1.
1
2
3
Note:
AT89C2051
6
Table
(1)
Lock Bit Protection Modes
Program Lock Bits
LB1
LB2
Protection Type
U
U
No program lock features
P
U
Further programming of the Flash is disabled
P
P
Same as mode 2, also verify is disabled
1. The Lock Bits can only be erased with the Chip Erase operation.
8-1.
0368H–MICRO–6/08