IC MCU 2K FLASH 24MHZ 20-DIP

AT89C2051-24PU

Manufacturer Part NumberAT89C2051-24PU
DescriptionIC MCU 2K FLASH 24MHZ 20-DIP
ManufacturerAtmel
Series89C
AT89C2051-24PU datasheet
 


Specifications of AT89C2051-24PU

Core Processor8051Core Size8-Bit
Speed24MHzConnectivityUART/USART
PeripheralsLEDNumber Of I /o15
Program Memory Size2KB (2K x 8)Program Memory TypeFLASH
Ram Size128 x 8Voltage - Supply (vcc/vdd)4 V ~ 6 V
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-DIP (0.300", 7.62mm)Processor SeriesAT89x
Core8051Data Bus Width8 bit
Data Ram Size128 BInterface TypeUART
Maximum Clock Frequency24 MHzNumber Of Programmable I/os15
Number Of Timers2Operating Supply Voltage2.7 V to 6 V
Maximum Operating Temperature+ 85 CMounting StyleThrough Hole
3rd Party Development ToolsPK51, CA51, A51, ULINK2Minimum Operating Temperature- 40 C
Package20PDIPDevice Core8051
Family Name89CMaximum Speed24 MHz
Cpu Family89CDevice Core Size8b
Frequency (max)24MHzTotal Internal Ram Size128Byte
# I/os (max)15Number Of Timers - General Purpose2
Operating Supply Voltage (typ)5VOperating Supply Voltage (max)6V
Operating Supply Voltage (min)4VInstruction Set ArchitectureCISC
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
MountingThrough HolePin Count20
Package TypePDIPLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
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9. Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The
mode is invoked by software. The content of the on-chip RAM and all the special functions regis-
ters remain unchanged during this mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
The P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if
external pull-ups are used.
It should be noted that when idle is terminated by a hardware reset, the device normally
resumes program execution, from where it left off, up to two machine cycles before the internal
reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a
port pin when Idle is terminated by reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external memory.
10. Power-down Mode
In the power-down mode the oscillator is stopped, and the instruction that invokes power-down
is the last instruction executed. The on-chip RAM and Special Function Registers retain their
values until the power-down mode is terminated. The only exit from power-down is a hardware
reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be
activated before V
enough to allow the oscillator to restart and stabilize.
The P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if
external pull-ups are used.
11. Programming The Flash
The AT89C2051 is shipped with the 2K bytes of on-chip PEROM code memory array in the
erased state (i.e., contents = FFH) and ready to be programmed. The code memory array is pro-
grammed one byte at a time. Once the array is programmed, to re-program any non-blank byte,
the entire memory array needs to be erased electrically.
Internal Address Counter: The AT89C2051 contains an internal PEROM address counter
which is always reset to 000H on the rising edge of RST and is advanced by applying a positive
going pulse to pin XTAL1.
Programming Algorithm: To program the AT89C2051, the following sequence is
recommended.
1. Power-up sequence:
Apply power between V
Set RST and XTAL1 to GND
2. Set pin RST to “H”
Set pin P3.2 to “H”
3. Apply the appropriate combination of “H” or “L” logic
levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the programming operations
shown in the PEROM Programming Modes table.
0368H–MICRO–6/08
is restored to its normal operating level and must be held active long
CC
and GND pins
CC
AT89C2051
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