Manufacturer Part NumberAT89C2051-24PU
DescriptionIC MCU 2K FLASH 24MHZ 20-DIP
AT89C2051-24PU datasheet

Specifications of AT89C2051-24PU

Core Processor8051Core Size8-Bit
PeripheralsLEDNumber Of I /o15
Program Memory Size2KB (2K x 8)Program Memory TypeFLASH
Ram Size128 x 8Voltage - Supply (vcc/vdd)4 V ~ 6 V
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-DIP (0.300", 7.62mm)Processor SeriesAT89x
Core8051Data Bus Width8 bit
Data Ram Size128 BInterface TypeUART
Maximum Clock Frequency24 MHzNumber Of Programmable I/os15
Number Of Timers2Operating Supply Voltage2.7 V to 6 V
Maximum Operating Temperature+ 85 CMounting StyleThrough Hole
3rd Party Development ToolsPK51, CA51, A51, ULINK2Minimum Operating Temperature- 40 C
Package20PDIPDevice Core8051
Family Name89CMaximum Speed24 MHz
Cpu Family89CDevice Core Size8b
Frequency (max)24MHzTotal Internal Ram Size128Byte
# I/os (max)15Number Of Timers - General Purpose2
Operating Supply Voltage (typ)5VOperating Supply Voltage (max)6V
Operating Supply Voltage (min)4VInstruction Set ArchitectureCISC
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
MountingThrough HolePin Count20
Package TypePDIPLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
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To Program and Verify the Array:
4. Apply data for Code byte at location 000H to P1.0 to P1.7.
5. Raise RST to 12V to enable programming.
6. Pulse P3.2 once to program a byte in the PEROM array or the lock bits. The byte-write
cycle is self-timed and typically takes 1.2 ms.
7. To verify the programmed data, lower RST from 12V to logic “H” level and set pins P3.3
to P3.7 to the appropriate levels. Output data can be read at the port P1 pins.
8. To program a byte at the next address location, pulse XTAL1 pin once to advance the
internal address counter. Apply new data to the port P1 pins.
9. Repeat steps 6 through 8, changing data and advancing the address counter for the
entire 2K bytes array or until the end of the object file is reached.
10. Power-off sequence:
set XTAL1 to “L”
set RST to “L”
Turn V
Data Polling: The AT89C2051 features Data Polling to indicate the end of a write cycle. During
a write cycle, an attempted read of the last byte written will result in the complement of the writ-
ten data on P1.7. Once the write cycle has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.
Ready/Busy: The Progress of byte programming can also be monitored by the RDY/BSY output
signal. Pin P3.1 is pulled low after P3.2 goes High during programming to indicate BUSY. P3.1 is
pulled High again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed code data can be read
back via the data lines for verification:
1. Reset the internal address counter to 000H by bringing RST from “L” to “H”.
2. Apply the appropriate control signals for Read Code data and read the output data at
the port P1 pins.
3. Pulse pin XTAL1 once to advance the internal address counter.
4. Read the next code data byte at the port P1 pins.
5. Repeat steps 3 and 4 until the entire array is read.
The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that
their features are enabled.
Chip Erase: The entire PEROM array (2K bytes) and the two Lock Bits are erased electrically
by using the proper combination of control signals and by holding P3.2 low for 10 ms. The code
array is written with all “1”s in the Chip Erase operation and must be executed before any non-
blank memory byte can be re-programmed.
Reading the Signature Bytes: The signature bytes are read by the same procedure as a nor-
mal verification of locations 000H, 001H, and 002H, except that P3.5 and P3.7 must be pulled to
a logic low. The values returned are as follows.
(000H) = 1EH indicates manufactured by Atmel
(001H) = 21H indicates 89C2051
power off