IC MCU AVR 4K FLASH 28PDIP

ATMEGA48A-PU

Manufacturer Part NumberATMEGA48A-PU
DescriptionIC MCU AVR 4K FLASH 28PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA48A-PU datasheets
 


Specifications of ATMEGA48A-PU

Core ProcessorAVRCore Size8-Bit
Speed20MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o23
Program Memory Size4KB (2K x 16)Program Memory TypeFLASH
Eeprom Size256 x 8Ram Size512 x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 6x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case28-DIP (0.300", 7.62mm)Controller Family/seriesAtmega
No. Of I/o's23Eeprom Memory Size256Byte
Ram Memory Size512ByteCpu Speed20MHz
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
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Features
High Performance, Low Power AVR
Advanced RISC Architecture
– 131 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory Segments
– 4/8/16/32K Bytes of In-System Self-Programmable Flash program memory
– 256/512/512/1K Bytes EEPROM
– 512/1K/1K/2K Bytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel 10-bit ADC in TQFP and QFN/MLF package
Temperature Measurement
– 6-channel 10-bit ADC in PDIP Package
Temperature Measurement
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface (Philips I
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
I/O and Packages
– 23 Programmable I/O Lines
– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
Operating Voltage:
– 1.8 - 5.5V
Temperature Range:
°
°
– -40
C to 85
C
Speed Grade:
– 0 - 4 MHz@1.8 - 5.5V, 0 - 10 MHz@2.7 - 5.5.V, 0 - 20 MHz @ 4.5 - 5.5V
Power Consumption at 1 MHz, 1.8V, 25°C
– Active Mode: 0.2 mA
– Power-down Mode: 0.1 µA
– Power-save Mode: 0.75 µA (Including 32 kHz RTC)
®
8-Bit Microcontroller
(1)
2
C compatible)
8-bit
Microcontroller
with 4/8/16/32K
Bytes In-System
Programmable
Flash
ATmega48A
ATmega48PA
ATmega88A
ATmega88PA
ATmega168A
ATmega168PA
ATmega328
ATmega328P
Rev. 8271C–AVR–08/10

ATMEGA48A-PU Summary of contents

  • Page 1

    ... Active Mode: 0.2 mA – Power-down Mode: 0.1 µA – Power-save Mode: 0.75 µA (Including 32 kHz RTC) ® 8-Bit Microcontroller ( compatible) 8-bit Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash ATmega48A ATmega48PA ATmega88A ATmega88PA ATmega168A ATmega168PA ATmega328 ATmega328P Rev. 8271C–AVR–08/10 ...

  • Page 2

    ... PC1 (ADC1/PCINT9 PC0 (ADC0/PCINT8) 18 GND AREF 6 16 AVCC (PCINT6/XTAL1/TOSC1) PB6 15 PB5 (SCK/PCINT5) 7 (PCINT7/XTAL2/TOSC2) PB7 NOTE: Bottom pad should be soldered to ground. 32UFBGA - Pinout ATmega48A/48PA/88A/88PA/168A/168PA 1 2 PD2 PD1 PC6 PD3 PD4 PD0 GND GND VDD VDD PB6 PD6 PB0 PB7 PD5 PD7 28 PDIP ...

  • Page 3

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 1.1 Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability ...

  • Page 4

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The various special features of Port D are elaborated in 89. 1.1 the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally CC connected to V through a low-pass filter. Note that PC6...4 use digital supply voltage, V 1.1.8 AREF AREF is the analog reference pin for the A/D Converter. ...

  • Page 5

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 2. Overview The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P is a low-power CMOS 8-bit microcon- troller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P achieves through- puts approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...

  • Page 6

    ... Atmel ATmega48A/48PA/88A/88PA/168A/168PA/328/328P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded con- trol applications. The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. ...

  • Page 7

    ... ATmega168PA ATmega328 ATmega328P ATmega48A/48PA/88A/88PA/168A/168PA/328/328P support a real Read-While-Write Self-Pro- gramming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega 48A/48PA there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash. ...

  • Page 8

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 6. AVR CPU Core 6.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 6-1. ...

  • Page 9

    ... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...

  • Page 10

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ...

  • Page 11

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 6.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • ...

  • Page 12

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 6.4.1 The X-register, Y-register, and Z-register The registers R26...R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 6-3 ...

  • Page 13

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 6.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value 6.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip ...

  • Page 14

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 6.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt ...

  • Page 15

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example in r16, SREG cli sbi EECR, EEMPE sbi EECR, EEPE out SREG, r16 C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */ When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example ...

  • Page 16

    ... Store Program Memory Control and Status Register” on page 294 The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P Program Counter (PC) is 11/12/13/14 bits wide, thus addressing the 2/4/8/16K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in gramming the Flash, ATmega 48A/48PA” ...

  • Page 17

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 7-1. Figure 7-2. 8271C–AVR–08/10 Program Memory Map ATmega 48A/48PA Program Memory Application Flash Section Program Memory Map ATmega88A, ATmega88PA, ATmega168A, ATmega168PA, ATmega328 and ATmega328P Program Memory Application Flash Section Boot Flash Section 0x0000 0x7FF 0x0000 0x0FFF/0x1FFF/0x3FFF 17 ...

  • Page 18

    ... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and ATmega48A/48PA/88A/88PA/168A/168PA/328/328P are all accessible through all these addressing modes. The Register File is described in 11. Figure 7-3. ...

  • Page 19

    ... Figure 7-4. 7.4 EEPROM Data Memory The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P contains 256/512/512/1K bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. ” ...

  • Page 20

    ... I/O Memory The I/O space definition of the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P is shown in ”Register Summary” on page All ATmega48A/48PA/88A/88PA/168A/168PA/328/328P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space ...

  • Page 21

    ... EEDR contains the data read out from the EEPROM at the address given by EEAR. 7.6.3 EECR – The EEPROM Control Register Bit 0x1F (0x3F) Read/Write Initial Value • Bits 7:6 – Reserved These bits are reserved bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and will always read as zero. 8271C–AVR–08/ – ...

  • Page 22

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be trig- gered when writing EEPE possible to program data in one atomic operation (erase the old value and program the new value split the Erase and Write operations in two different operations ...

  • Page 23

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems ...

  • Page 24

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData 8271C–AVR–08/10 ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ...

  • Page 25

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned char EEPROM_read(unsigned int uiAddress 7.6.4 GPIOR2 – ...

  • Page 26

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 8. System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ment and Sleep Modes” on page Figure 8-1 ...

  • Page 27

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 8.1.3 Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. 8.1.4 Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal ...

  • Page 28

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 selectable delays are shown in dependent as shown in Table 8-2. Typ Time-out (V Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum V delay will not monitor the actual voltage and it will be required to select a delay longer than the V rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be CC used ...

  • Page 29

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 8-2. The Low Power Oscillator can operate in three different modes, each optimized for a specific fre- quency range. The operating mode is selected by the fuses CKSEL3...1 as shown in on page Table 8-3. Frequency Range Notes: The CKSEL0 Fuse together with the SUT1...0 Fuses select the start-up times as shown in 8-4 ...

  • Page 30

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 8-4. Oscillator Source / Power Conditions Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 8.4 Full Swing Crystal Oscillator Pins XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in crystal or a ceramic resonator may be used ...

  • Page 31

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 8-3. Table 8-6. Oscillator Source / Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power ...

  • Page 32

    ... When selecting crystals, load capacitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified by the crystal vendor. ATmega48A/48PA/88A/88PA/168A/168PA/328/328P oscillator is optimized for very low power consumption, and thus when selecting crystals, see tions on 6.5 pF, 9.0 pF and 12.5 pF crystals Table 8-7 ...

  • Page 33

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 8-9. SUT1... Table 8-10. CKSEL3... 0 0100 0101 Note: 8.6 Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8.0 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See 28-10 on page 322 See ” ...

  • Page 34

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 8-12. Table 8-12. Power Conditions BOD enabled Fast rising power Slowly rising power Note: 8.7 128 kHz Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre- quency is nominal at 3V and 25° ...

  • Page 35

    ... Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is used the divided system clock that is output. 8.10 Timer/Counter Oscillator ATmega48A/48PA/88A/88PA/168A/168PA/328/328P uses the same crystal oscillator for Low- frequency Oscillator and Timer/Counter Oscillator. See page 32 ATmega48A/48PA/88A/88PA/168A/168PA/328/328P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2 ...

  • Page 36

    ... System Clock Prescaler The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P has a system clock prescaler, and the system clock can be divided by setting the This feature can be used to decrease the system clock frequency and the power consumption when the requirement for processing power is low ...

  • Page 37

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 8.12 Register Description 8.12.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – CAL[7:0]: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value is ...

  • Page 38

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operat- ing conditions ...

  • Page 39

    ... To further save power possible to disable the BOD in some sleep modes. See ”BOD Disable(1)” on page 40 9.1 Sleep Modes ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and their distribution. The figure is helpful in selecting an appropriate sleep mode. up sources BOD disable ability. Note: Table 9-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. ...

  • Page 40

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 (1) 9.2 BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses - see 298 and onwards, the BOD is actively monitoring the power supply voltage during a sleep period. To save power possible to disable the BOD by software for some of the sleep modes, see level as when BOD is globally disabled by fuses. If BOD is disabled in software, the BOD func- tion is turned off immediately after entering the sleep mode ...

  • Page 41

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 9.5 Power-down Mode When the SM2...0 bits are written to 010, the SLEEP instruction makes the MCU enter Power- down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2- wire Serial Interface address watch, and the Watchdog continue operating (if enabled). Only an ...

  • Page 42

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 9.8 Extended Standby Mode When the SM2...0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles ...

  • Page 43

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 9.10.4 Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used ...

  • Page 44

    ... Read/Write Initial Value • Bits [7:4]: Reserved These bits are unused in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and will always be read as zero. • Bits 3:1 – SM[2:0]: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 9-2 ...

  • Page 45

    ... Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. • Bit 4 – RReserved This bit is reserved in ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and will always read as zero. • Bit 3 – PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module ...

  • Page 46

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 If using debugWIRE On-chip Debug System, this bit should not be written to one. Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation. ...

  • Page 47

    ... Reset Sources The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...

  • Page 48

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 10-1. Reset Logic BODLEVEL [2..0] RSTDISBL 10.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used to trigger the start-up Reset well as to detect a failure in supply voltage. ...

  • Page 49

    ... Figure 10-4. External Reset During Operation 10.5 Brown-out Detection ATmega48A/48PA/88A/88PA/168A/168PA/328/328P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level ...

  • Page 50

    ... Figure 10-6. Watchdog System Reset During Operation 10.7 Internal Voltage Reference ATmega48A/48PA/88A/88PA/168A/168PA/328/328P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 10.7.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used ...

  • Page 51

    ... Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 10.8.2 Overview ATmega48A/48PA/88A/88PA/168A/168PA/328/328P has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR - Watchdog Timer Reset - instruc- tion to restart the counter before the time-out value is reached ...

  • Page 52

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, altera- tions to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE ...

  • Page 53

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example WDT_off: C Code Example void WDT_off(void Note: Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialization routine, even if the Watchdog is not in use ...

  • Page 54

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example WDT_Prescaler_Change: C Code Example void WDT_Prescaler_Change(void Note: Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period. 8271C– ...

  • Page 55

    ... Read/Write Initial Value • Bit 7:4: Reserved These bits are unused bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and will always read as zero. • Bit 3 – WDRF: Watchdog System Reset Flag This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...

  • Page 56

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode ...

  • Page 57

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 10-2. WDP3 8271C–AVR–08/10 Watchdog Timer Prescale Select (Continued) Number of WDT Oscillator WDP2 WDP1 WDP0 256K (262144) cycles 512K (524288) cycles 1024K (1048576) cycles Typical Time-out at Cycles V = 5.0V CC 2.0 s 4.0 s 8.0 s Reserved 57 ...

  • Page 58

    ... ATmega 48A/48PA does not have a separate Boot Loader Section. In ATmega88A/88PA, ATmega168A/168PA and ATmega328/328P, the Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is affected by the IVSEL bit in MCUCR. 11.1 Interrupt Vectors in ATmega48A and ATmega48PA Table 11-1. Reset and Interrupt Vectors in ATmega48A and ATmega48PA Vector No. Program Address 1 0x000 2 ...

  • Page 59

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 11-1. Reset and Interrupt Vectors in ATmega48A and ATmega48PA (Continued) Vector No. Program Address 24 0x017 25 0x018 26 0x019 The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega 48A/48PA is: Address Labels Code 0x000 0x001 0x002 0x003 0x004 ...

  • Page 60

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 11.2 Interrupt Vectors in ATmega88A and ATmega88PA Table 11-2. Reset and Interrupt Vectors in ATmega88A and ATmega88PA Program (2) Vector No. Address (1) 1 0x000 2 0x001 3 0x002 4 0x003 5 0x004 6 0x005 7 0x006 8 0x007 9 0x008 10 0x009 11 0x00A 12 0x00B 13 0x00C 14 0x00D 15 0x00E 16 0x00F 17 0x010 18 0x011 19 0x012 20 0x013 21 0x014 ...

  • Page 61

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 11-3. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega88A/88PA is: Address Labels Code 0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0X008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 ...

  • Page 62

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega88A/88PA is: ...

  • Page 63

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 0xC1B 0xC1C 0xC1D 0xC1E 0xC1F 11.3 Interrupt Vectors in ATmega168A and ATmega168PA Table 11-4. Reset and Interrupt Vectors in ATmega168A and ATmega168PA Program (2) VectorNo. Address (1) 1 0x0000 2 0x0002 3 0x0004 4 0x0006 5 0x0008 6 0x000A 7 0x000C 8 0x000E 9 0x0010 10 0x0012 11 0x0014 12 0x0016 13 0x0018 14 0x001A 15 0x001C 16 0x001E ...

  • Page 64

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 11-5 on page 64 tions of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa ...

  • Page 65

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 0x0034 0x0035 0x0036 0x0037 0x0038 ... When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega168A/168PA is: ...

  • Page 66

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Address Labels Code ; .org 0x1C00 0x1C00 0x1C02 0x1C04 ... 0x1C32 ; 0x1C33 0x1C34 0x1C35 0x1C36 0x1C37 0x1C38 11.4 Interrupt Vectors in ATmega328 and ATmega328P Table 11-6. Reset and Interrupt Vectors in ATmega328 and ATmega328P Program (2) VectorNo. Address (1) 1 0x0000 2 0x0002 3 0x0004 4 0x0006 5 0x0008 6 0x000A ...

  • Page 67

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 11-6. Reset and Interrupt Vectors in ATmega328 and ATmega328P (Continued) Program (2) VectorNo. Address 21 0x0028 22 0x002A 23 0x002C 24 0x002E 25 0x0030 26 0x0032 Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see port – Read-While-Write Self-Programming” on page 2 ...

  • Page 68

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 0x0028 0x002A 0x002C 0x002E 0x0030 0x0032 ; 0x0033RESET: 0x0034 0x0035 0x0036 0x0037 0x0038 ... When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and ...

  • Page 69

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 ; .org 0x3C00 0x3C00 0x3C01 0x3C02 0x3C03 0x3C04 0x3C05 When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega328/328P is: Address Labels Code ...

  • Page 70

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 a. Write the Interrupt Vector Change Enable (IVCE) bit to one. b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL ...

  • Page 71

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 12. External Interrupts The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23...0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23...0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI2 will trigger if any enabled PCINT[23:16] pin toggles ...

  • Page 72

    ... Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and will always read as zero. • Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre- sponding interrupt mask are set ...

  • Page 73

    ... Read/Write Initial Value • Bit 7:2 – Reserved These bits are unused bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and will always read as zero. • Bit 1 – INTF1: External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one) ...

  • Page 74

    ... Read/Write Initial Value • Bit 7:3 – Reserved These bits are unused bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and will always read as zero. • Bit 2 – PCIF2: Pin Change Interrupt Flag 2 When a logic change on any PCINT[23:16] pin triggers an interrupt request, PCIF2 becomes set (one) ...

  • Page 75

    ... Read/Write Initial Value • Bit 7 – Reserved This bit is an unused bit in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and will always read as zero. • Bit 6:0 – PCINT[14:8]: Pin Change Enable Mask 14...8 Each PCINT[14:8]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin ...

  • Page 76

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 13. I/O-Ports 13.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when chang- ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input) ...

  • Page 77

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 13.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. ...

  • Page 78

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 13.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. ...

  • Page 79

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 13-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “ ...

  • Page 80

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example C Code Example unsigned char i; Note: 13.2.5 Digital Input Enable and Sleep Modes As shown in Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to V SLEEP is overridden for port pins enabled as external interrupt pins ...

  • Page 81

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pull-down ...

  • Page 82

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 13-2 ure 13-5 on page 81 generated internally in the modules having the alternate function. Table 13-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function ...

  • Page 83

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 13.3.1 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 13-3. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • XTAL2/TOSC2/PCINT7 – Port B, Bit 7 XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator ...

  • Page 84

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PB6 is dis- connected from the port, and becomes the input of the inverting Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. ...

  • Page 85

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source. • ICP1/CLKO/PCINT0 – Port B, Bit 0 ICP1, Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1. ...

  • Page 86

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 13-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 13.3.2 Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 13-6. Port Pin 8271C–AVR–08/10 Overriding Signals for Alternate Functions in PB3...PB0 PB3/MOSI/ ...

  • Page 87

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The alternate pin configuration is as follows: • RESET/PCINT14 – Port C, Bit 6 RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset sources. ...

  • Page 88

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 • ADC1/PCINT9 – Port C, Bit 1 PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog power. PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external interrupt source. • ADC0/PCINT8 – Port C, Bit 0 PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog power ...

  • Page 89

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 13-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 13.3.3 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 13-9. Port Pin 8271C–AVR–08/10 Overriding Signals for Alternate Functions in PC3...PC0 PC3/ADC3/ ...

  • Page 90

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The alternate pin configuration is as follows: • AIN1/OC2B/PCINT23 – Port D, Bit 7 AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. ...

  • Page 91

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 • INT0/PCINT18 – Port D, Bit 2 INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source. PCINT18: Pin Change Interrupt source 18. The PD2 pin can serve as an external interrupt source. • TXD/PCINT17 – Port D, Bit 1 TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is enabled, this pin is configured as an output regardless of the value of DDD1 ...

  • Page 92

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 13-11. Overriding Signals for Alternate Functions in PD3...PD0 Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 8271C–AVR–08/10 PD3/OC2B/INT1/ PD2/INT0/ PCINT19 PCINT18 OC2B ENABLE 0 OC2B 0 INT1 ENABLE + INT0 ENABLE + PCINT19 • PCIE2 PCINT18 • PCIE1 ...

  • Page 93

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 13.4 Register Description 13.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value Notes: • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See figuring the Pin” ...

  • Page 94

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 13.4.8 PORTD – The Port D Data Register Bit 0x0B (0x2B) Read/Write Initial Value 13.4.9 DDRD – The Port D Data Direction Register Bit 0x0A (0x2A) Read/Write Initial Value 13.4.10 PIND – The Port D Input Pins Address Bit 0x09 (0x29) Read/Write Initial Value 8271C– ...

  • Page 95

    ... CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the 107. The PRTIM0 bit in enable Timer/Counter0 module. 8271C–AVR–08/10 ”Pinout ATmega48A/48PA/88A/88PA/168A/168PA/328/328P” on ”Minimizing Power Consumption” on page 42 Figure 14-1. For the actual ”Register Description” on page must be written to zero to ...

  • Page 96

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 14-1. 8-bit Timer/Counter Block Diagram 14.2.1 Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com- pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be used, i ...

  • Page 97

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The Timer/Counter can be clocked internally, via the prescaler external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times ...

  • Page 98

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B. ...

  • Page 99

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is dis- abled the CPU will access the OCR0x directly. 14.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0x) bit ...

  • Page 100

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 14-4. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out- put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visi- ble on the pin ...

  • Page 101

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 14.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot- tom (0x00) ...

  • Page 102

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 the pin is set to output. The waveform generated will have a maximum frequency when OCR0A is set to zero (0x00). The waveform frequency is defined by the following clk_I/O equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00 ...

  • Page 103

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (see the port pin if the data direction for the port pin is set as output ...

  • Page 104

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 14-7. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins ...

  • Page 105

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 symmetry around BOTTOM the OCnx value at MAX must correspond to the result of an up- counting Compare Match. • The timer starts counting from a value higher than the one in OCRnx, and for that reason misses the Compare Match and hence the OCnx change that would have happened on the way up ...

  • Page 106

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 14-11 PWM mode where OCR0A is TOP. Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk TCNTn (CTC) OCRnx OCFnx 8271C– ...

  • Page 107

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 14.9 Register Description 14.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to ...

  • Page 108

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 14-4 rect PWM mode. Table 14-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to ...

  • Page 109

    ... Note: • Bits 3, 2 – Reserved These bits are reserved bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...

  • Page 110

    ... A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Reserved These bits are reserved bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • ...

  • Page 111

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 14-9. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 14.9.3 TCNT0 – Timer/Counter Register Bit 0x26 (0x46) Read/Write ...

  • Page 112

    ... Read/Write Initial Value • Bits 7:3 – Reserved These bits are reserved bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and will always read as zero. • Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – ...

  • Page 113

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector ...

  • Page 114

    ... I/O Register and bit locations are listed in the 135. The PRTIM1 bit in enable Timer/Counter1 module. 8271C–AVR–08/10 ”Pinout ATmega48A/48PA/88A/88PA/168A/168PA/328/328P” on ”PRR – Power Reduction Register” on page 45 Figure 15-1. For the actual ”Register Description” on page must be written to zero to ...

  • Page 115

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 15-1. 16-bit Timer/Counter Block Diagram Note: 15.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are described in the section page 116 ...

  • Page 116

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 put Compare Units” on page Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture pin (ICP1 the Analog Comparator pins (See ” ...

  • Page 117

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit Timer Regis- ters, then the result of the access outside the interrupt will be corrupted ...

  • Page 118

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example TIM16_ReadTCNT1: C Code Example unsigned int TIM16_ReadTCNT1( void ) { } Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. ...

  • Page 119

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example TIM16_WriteTCNT1: C Code Example void TIM16_WriteTCNT1( unsigned int Note: The assembly code example requires that the r17:r16 register pair contains the value to be writ- ten to TCNT1. 15.3.1 Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once ...

  • Page 120

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 15.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con- taining the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits ...

  • Page 121

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 15.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul- tiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit ...

  • Page 122

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to on page 15 ...

  • Page 123

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 15.7 Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle ...

  • Page 124

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out- put glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is dis- abled the CPU will access the OCR1x directly ...

  • Page 125

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 15.8 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. ...

  • Page 126

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 non-PWM modes refer to page 136, and for phase correct and phase and frequency correct PWM refer to page 136. A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits ...

  • Page 127

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 15-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. How- ...

  • Page 128

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max- imum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: ...

  • Page 129

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set ...

  • Page 130

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11) ...

  • Page 131

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output ...

  • Page 132

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction ...

  • Page 133

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature ...

  • Page 134

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 15-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f Figure 15-12 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. ...

  • Page 135

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 15-13 Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 15.11 Register Description 15.11.1 TCCR1A – Timer/Counter1 Control Register A Bit (0x80) Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec- tively) behavior ...

  • Page 136

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 15-2 PWM mode. Table 15-2. COM1A1/COM1B1 Note: Table 15-3 correct or the phase and frequency correct, PWM mode. Table 15-3. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting ...

  • Page 137

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 15-4. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the location of these bits are compatible with previous versions of the timer. 15.11.2 TCCR1B – Timer/Counter1 Control Register B ...

  • Page 138

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • ...

  • Page 139

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 15.11.4 TCNT1H and TCNT1L – Timer/Counter1 Bit (0x85) (0x84) Read/Write Initial Value The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP) ...

  • Page 140

    ... TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 0x16 (0x36) Read/Write Initial Value • Bit 7, 6 – Reserved These bits are unused bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and will always read as zero. 8271C–AVR–08/10 See Section “15.3” on page 116 – ...

  • Page 141

    ... ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. • Bit 4, 3 – Reserved These bits are unused bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and will always read as zero. • Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B) ...

  • Page 142

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 16. Timer/Counter0 and Timer/Counter1 Prescalers ”8-bit Timer/Counter0 with PWM” on page 95 114 share the same prescaler module, but the Timer/Counters can have different prescaler set- tings. The description below applies to both Timer/Counter1 and Timer/Counter0. 16.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This ...

  • Page 143

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling ...

  • Page 144

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 16.4 Register Description 16.4.1 GTCCR – General Timer/Counter Control Register Bit 0x23 (0x43) Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond- ing prescaler reset signals asserted ...

  • Page 145

    ... I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM2 bit in enable Timer/Counter2 module. Figure 17-1. 8-bit Timer/Counter Block Diagram 8271C–AVR–08/10 ”Pinout ATmega48A/48PA/88A/88PA/168A/168PA/328/328P” on page ”Register Description” on page ”Minimizing Power Consumption” on page 42 Count Clear Control Logic ...

  • Page 146

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 17.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg- isters. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2) ...

  • Page 147

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 17-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22 the timer is stopped ...

  • Page 148

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 17-3. Output Compare Unit, Block Diagram The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare Register to either top or bottom of the counting sequence ...

  • Page 149

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Com- pare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when changing between Waveform Generation modes ...

  • Page 150

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 17.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1 tells the Waveform Generator that no action on the OC2x Register performed on the next compare match. For compare output actions in the ...

  • Page 151

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 17-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run- ning with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature ...

  • Page 152

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs ...

  • Page 153

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 generated will have a maximum frequency of f ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 17.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM22 provides a high resolution phase correct PWM waveform generation option ...

  • Page 154

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2 and OCR2A when MGM2 (See value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x Register at compare match between OCR2x and TCNT2 when the counter decrements ...

  • Page 155

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 17-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 17-10 Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 17-11 Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- ...

  • Page 156

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 17.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is: a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2. ...

  • Page 157

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 • Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP ...

  • Page 158

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port B. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. For Timer/Counter2, the possible prescaled selections are: clk ...

  • Page 159

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 17.11 Register Description 17.11.1 TCCR2A – Timer/Counter Control Register A Bit (0xB0) Read/Write Initial Value • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to ...

  • Page 160

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 17-4 rect PWM mode. Table 17-4. COM2A1 Note: • Bits 5:4 – COM2B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected to ...

  • Page 161

    ... Note: • Bits 3, 2 – Reserved These bits are reserved bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and will always read as zero. • Bits 1:0 – WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting ...

  • Page 162

    ... A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2B as TOP. The FOC2B bit is always read as zero. • Bits 5:4 – Reserved These bits are reserved bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and will always read as zero. • Bit 3 – WGM22: Waveform Generation Mode See the description in the • ...

  • Page 163

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 17-9. CS22 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 17.11.3 TCNT2 – Timer/Counter Register Bit (0xB2) Read/Write Initial Value The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter ...

  • Page 164

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 17.11.6 TIMSK2 – Timer/Counter2 Interrupt Mask Register Bit (0x70) Read/Write Initial Value • Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Coun- ter 2 Interrupt Flag Register – ...

  • Page 165

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 17.11.8 ASSR – Asynchronous Status Register Bit (0xB6) Read/Write Initial Value • Bit 7 – Reserved This bit is reserved and will always read as zero. • Bit 6 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buf- fer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead kHz crystal ...

  • Page 166

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 17.11.9 GTCCR – General Timer/Counter Control Register ...

  • Page 167

    ... Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and peripheral devices or between sev- eral AVR devices. The USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 205. The PRSPI bit in module. 8271C– ...

  • Page 168

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 18-1. SPI Block Diagram Note: The interconnection between Master and Slave CPUs with SPI is shown in 169. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. ...

  • Page 169

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 18-2. SPI Master-slave Interconnection The system is single buffered in the transmit direction and double buffered in the receive direc- tion ...

  • Page 170

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 8271C–AVR–08/10 (1) ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 ldi r17,(1< ...

  • Page 171

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 8271C–AVR–08/10 (1) ; Set MISO output, all others input ldi r17,(1<<DD_MISO) ...

  • Page 172

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 18.3 SS Pin Functionality 18.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data ...

  • Page 173

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 18-3. SPI Transfer Format with CPHA = 0 Figure 18-4. SPI Transfer Format with CPHA = 1 8271C–AVR–08/10 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 Bit 5 LSB first (DORD = 1) ...

  • Page 174

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 18.5 Register Description 18.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set. ...

  • Page 175

    ... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P is also used for program memory and EEPROM downloading or uploading. See ming and verification. 8271C–AVR–08/10 ...

  • Page 176

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 18.5.3 SPDR – SPI Data Register Bit 0x2E (0x4E) Read/Write Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 8271C– ...

  • Page 177

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 19. USART0 19.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with Data Bits and Stop Bits • ...

  • Page 178

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 19-1. USART Block Diagram Note: 19.3 Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn- chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART Control and Status Register C (UCSRnC) selects between asynchronous and synchronous operation ...

  • Page 179

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 19-2 Figure 19-2. Clock Generation Logic, Block Diagram Signal description: txclk rxclk xcki xcko fosc 19.3.1 Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in this section refers to The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a programmable prescaler or baud rate generator ...

  • Page 180

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 19-1 ing the UBRRn value for each mode of operation using an internally generated clock source. Table 19-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: BAUD f OSC UBRRn Some examples of UBRRn values for some system clock frequencies are found in page 196) ...

  • Page 181

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 19.3.3 External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver ...

  • Page 182

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 A frame starts with the start bit followed by the least significant data bit. Then the next data bits total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state ...

  • Page 183

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 19.5 USART Initialization The USART has to be initialized before any communication can take place. The initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization ...

  • Page 184

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example USART_Init: C Code Example #define FOSC 1843200 // Clock Speed #define BAUD 9600 #define MYUBRR FOSC/16/BAUD-1 void main( void ) { ... ... } void USART_Init( unsigned int ubrr Note: More advanced initialization routines can be made that include frame format as parameters, dis- able interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine combined with initialization code for other I/O modules ...

  • Page 185

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 chronous operation is used, the clock on the XCKn pin will be overridden and used as transmission clock. 19.6.1 Sending Frames with Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame ...

  • Page 186

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example USART_Transmit: C Code Example void USART_Transmit( unsigned int data ) { } Notes: The ninth bit can be used for indicating an address frame when using multi processor communi- cation mode or for other protocol handling as for example synchronization. 19.6.3 Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit Complete (TXCn) ...

  • Page 187

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. ...

  • Page 188

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example USART_Receive: C Code Example unsigned char USART_Receive( void ) { } Note: The function simply waits for data to be present in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the value. 19.7.2 Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZn=7) the ninth bit must be read from the RXB8n bit in UCSRnB before reading the low bits from the UDRn ...

  • Page 189

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: 8271C–AVR–08/10 (1) ; Wait for data to be received in r16, UCSRnA sbrs r16, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRnA in r17, UCSRnB ...

  • Page 190

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. 19.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state ...

  • Page 191

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error ...

  • Page 192

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 19.8.1 Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor- izontal arrows illustrate the synchronization variation due to the sampling process ...

  • Page 193

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. Figure 19-7 on page 193 of the start bit of the next frame. Figure 19-7. Stop Bit Sampling and Next Start Bit Sampling The same majority voting is done to the stop bit as done for the other bits in the frame ...

  • Page 194

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 19-2 on page 194 that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. Table 19-2. # (Data+Parity Bit) Table 19-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. ...

  • Page 195

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 setting, but has to be used differently when part of a system utilizing the Multi-processor Communication mode. If the Receiver is set up to receive frames that contain data bits, then the first stop bit indi- cates if the frame contains data or address information. If the Receiver is set up for frames with nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames ...

  • Page 196

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 table. Higher error ratings are acceptable, but the Receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see Range” on page Examples of UBRRn Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc ...

  • Page 197

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 19-4. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% 47 14.4k 15 0.0% 31 19.2k 11 0.0% 23 28.8k 7 0.0% 15 38.4k 5 0.0% 11 57.6k 3 0.0% 7 76. ...

  • Page 198

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 19-5. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% 103 14.4k 34 -0.8% 68 19.2k 25 0.2% 51 28.8k 16 2.1% 34 38. ...

  • Page 199

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 19-6. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% 207 14.4k 68 0.6% 138 19.2k 51 0.2% 103 28 ...

  • Page 200

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 19.11 Register Description 19.11.1 UDRn – USART I/O Data Register n Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Reg- ister (TXB) will be the destination for data written to the UDRn Register location ...