IC MCU AVR 2K FLASH 20DIP

ATTINY2313-20PU

Manufacturer Part NumberATTINY2313-20PU
DescriptionIC MCU AVR 2K FLASH 20DIP
ManufacturerAtmel
SeriesAVR® ATtiny
ATTINY2313-20PU datasheets
 

Specifications of ATTINY2313-20PU

Core ProcessorAVRCore Size8-Bit
Speed20MHzConnectivitySPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o18
Program Memory Size2KB (1K x 16)Program Memory TypeFLASH
Eeprom Size128 x 8Ram Size128 x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case20-DIP (0.300", 7.62mm)
Package20PDIPDevice CoreAVR
Family NameATtinyMaximum Speed20 MHz
Operating Supply Voltage3.3|5 VData Bus Width8 Bit
Number Of Programmable I/os18Interface TypeSPI/USART/USI
Number Of Timers2Processor SeriesATTINY2x
CoreAVR8Data Ram Size128 B
Maximum Clock Frequency20 MHzMaximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
Cpu FamilyATtinyDevice Core Size8b
Frequency (max)20MHzTotal Internal Ram Size128Byte
# I/os (max)18Number Of Timers - General Purpose2
Operating Supply Voltage (typ)3.3/5VOperating Supply Voltage (max)5.5V
Operating Supply Voltage (min)2.7VInstruction Set ArchitectureRISC
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
MountingThrough HolePin Count20
Package TypePDIPFor Use WithATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS StatusLead free / RoHS CompliantData Converters-
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Features
®
Utilizes the AVR
RISC Architecture
AVR – High-performance and Low-power RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
Data and Non-volatile Program and Data Memories
– 2K Bytes of In-System Self Programmable Flash
Endurance 10,000 Write/Erase Cycles
– 128 Bytes In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– 128 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes
– Four PWM Channels
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– USI – Universal Serial Interface
– Full Duplex USART
Special Microcontroller Features
– debugWIRE On-chip Debugging
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low-power Idle, Power-down, and Standby Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
I/O and Packages
– 18 Programmable I/O Lines
– 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF
Operating Voltages
– 1.8 – 5.5V (ATtiny2313V)
– 2.7 – 5.5V (ATtiny2313)
Speed Grades
– ATtiny2313V: 0 – 4 MHz @ 1.8 - 5.5V, 0 – 10 MHz @ 2.7 – 5.5V
– ATtiny2313: 0 – 10 MHz @ 2.7 - 5.5V, 0 – 20 MHz @ 4.5 – 5.5V
Typical Power Consumption
– Active Mode
1 MHz, 1.8V: 230 µA
32 kHz, 1.8V: 20 µA (including oscillator)
– Power-down Mode
< 0.1 µA at 1.8V
8-bit
Microcontroller
with 2K Bytes
In-System
Programmable
Flash
ATtiny2313/V
Preliminary
Rev. 2543L–AVR–08/10

ATTINY2313-20PU Summary of contents

  • Page 1

    ... Speed Grades – ATtiny2313V: 0 – 4 MHz @ 1.8 - 5.5V, 0 – 10 MHz @ 2.7 – 5.5V – ATtiny2313: 0 – 10 MHz @ 2.7 - 5.5V, 0 – 20 MHz @ 4.5 – 5.5V • Typical Power Consumption – Active Mode 1 MHz, 1.8V: 230 µA 32 kHz, 1.8V: 20 µ ...

  • Page 2

    ... Figure 1. Pinout ATtiny2313 Configurations Overview The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. ...

  • Page 3

    Block Diagram Figure 2. Block Diagram VCC GND 2543L–AVR–08/10 PA0 - PA2 PORTA DRIVERS DATA REGISTER DATA DIR. REG. PORTA PORTA 8-BIT DATA BUS STACK PROGRAM POINTER COUNTER PROGRAM SRAM FLASH INSTRUCTION GENERAL REGISTER PURPOSE REGISTER INSTRUCTION DECODER CONTROL ALU ...

  • Page 4

    ... RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny2313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny2313 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. ...

  • Page 5

    ... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATtiny2313 as listed on 56. RESET Reset input ...

  • Page 6

    ... C is compiler dependent. Please confirm with the C compiler documen- tation for more details. Disclaimer Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. ATtiny2313 6 2543L–AVR–08/10 ...

  • Page 7

    AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and ...

  • Page 8

    ... Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ATtiny2313 8 2543L–AVR–08/10 ...

  • Page 9

    The AVR Status Register – SREG – is defined as: Bit Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt ...

  • Page 10

    ... X, Y, and Z are defined as described in Figure 5. The X-, Y-, and Z-registers X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). ATtiny2313 … R13 ...

  • Page 11

    Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the ...

  • Page 12

    ... Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the ATtiny2313 12 T1 clk ...

  • Page 13

    CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.. Assembly Code Example in r16, SREG cli sbi EECR, EEMPE sbi EECR, EEPE out SREG, r16 C Code Example char ...

  • Page 14

    ... Reprogrammable 16. Flash Program Memory The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny2313 Pro- gram Counter (PC bits wide, thus addressing the 1K program memory locations. Programming” on page 158 using the SPI pins. Constant tables can be allocated within the entire program memory address space (see the LPM – ...

  • Page 15

    ... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128 bytes of internal data SRAM in the ATtiny2313 are all accessible through all these addressing modes. The Register File is described in Figure 9. Data Memory Map Data Memory Access This section describes the general access timing concepts for internal memory access ...

  • Page 16

    ... Figure 10. On-chip Data SRAM Access Cycles EEPROM Data The ATtiny2313 contains 128 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at Memory least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...

  • Page 17

    ... Initial Value • Bits 7..6 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313 and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bits setting defines which programming action that will be triggered when writing EEPE ...

  • Page 18

    ... While the device is busy with programming not possible to do any other EEPROM operations. The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator fre- quency is within the requirements described in page 26. ATtiny2313 18 “Oscillator Calibration Register – OSCCAL” on 2543L–AVR–08/10 ...

  • Page 19

    The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glob- ally) so that no interrupts will occur during execution of these functions. ...

  • Page 20

    ... I/O Memory The I/O space definition of the ATtiny2313 is shown in All ATtiny2313 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 ATtiny2313 ...

  • Page 21

    ... The I/O and peripherals control registers are explained in later sections. General Purpose I/O The ATtiny2313 contains three General Purpose I/O Registers. These registers can be used for Registers storing any information, and they are particularly useful for storing global variables and status flags ...

  • Page 22

    ... Flash Clock – clk The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- FLASH taneously with the CPU clock. ATtiny2313 22 presents the principal clock systems in the AVR and their distribution. All of the clocks 30. The clock systems are detailed below. ...

  • Page 23

    ... For all fuses “1” means unprogrammed while “0” means programmed. 181. = 5.0V) Typ Time-out ( Table 4 on page CKSEL3..0 0000 0010 0100 0110 1000 - 1111 0001/0011/0101/0111 Table “ATtiny2313 Typical Characteris- = 3.0V) Number of Cycles CC 4.3 ms 512 (8,192) Figure 12 on page 24. Either a quartz 24. For ceramic resonators, the capacitor values 3. The frequency 23 ...

  • Page 24

    ... The operating mode is selected by the fuses CKSEL3..1 as shown in Table 4. Crystal Oscillator Operating Modes CKSEL3..1 (2) 100 101 110 111 Notes: The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in 5. ATtiny2313 (1) Frequency Range (MHz) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8 ...

  • Page 25

    ... OSCCAL Register and thereby automatically calibrates the RC Oscillator and 25°C, this calibration gives a frequency within ± 10% of the nominal frequency. Using calibration methods as described in application notes available at www.atmel.com/avr it is possi- ble to achieve ± 2% accuracy at any given V as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “ ...

  • Page 26

    ... Oscillator to ensure stable operation of the MCU. A variation in frequency of more than 2% from one cycle to the next can lead to unpredictable behavior. Changes in OSCCAL should not exceed 0x20 for each calibration. Table 8. Internal RC Oscillator Frequency Range. OSCCAL Value 0x00 0x3F 0x7F ATtiny2313 26 Start-up Time from Power- Additional Delay from down and Power-save ...

  • Page 27

    External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in 13. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 13. External Clock Drive ...

  • Page 28

    ... System Clock The ATtiny2313 has a system clock prescaler, and the system clock can be divided by setting Prescalar the “CLKPR – Clock Prescale Register” on page system clock frequency and the power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...

  • Page 29

    CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. • Bits 3:0 – CLKPS3:0: Clock ...

  • Page 30

    ... ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. ATtiny2313 30 for a summary enabled interrupt occurs while the MCU sleep mode, presents the different clock systems in the ATtiny2313, and their distribu ...

  • Page 31

    Power-down Mode When the SM1..0 bits are written 11, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the USI start condition detection, and the ...

  • Page 32

    ... For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR). Refer to “Digital Input Disable Register – DIDR” on page ATtiny2313 32 for details on the start-up time. “Interrupts” on page 44 for details on how to configure the Watchdog Timer ...

  • Page 33

    ... SUT and CKSEL Fuses. The dif- ferent selections for the delay period are presented in Reset Sources The ATtiny2313 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • ...

  • Page 34

    ... A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V CC Figure 15. MCU Start-up, RESET Tied to V TIME-OUT INTERNAL ATtiny2313 34 Parameter Condition Power-on Reset Threshold Voltage +85°C ...

  • Page 35

    ... Figure 17. External Reset During Operation Brown-out Detection ATtiny2313 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection ...

  • Page 36

    ... V antees that a Brown-Out Reset will occur before V operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 110 for ATtiny2313V and BODLEVEL = 101 for ATtiny2313L. Parameter Brown-out Detector Hysteresis Min Pulse Width on Brown-out Reset ...

  • Page 37

    Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t page 44 Figure 19. Watchdog ...

  • Page 38

    ... Internal Voltage ATtiny2313 features an internal bandgap reference. This reference is used for Brown-out Detec- Reference tion, and it can be used as an input to the Analog Comparator. Voltage Reference The voltage reference has a start-up time that may influence the way it should be used. The Enable Signals and ...

  • Page 39

    ... Watchdog Timer ATtiny2313 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode Figure 20 ...

  • Page 40

    ... Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use. ATtiny2313 40 (1) r16, MCUSR r16, (0xff & ...

  • Page 41

    The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example WDT_Prescaler_Change: C Code Example void WDT_Prescaler_Change(void Note: Note: The Watchdog Timer should be reset before ...

  • Page 42

    ... Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown in Table 20 on page ATtiny2313 ...

  • Page 43

    Table 20. Watchdog Timer Prescale Select WDP3 2543L–AVR–08/10 Number of WDT Oscillator WDP2 WDP1 WDP0 (2048) cycles ...

  • Page 44

    ... Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny2313. For a general explanation of the AVR interrupt handling, refer to page 12. Interrupt Vectors Table 21. Reset and Interrupt Vectors in ATtiny2313 Vector No ATtiny2313 44 Program Address Source Interrupt Definition 0x0000 RESET External Pin, Power-on Reset, Brown-out Reset, ...

  • Page 45

    ... The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny2313 is: Address Labels Code 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 ; 0x0013 0x0014 0x0015 0x0016 ... 2543L– ...

  • Page 46

    ... How each alternate function interferes with the port pin is described in Functions” on page nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATtiny2313 46 and Ground as indicated in CC for a complete list of parameters. ...

  • Page 47

    Ports as General The ports are bi-directional I/O ports with optional internal pull-ups. description of one I/O-port pin, here generically called Pxn. Digital I/O Figure 22. General Digital I/O Note: Configuring the Pin Each port pin consists of three register ...

  • Page 48

    ... The maximum and minimum propagation delays are denoted t Figure 23. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS ATtiny2313 48 summarizes the control signals for the pin value. PUD PORTxn ...

  • Page 49

    Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ...

  • Page 50

    ... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. ATtiny2313 50 (1) r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) r17,(1< ...

  • Page 51

    Alternate Port Most port pins have alternate functions in addition to being general digital I/Os. how the port pin control signals from the simplified Functions functions. The overriding signals may not be present in all port pins, but the figure ...

  • Page 52

    ... DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATtiny2313 52 Full Name Description Pull-up Override If this signal is set, the pull-up enable is controlled by the Enable PUOV signal ...

  • Page 53

    MCU Control Register Bit – MCUCR Read/Write Initial Value • Bit 7 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured ...

  • Page 54

    ... Comparator. PCINT0: Pin Change Interrupt Source 0. The PB0 pin can serve as an external interrupt source. Table 26 Figure 25 on page while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. ATtiny2313 54 Configure the port pin as input with the internal pull-up . and ...

  • Page 55

    Table 26. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 27. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE ...

  • Page 56

    ... INT0: External Interrupt Source 0. The PD2 pin can serve as en external interrupt source to the MCU. XCK: USART Transfer Clock used only by Synchronous Transfer mode. CKOUT: System Clock Output • TXD – Port D, Bit 1 TXD: UART Data Transmitter. • RXD – Port D, Bit 0 RXD: UART Data Receiver. ATtiny2313 56 Alternate Function ICP OC0B/T1 T0 INT1 INT0/XCK/CKOUT ...

  • Page 57

    Table 29 Figure 25 on page Table 29. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 30. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV ...

  • Page 58

    ... Bit Address – PINB Read/Write Initial Value Port D Data Register – Bit PORTD Read/Write Initial Value Port D Data Direction Bit Register – DDRD Read/Write Initial Value Port D Input Pins Bit Address – PIND Read/Write Initial Value ATtiny2313 – – – – ...

  • Page 59

    External The External Interrupts are triggered by the INT0 pin, INT1 pin or any of the PCINT7..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0, INT1 or PCINT7..0 pins are Interrupts configured as outputs. This ...

  • Page 60

    ... INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector. • Bit 6 – INT0: External Interrupt Request 0 Enable ATtiny2313 60 R/W R/W ...

  • Page 61

    When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU Control Register – ...

  • Page 62

    ... PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request. ATtiny2313 62 “Pinout ATtiny2313” on page “8-bit Timer/Counter Register Description” on page Count Clear Control Logic Direction ...

  • Page 63

    Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com- pare Unit, in this case Compare ...

  • Page 64

    ... WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (see Figure 29 Figure 29. Output Compare Unit, Block Diagram ATtiny2313 64 ). clk can be generated from an external or internal clock source present or not ...

  • Page 65

    The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is disabled. The double buffering synchronizes the update ...

  • Page 66

    ... The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot- tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same ATtiny2313 66 COMnx1 Waveform ...

  • Page 67

    TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, ...

  • Page 68

    ... OC0x Register at the Compare Match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). ATtiny2313 68 Figure 30. The TCNT0 value is in the timing diagram shown as a histo- ...

  • Page 69

    The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represents special cases when generating a PWM ...

  • Page 70

    ... There are two cases that give a transition without Compare Match. • OCR0A changes its value from MAX, like in OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up- counting Compare Match. ATtiny2313 Table 27 on page 55) ...

  • Page 71

    The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. Timer/Counter The Timer/Counter is a ...

  • Page 72

    ... Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- caler (f clk_I/O clk clk (clk I/O TCNTn (CTC) OCRnx OCFnx ATtiny2313 72 /8) I/O Tn /8) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP 2543L–AVR–08/10 ...

  • Page 73

    Timer/Counter Register Description Timer/Counter Control Bit Register A – TCCR0A Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 ...

  • Page 74

    ... Table 38 mode. Table 38. Compare Output Mode, Fast PWM Mode COM0B1 Note: ATtiny2313 74 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct COM0A0 Description 0 Normal port operation, OC0A disconnected. 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. ...

  • Page 75

    ... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...

  • Page 76

    ... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...

  • Page 77

    Table 41. Clock Select Bit Description CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as ...

  • Page 78

    ... Initial Value • Bit 4 – Res: Reserved Bit This bit is reserved bit in the ATtiny2313 and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter0 Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...

  • Page 79

    When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. 2543L–AVR–08/10 79 ...

  • Page 80

    ... The external clock must be guaranteed to have less than half the sys- tem clock frequency (f sampling, the maximum frequency of an external clock it can detect is half the sampling fre- ATtiny2313 80 ). Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ) ...

  • Page 81

    ... Initial Value • Bits 7..1 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313 and will always read as zero. • Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware ...

  • Page 82

    ... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the Figure 40. 16-bit Timer/Counter Block Diagram Note: ATtiny2313 82 “Pinout ATtiny2313” on page “16-bit Timer/Counter Register Description” on page Count Clear Control Logic Direction ...

  • Page 83

    Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are described in the section page 84. The Timer/Counter ...

  • Page 84

    ... The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. ATtiny2313 84 2543L–AVR–08/10 ...

  • Page 85

    Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions ...

  • Page 86

    ... SREG = sreg; return i; } Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. ATtiny2313 86 (1) (1) 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” ...

  • Page 87

    The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: C Code Example void ...

  • Page 88

    ... There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see ATtiny2313 88 “Timer/Counter0 and Timer/Counter1 Prescalers” on page shows a block diagram of the counter and its surroundings. ...

  • Page 89

    The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture ...

  • Page 90

    ... I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals ATtiny2313 90 84. “Accessing 16-bit Registers” ...

  • Page 91

    Waveform Generator for handling the special cases of the extreme values in some modes of operation A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In ...

  • Page 92

    ... Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. ATtiny2313 92 84. “Accessing 16-bit Registers” ...

  • Page 93

    Compare Match The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Output Unit Secondly the COM1x1:0 bits control the OC1x pin ...

  • Page 94

    ... It also simplifies the opera- tion of counting external events. The timing diagram for the CTC mode is shown in (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. ATtiny2313 94 Table 43 on page 104. For fast PWM mode refer to 93.) “ ...

  • Page 95

    Figure 45. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag according to the register used to define ...

  • Page 96

    ... When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. ATtiny2313 96 ( ...

  • Page 97

    Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 ...

  • Page 98

    ... The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OCF1A or ICF1 flag is set accord- ingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer ATtiny2313 98 ( ...

  • Page 99

    TOP). The interrupt flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or ...

  • Page 100

    ... OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. Figure 48. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period ATtiny2313 100 48 PFCPWM Figure 48. The figure shows phase and frequency correct PWM ...

  • Page 101

    The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OCF1A ...

  • Page 102

    ... Figure 51 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at BOTTOM. ATtiny2313 102 Figure 49 clk ...

  • Page 103

    Figure 51. Timer/Counter Timing Diagram, no Prescaling (PC and PFC PWM) Figure 52 Figure 52. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 2543L–AVR–08/10 clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn ...

  • Page 104

    ... When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen- dent of the WGM13:0 bits setting. WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). Table 43. Compare Output Mode, non-PWM COM1A1/COM1B1 Table 44 mode. Table 44. Compare Output Mode, Fast PWM COM1A1/COM1B1 ATtiny2313 104 COM1A1 COM1A0 COM1B1 ...

  • Page 105

    Note: Table 45 rect or the phase and frequency correct, PWM mode. Table 45. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits ...

  • Page 106

    ... Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATtiny2313 106 (1) WGM10 Timer/Counter Mode of (PWM10) Operation 0 0 Normal 0 1 PWM, Phase Correct, 8-bit ...

  • Page 107

    Timer/Counter1 Bit Control Register B – TCCR1B Read/Write Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the ...

  • Page 108

    ... TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units. Output Compare Bit Register 1 A – OCR1AH and OCR1AL Read/Write Initial Value ATtiny2313 108 FOC1A FOC1B – ...

  • Page 109

    Output Compare Bit Register OCR1BH and OCR1BL Read/Write Initial Value The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare ...

  • Page 110

    ... WGM13 used as the TOP value, the ICF1 flag is set when the coun- ter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. ATtiny2313 110 44.) is executed when the ICF1 flag, located in TIFR, is set. 7 ...

  • Page 111

    USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or ...

  • Page 112

    ... Register. When using synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 54 ATtiny2313 112 shows a block diagram of the clock generation logic. Figure 53) if the Buffer Registers are 2543L– ...

  • Page 113

    Figure 54. Clock Generation Logic, Block Diagram Signal description: txclk rxclk xcki xcko fosc Internal Clock Internal clock generation is used for the asynchronous and the synchronous master modes of Generation – The operation. The description in this section refers ...

  • Page 114

    ... XCK clock edge of the edge the data output (TxD) is changed. Figure 55. Synchronous Mode XCK Timing. UCPOL = 1 UCPOL = 0 The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As ATtiny2313 114 System Oscillator clock frequency Figure 54 for details. f XCK depends on the stability of the system clock source ...

  • Page 115

    XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge. Frame Formats A serial frame is defined to be one character of ...

  • Page 116

    ... UBRRL = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRB = (1<<RXEN)|(1<<TXEN); /* Set frame format: 8data, 2stop bit */ UCSRC = (1<<USBS)|(3<<UCSZ0); } Note: ATtiny2313 116 Data bit n of the character (1) UBRRH, r17 UBRRL, r16 r16, (1<<RXEN)|(1<<TXEN) UCSRB,r16 r16, (1< ...

  • Page 117

    More advanced initialization routines can be made that include frame format as parameters, dis- able interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization ...

  • Page 118

    ... UDR = data; } Note: The function simply waits for the transmit buffer to be empty by checking the UDRE flag, before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized, the interrupt routine writes the data into the buffer. ATtiny2313 118 (1) UDR,r16 (1) ; ...

  • Page 119

    Sending Frames with If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB 9 Data Bit before the low byte of the character is written to UDR. The following code ...

  • Page 120

    ... The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo- Transmitter ing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD pin. ATtiny2313 120 2543L–AVR–08/10 ...

  • Page 121

    Data Reception – The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Regis- ter to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden The USART by ...

  • Page 122

    ... UCSRB; resl = UDR error, return - status & (1<<FE)|(1<<DOR)|(1<<UPE Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); } ATtiny2313 122 (1) r18, UCSRA r17, UCSRB r16, UDR r17, HIGH(-1) r16, LOW(-1) ...

  • Page 123

    Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as ...

  • Page 124

    ... Receiver. The asynchronous reception operational range depends on the accuracy of the inter- nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. ATtiny2313 124 (1) ...

  • Page 125

    Asynchronous Clock The clock recovery logic synchronizes internal clock to the incoming serial frames. Recovery illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and ...

  • Page 126

    ... R accepted in relation to the receiver baud rate. Table 49 Normal Speed mode has higher toleration of baud rate variations. Table 49. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) # (Data+Parity Bit) ATtiny2313 126 RxD ...

  • Page 127

    Table 49. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) # (Data+Parity Bit) Table 50. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X = 1) # (Data+Parity Bit) The recommendations of the ...

  • Page 128

    ... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC flag and this might accidentally be cleared when using SBI or CBI instructions. ATtiny2313 128 2543L–AVR–08/10 ...

  • Page 129

    USART Register Description USART I/O Data Bit Register – UDR Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. The Transmit ...

  • Page 130

    ... This bit enables the Multi-processor Communication mode. When the MPCM bit is written to one, all the incoming frames received by the USART Receiver that do not contain address infor- mation will be ignored. The Transmitter is unaffected by the MPCM setting. For more detailed information see ATtiny2313 130 “Multi-processor Communication Mode” on page 128. ...

  • Page 131

    USART Control and Bit Status Register B – UCSRB Read/Write Initial Value • Bit 7 – RXCIE: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated ...

  • Page 132

    ... This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 53. USBS Bit Settings • Bit 2:1 – UCSZ1:0: Character Size The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Char- acter SiZe frame the Receiver and Transmitter use. See ATtiny2313 132 – ...

  • Page 133

    Table 54. UCSZ Bits Settings UCSZ2 • Bit 0 – UCPOL: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output ...

  • Page 134

    ... Max. 62.5 kbps 125 kbps 1. UBRR = 0, Error = 0.0% ATtiny2313 134 126). The error values are calculated using the following equation: BaudRate ⎛ Error[%] = ------------------------------------------------------- - 1 ⎝ BaudRate f = 1.8432 MHz osc U2X = 0 U2X = 1 Error UBRR ...

  • Page 135

    Table 57. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...

  • Page 136

    ... Max. 0.5 Mbps 1. UBRR = 0, Error = 0.0% ATtiny2313 136 11.0592 f = osc U2X = 0 Error UBRR Error UBRR -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% ...

  • Page 137

    Table 59. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) Baud Rate (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M (1) Max. 1. 2543L–AVR–08/10 U2X = 0 UBRR Error 416 -0.1% ...

  • Page 138

    ... In this case the counter counts the number of edges, and not the number of bits. The clock can be selected from three different sources: The USCK pin, Timer0 overflow, or from software. ATtiny2313 138 “Pinout ATtiny2313” on page 2. CPU accessible I/O Registers, including I/O bits 144 ...

  • Page 139

    The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start con- dition is detected, or after ...

  • Page 140

    ... The second and third instructions clears the USI Counter Overflow Flag and the USI counter value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. ATtiny2313 140 out ...

  • Page 141

    The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/2): SPITransfer_Fast: ret SPI Slave Operation The following code demonstrates how to use the USI module as a SPI Slave: Example ...

  • Page 142

    ... The clock is generated by the master by toggling the USCK pin via the PORT Register. The data direction is not given by the physical layer. A protocol, like the one used by the TWI- bus, must be implemented to control the data flow. ATtiny2313 142 Bit7 Bit6 ...

  • Page 143

    Figure 64. Two-wire Mode, Typical Timing Diagram SDA SCL Referring to the timing diagram (Figure 64.), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while ...

  • Page 144

    ... MSB written as long as the latch is open. The latch ensures that data input is sampled and data output is changed on opposite clock edges. Note that the corresponding Data Direction Register to the pin must be set to one for enabling data output from the Shift Register. ATtiny2313 144 “Clock Systems and their Distribution” on page 7 ...

  • Page 145

    USI Status Register – Bit USISR Read/Write Initial Value The Status Register contains interrupt flags, line status flags and the counter value. • Bit 7 – USISIF: Start Condition Interrupt Flag When Two-wire mode is selected, the USISIF flag is ...

  • Page 146

    ... Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and Shift Register can therefore be clocked externally, and data input sampled, even when outputs are disabled. The relations between USIWM1..0 and the USI operation is summarized in ATtiny2313 146 Table 60 on page 147. ...

  • Page 147

    Table 60. Relations between USIWM1..0 and the USI Operation USIWM1 Note: 2543L–AVR–08/10 USIWM0 Description 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. ...

  • Page 148

    ... When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ- ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device. ATtiny2313 148 shows the relationship between the USICS1..0 and USICLK setting and clock source ...

  • Page 149

    Analog The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin Comparator AIN1, the Analog Comparator output, ...

  • Page 150

    ... PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ- ten logic one to reduce power consumption in the digital input buffer. ATtiny2313 150 Table 62 ...

  • Page 151

    On- chip Debug System Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or for other ...

  • Page 152

    ... Read/Write Initial Value The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. ATtiny2313 152 will not work. CC ® ...

  • Page 153

    Self- The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associ- Programming ated protocol to read code and write (program) that code into the ...

  • Page 154

    ... Page Erase and Page Write operation. The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. Figure 68. Addressing the Flash During SPM Z - REGISTER Note: ATtiny2313 154 ...

  • Page 155

    ... Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313 and always read as zero. • Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost. • ...

  • Page 156

    ... SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below. Refer to High byte. Bit Rd Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one. ATtiny2313 156 – ...

  • Page 157

    Preventing Flash During periods of low V Corruption too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. ...

  • Page 158

    ... Memory Programming Program And Data The ATtiny2313 provides two Lock bits which can be left unprogrammed (“1”) or can be pro- Memory Lock Bits grammed (“0”) to obtain the additional features listed in erased to “1” with the Chip Erase command. Table 64. Lock Bit Byte ...

  • Page 159

    ... Fuse Bits The ATtiny2313 has three Fuse bytes. all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logi- cal zero, “0”, if they are programmed. Table 66. Fuse Extended Byte Fuse Extended Byte ...

  • Page 160

    ... ATtiny2313 device when 0x001 is 0x91). Calibration Byte Signature area of ATtiny2313 has one byte of calibration data for the internal RC Oscillator. This byte resides in the high byte of address 0x0000. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator. See “ ...

  • Page 161

    ... Parallel This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATtiny2313. Pulses are assumed Programming least 250 ns unless otherwise noted. Parameters, Pin Mapping, and Commands Signal Names In this section, some pins of the ATtiny2313 are referenced by signal names describing their functionality during parallel programming, see following table are referenced by pin names ...

  • Page 162

    ... XA0 XA1/BS2 DATA I/O Table 72. Pin Values Used to Enter Programming Mode Table 73. XA1 and XA0 Coding XA1 Table 74. Command Byte Bit Coding Command Byte ATtiny2313 162 Pin Name I/O Function PD5 I XTAL Action Bit 0 XTAL Action Bit 1. PD6 I Byte Select 2 (“0” selects low byte, “1” selects 2’nd high byte) ...

  • Page 163

    Serial Table 75. Pin Mapping Serial Programming Programming Pin Mapping Parallel Programming Enter Programming The following algorithm puts the device in Parallel programming mode: Mode 1. Set Prog_enable pins listed in 0V. 2. Apply 4.5 - 5.5V between V 3. ...

  • Page 164

    ... Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command. ATtiny2313 164 2543L–AVR–08/10 ...

  • Page 165

    Programming the The Flash is organized in pages, see Flash program data is latched into a page buffer. This allows one page of program data to be pro- grammed simultaneously. The following procedure describes how to program the entire Flash ...

  • Page 166

    ... Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 70. Addressing the Flash Which is Organized in Pages Note: Figure 71. Programming the Flash Waveforms RDY/BSY RESET +12V PAGEL Note: ATtiny2313 166 PCMSB PROGRAM PCPAGE COUNTER PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE 1 ...

  • Page 167

    Programming the The EEPROM is organized in pages, see EEPROM EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as ...

  • Page 168

    ... Give WR a negative pulse and wait for RDY/BSY to go high Set BS2 to “0”. This selects low data byte. Figure 73. Programming the FUSES Waveforms RDY/BSY RESET +12V ATtiny2313 168 for details on Command and Address loading): for details on Command and Data loading): for details on Command and Data loading): ...

  • Page 169

    Programming the The algorithm for programming the Lock bits is as follows (refer to Lock Bits page 165 1. A: Load Command “0010 0000” Load Data Low Byte. Bit n = “0” programs the Lock bit ...

  • Page 170

    ... Figure 75. Parallel Programming Timing, Including some General Timing Requirements Characteristics (DATA, XA0/1, BS1, BS2) Figure 76. Parallel Programming Timing, Loading Sequence with Timing Requirements XTAL1 BS1 PAGEL DATA XA0 XA1 Note: ATtiny2313 170 for details on Command and Address loading): t XHXL XTAL1 t DVXH Data & Contol t BVPH ...

  • Page 171

    Figure 77. Parallel Programming Timing, Reading Sequence (within the Same Page) with Tim- ing Requirements XTAL1 BS1 DATA XA0 XA1 Note: Table 76. Parallel Programming Characteristics, V Symbol DVXH t XLXH t XHXL t XLDX ...

  • Page 172

    ... Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low:> 2 CPU clock cycles for f High:> 2 CPU clock cycles for f ATtiny2313 172 Parameter BS1 Valid to DATA valid ...

  • Page 173

    ... Serial Programming When writing serial data to the ATtiny2313, data is clocked on the rising edge of SCK. Algorithm When reading data from the ATtiny2313, data is clocked on the falling edge of SCK. See 79, Figure 80 To program and verify the ATtiny2313 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in 1 ...

  • Page 174

    ... Read EEPROM Memory 1010 0000 Write EEPROM Memory 1100 0000 Load EEPROM Memory 1100 0001 Page (page access) Write EEPROM Memory 1100 0010 Page (page access) ATtiny2313 174 SERIAL DATA INPUT MSB (MOSI) MSB (MISO) (SCK) SAMPLE Instruction Format Byte 2 ...

  • Page 175

    Table 78. Serial Programming Instruction Set Instruction Byte 1 Read Lock bits 0101 1000 Write Lock bits 1010 1100 Read Signature Byte 0011 0000 Write Fuse bits 1010 1100 Write Fuse High bits 1010 1100 Write Extended Fuse Bits 1010 ...

  • Page 176

    ... OVSH SCK t SHSL MISO Parameter Oscillator Frequency (ATtiny2313L) Oscillator Period (ATtiny2313L) Oscillator Frequency (ATtiny2313, V 5.5V) Oscillator Period (ATtiny2313 5.5V) SCK Pulse Width High SCK Pulse Width Low MOSI Setup to SCK High MOSI Hold after SCK High SCK Low to MISO Valid for f < ...

  • Page 177

    Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0. Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating ...

  • Page 178

    ... The sum of all IOH, for all ports, should not exceed 60 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. ATtiny2313 178 (1) (Continued) Condition Min ...

  • Page 179

    External Clock Figure 81. External Clock Drive Waveforms Drive Waveforms External Clock Table 80. External Clock Drive (Estimated Values) Drive Symbol 1/t CLCL t CLCL t CHCX t CLCX t CLCH t CHCL Δ t CLCL 2543L–AVR–08/10 V IH1 V ...

  • Page 180

    ... Figure 82. Maximum Frequency vs. V Figure 83. Maximum Frequency vs. V ATtiny2313 180 As shown in CC. curve is linear between 1.8V < ATtiny2313V CC 10 MHz Safe Operating Area 4 MHz 1.8V 2.7V , ATtiny2313 CC 20 MHz 10 MHz Safe Operating Area 2.7V Figure 82 and Figure 83, the Maximum < 2.7V and between 2.7V < 5.5V 4.5V 5.5V 2543L– ...

  • Page 181

    ... ATtiny2313 The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and Typical with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock Characteristics source ...

  • Page 182

    ... Figure 85. Active Supply Current vs. Frequency ( MHz) Figure 86. Active Supply Current vs. V ATtiny2313 182 ACTIVE SUPPLY CURRENT vs. FREQUENCY MHz 1 Frequency (MHz) CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz 1 4.0 V 3 (Internal RC Oscillator, 8 MHz) CC 3.5 4 4.5 5 5.5 (V) 5.5 V 5 ˚ ...

  • Page 183

    Figure 87. Active Supply Current vs. V Figure 88. Active Supply Current vs. V 2543L–AVR–08/10 CC ACTIVE SUPPLY CURRENT vs INTERNAL RC OSCILLATOR, 4 MHz 1 ACTIVE ...

  • Page 184

    ... Figure 89. Active Supply Current vs. V 1.2 0.8 0.6 0.4 0.2 Figure 90. Active Supply Current vs. V 0.14 0.12 0.1 0.08 0.06 0.04 0.02 ATtiny2313 184 (Internal RC Oscillator, 0.5 MHz) CC ACTIVE SUPPLY CURRENT vs INTERNAL RC OSCILLATOR, 0.5 MHz 1 0 1.5 2 2 (V) (Internal RC Oscillator, 128 KHz) CC ACTIVE SUPPLY CURRENT vs ...

  • Page 185

    Idle Supply Current Figure 91. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) 0.25 0.15 0.05 Figure 92. Idle Supply Current vs. Frequency ( MHz) 2543L–AVR–08/10 IDLE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 0.2 0.1 ...

  • Page 186

    ... Figure 93. Idle Supply Current vs. V 2.5 1.5 0.5 Figure 94. Idle Supply Current vs. V 1.6 1.4 1.2 0.8 0.6 0.4 0.2 ATtiny2313 186 (Internal RC Oscillator, 8 MHz) CC IDLE SUPPLY CURRENT vs INTERNAL RC OSCILLATOR, 8 MHz 1.5 2 2 (V) (Internal RC Oscillator, 4 MHz) CC IDLE SUPPLY CURRENT vs INTERNAL RC OSCILLATOR, 4 MHz ...

  • Page 187

    Figure 95. Idle Supply Current vs. V Figure 96. Idle Supply Current vs. V 0.25 0.15 0.05 2543L–AVR–08/10 (Internal RC Oscillator, 1 MHz) CC IDLE SUPPLY CURRENT vs INTERNAL RC OSCILLATOR, 1 MHz 0.5 0.4 0.3 0.2 0.1 ...

  • Page 188

    ... Figure 97. Idle Supply Current vs. V 0.035 0.03 0.025 0.02 0.015 0.01 0.005 Power-down Supply Figure 98. Power-down Supply Current vs. V Current 1.25 0.75 0.25 ATtiny2313 188 (Internal RC Oscillator, 128 KHz) CC IDLE SUPPLY CURRENT vs INTERNAL RC OSCILLATOR, 128 KHz 0 1 (V) POWER-DOWN SUPPLY CURRENT vs WATCHDOG TIMER DISABLED 1 ...

  • Page 189

    Figure 99. Power-down Supply Current vs. V Standby Supply Figure 100. Standby Supply Current vs. V Current 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 2543L–AVR–08/10 POWER-DOWN SUPPLY CURRENT vs WATCHDOG TIMER ENABLED ...

  • Page 190

    ... Pin Pull-up Figure 101. I/O Pin Pull-up Resistor Current vs. Input Voltage (V 160 140 85 °C 120 100 Figure 102. I/O Pin Pull-up Resistor Current vs. Input Voltage (V 85 °C ATtiny2313 190 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 25 °C -40 ° 0 ...

  • Page 191

    Figure 103. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V -40 °C Figure 104. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V -40 °C 2543L–AVR–08/10 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 120 25 °C 100 85 ...

  • Page 192

    ... Pin Driver Strength Figure 105. I/O Pin Source Current vs. Output Voltage (V Figure 106. I/O Pin Source Current vs. Output Voltage (V ATtiny2313 192 I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = °C 70 -40 ° ° 3.2 3.4 3.6 3.8 V I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2 ...

  • Page 193

    Figure 107. I/O Pin Source Current vs. Output Voltage (V 25 °C Figure 108. I/O Pin Sink Current vs. Output Voltage (V 2543L–AVR–08/10 I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 1.8V 9 -40 ° °C ...

  • Page 194

    ... Figure 109. I/O Pin Sink Current vs. Output Voltage (V Figure 110. I/O Pin Sink Current vs. Output Voltage (V ATtiny2313 194 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 2. 0.2 0.4 0.6 0.8 V I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.2 0.4 0.6 0 2.7V 1.2 1.4 1.6 1 ...

  • Page 195

    Figure 111. Reset I/O Pin Source Current vs. Output Voltage (V 25 °C Figure 112. Reset I/O Pin Source Current vs. Output Voltage (V 25 °C 2543L–AVR–08/10 RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 16 -40 ° ...

  • Page 196

    ... Figure 113. Reset I/O Pin Source Current vs. Output Voltage (V 1.4 1.2 25 °C 0.8 0.6 0.4 0.2 Figure 114. Reset I/O Pin Sink Current vs. Output Voltage (V ATtiny2313 196 RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 1.8V -40 ° ° 0.2 0.4 0.6 0.8 V RESET I/O PIN SINK CURRENT vs ...

  • Page 197

    Figure 115. Reset I/O Pin Sink Current vs. Output Voltage (V Figure 116. Reset I/O Pin Sink Current vs. Output Voltage (V 2543L–AVR–08/10 RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 4.5 4 3.5 3 2.5 2 1.5 1 0.5 ...

  • Page 198

    ... Pin Thresholds and Figure 117. I/O Pin Input Threshold Voltage vs. V Hysteresis Figure 118. I/O Pin Input Threshold Voltage vs. V 2.5 1.5 0.5 ATtiny2313 198 I/O PIN INPUT THRESHOLD VOLTAGE vs VIH, IO PIN READ AS '1' 3 2.5 2 1.5 1 0.5 0 1 I/O PIN INPUT THRESHOLD VOLTAGE vs ...

  • Page 199

    Figure 119. Reset I/O Input Threshold Voltage vs. V Figure 120. Reset I/O Input Threshold Voltage vs. V 2543L–AVR–08/10 RESET I/O PIN INPUT THRESHOLD VOLTAGE vs VIH, IO PIN READ AS '1' 3 2.5 2 1.5 1 0.5 ...

  • Page 200

    ... Figure 121. Reset I/O Input Pin Hysteresis vs. V 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 Figure 122. Reset Input Threshold Voltage vs. V 2.5 1.5 0.5 ATtiny2313 200 RESET I/O INPUT PIN HYSTERESIS vs -40 °C 25 °C 85 °C 0 1.5 2 2 RESET INPUT THRESHOLD VOLTAGE vs ...