ATTINY2313-20PU Atmel, ATTINY2313-20PU Datasheet
ATTINY2313-20PU
Specifications of ATTINY2313-20PU
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ATTINY2313-20PU Summary of contents
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... Speed Grades – ATtiny2313V: 0 – 4 MHz @ 1.8 - 5.5V, 0 – 10 MHz @ 2.7 – 5.5V – ATtiny2313: 0 – 10 MHz @ 2.7 - 5.5V, 0 – 20 MHz @ 4.5 – 5.5V • Typical Power Consumption – Active Mode 1 MHz, 1.8V: 230 µA 32 kHz, 1.8V: 20 µ ...
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... Figure 1. Pinout ATtiny2313 Configurations Overview The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. ...
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Block Diagram Figure 2. Block Diagram VCC GND 2543LS–AVR–08/10 PA0 - PA2 PORTA DRIVERS DATA REGISTER DATA DIR. REG. PORTA PORTA 8-BIT DATA BUS STACK PROGRAM POINTER COUNTER PROGRAM SRAM FLASH INSTRUCTION GENERAL REGISTER PURPOSE REGISTER INSTRUCTION DECODER CONTROL ALU ...
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... RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny2313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny2313 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. ...
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... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATtiny2313 as listed on 56. RESET Reset input ...
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... C is compiler dependent. Please confirm with the C compiler documen- tation for more details. Disclaimer Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. ATtiny2313 6 2543LS–AVR–08/10 ...
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Register Summary Address Name Bit 7 0x3F (0x5F) SREG I 0x3E (0x5E) Reserved – 0x3D (0x5D) SPL SP7 0x3C (0x5C) OCR0B 0x3B (0x5B) GIMSK INT1 0x3A (0x5A) EIFR INTF1 0x39 (0x59) TIMSK TOIE1 0x38 (0x58) TIFR TOV1 0x37 (0x57) SPMCSR ...
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... CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. ATtiny2313 8 2543LS–AVR–08/10 ...
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Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant ...
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... Rd Pop Register from Stack MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break ATtiny2313 10 Description Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Rd(n) ← Rd(n+1), n=0..6 Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) SREG(s) ← 1 SREG(s) ← ← Rr(b) Rd(b) ← ← ← ← ...
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... Body, Quad Flat No-Lead/Micro Lead Frame Package (MLF) 2543LS–AVR–08/10 (4) Ordering Code Package ATtiny2313V-10PU 20P3 ATtiny2313V-10SU 20S ATtiny2313V-10SUR 20S ATtiny2313V-10MU 20M1 ATtiny2313V-10MUR 20M1 ATtiny2313-20PU 20P3 ATtiny2313-20SU 20S ATtiny2313-20SUR 20S ATtiny2313-20MU 20M1 ATtiny2313-20MUR 20M1 and Figure 83 on page 180. Package Type (2) ...
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... A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R ATtiny2313 12 D PIN TITLE 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual ...
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20S 2543LS–AVR–08/10 13 ...
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... TOP VIEW D2 Pin #1 Notch (0. BOTTOM VIEW Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. 2325 Orchard Parkway San Jose, CA 95131 R ATtiny2313 TITLE 20M1, 20-pad 0.8 mm Body, Lead Pitch 0.50 mm, 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) SIDE VIEW A2 ...
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... Errata The revision in this section refers to the revision of the ATtiny2313 device. ATtiny2313 Rev C No known errata ATtiny2313 Rev B • Wrong values read after Erase Only operation • Parallel Programming does not work • Watchdog Timer Interrupt disabled • EEPROM can not be written below 1.9 volts 1 ...
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... Changes from Rev. 2543G-10/ Rev. 2543H-02/05 2. ATtiny2313 16 “Ordering Information” on page Added device Rev C “No known errata” in Updated template Changed device status to “Not recommended for new designs.” Updated “Stack Pointer” on page Updated Table “Sleep Mode Select” on page Updated “ ...
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... Updated Figure 1 on page 2. Updated “Ordering Information” on page Updated “Maximum Speed vs. V Updated “ATtiny2313 Typical Characteristics” on page Updated Table 2 on page 23. Replaced “Watchdog Timer” on page Added “Maximum Speed vs “Serial Programming Algorithm” on page 173 Changed mA to µ ...
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... Rev. 2543B-09/ ATtiny2313 18 Package drawing “20P3” on page 216 Updated C-code examples. Renamed instances of SPMEN to SELFPRGEN, Self Programming Enable. Updated “Calibrated Internal RC Oscillator” on page Fixed typo from UART to USART and updated Speed Grades and Power Consumption Estimates in “Features” on page Updated “ ...
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2543LS–AVR–08/10 19 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...