ATTINY2313V-10PU Atmel, ATTINY2313V-10PU Datasheet
ATTINY2313V-10PU
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ATTINY2313V-10PU Summary of contents
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... Speed Grades – ATtiny2313V: 0 – 4 MHz @ 1.8 - 5.5V, 0 – 10 MHz @ 2.7 – 5.5V – ATtiny2313: 0 – 10 MHz @ 2.7 - 5.5V, 0 – 20 MHz @ 4.5 – 5.5V • Typical Power Consumption – Active Mode 1 MHz, 1.8V: 230 µ ...
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Pin Figure 1. Pinout ATtiny2313 Configurations Overview The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz ...
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Block Diagram Figure 2. Block Diagram VCC GND 2543L–AVR–08/10 PA0 - PA2 PORTA DRIVERS DATA REGISTER DATA DIR. REG. PORTA PORTA 8-BIT DATA BUS STACK PROGRAM POINTER COUNTER PROGRAM SRAM FLASH INSTRUCTION GENERAL REGISTER PURPOSE REGISTER INSTRUCTION DECODER CONTROL ALU ...
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... On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface conventional non-volatile memory programmer. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny2313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications ...
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Pin Descriptions VCC Digital supply voltage. GND Ground. Port A (PA2..PA0) Port 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink ...
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... Information Resources A comprehensive set of development tools, application notes and datasheets are available for downloadon http://www.atmel.com/avr. Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation ...
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AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and ...
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Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look ...
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The AVR Status Register – SREG – is defined as: Bit Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt ...
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Figure 4. AVR CPU General Purpose Working Registers Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in directly into the first 32 locations ...
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Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the ...
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Figure 7. Single Cycle ALU Operation Register Operands Fetch ALU Operation Execute Reset and The AVR provides several different interrupt sources. These interrupts and the separate Reset Interrupt Handling Vector each have a separate program vector in the program memory ...
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CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.. Assembly Code Example in r16, SREG cli sbi EECR, EEMPE sbi EECR, EEPE out SREG, r16 C Code Example char ...
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AVR ATtiny2313 This section describes the different memories in the ATtiny2313. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the Memories ATtiny2313 features an EEPROM Memory for data storage. All ...
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SRAM Data Figure 9 Memory The lower 224 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the ...
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Figure 10. On-chip Data SRAM Access Cycles EEPROM Data The ATtiny2313 contains 128 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance ...
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Bits 6..0 – EEAR6..0: EEPROM Address The EEPROM Address Register – EEAR specify the EEPROM address in the 128 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127. The ini- tial value of EEAR ...
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Bit 2 – EEMPE: EEPROM Master Program Enable The EEMPE bit determines whether writing EEPE to one will have effect or not. When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected ...
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The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glob- ally) so that no interrupts will occur during execution of these functions. ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion ...
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I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the ...
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System Clock and Clock Options Clock Systems Figure 11 and their need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, ...
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Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 2. Device ...
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Figure 12. Crystal Oscillator Connections The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 4. Crystal Oscillator Operating Modes CKSEL3..1 (2) ...
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... OSCCAL Register and thereby automatically calibrates the RC Oscillator and 25°C, this calibration gives a frequency within ± 10% of the nominal frequency. Using calibration methods as described in application notes available at www.atmel.com/avr it is possi- ble to achieve ± 2% accuracy at any given V as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “ ...
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When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 7. Table 7. Start-up times for the internal calibrated RC Oscillator clock selection SUT1.. ( Note: Oscillator Calibration Bit ...
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External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in 13. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 13. External Clock Drive ...
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Internal The 128 kHz Internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre- Oscillator quency is nominal and 25°C. This clock may be selected as the system clock by ...
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CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. • Bits 3:0 – CLKPS3:0: Clock ...
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Power Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- Management tion to the application’s requirements. and Sleep To ...
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Power-down Mode When the SM1..0 bits are written 11, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the USI start condition detection, and the ...
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Refer to on how to configure the Brown-out Detector. Internal Voltage The Internal Voltage Reference will be enabled when needed by the Brown-out Detection or the Reference Analog Comparator. If these modules are disabled ...
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System Control and Reset Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be an RJMP – Relative ...
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Table 15. Reset Characteristics Symbol V POT V RST t RST Notes: Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in POR circuit can be used to trigger the ...
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Figure 16. MCU Start-up, RESET Extended Externally TIME-OUT INTERNAL External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Shorter pulses are not guaranteed to generate ...
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... V antees that a Brown-Out Reset will occur before V operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 110 for ATtiny2313V and BODLEVEL = 101 for ATtiny2313L. Parameter Brown-out Detector Hysteresis Min Pulse Width on Brown-out Reset ...
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Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t page 44 Figure 19. Watchdog ...
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Internal Voltage ATtiny2313 features an internal bandgap reference. This reference is used for Brown-out Detec- Reference tion, and it can be used as an input to the Analog Comparator. Voltage Reference The voltage reference has a start-up time that may ...
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Watchdog Timer ATtiny2313 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to ...
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The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of ...
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The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example WDT_Prescaler_Change: C Code Example void WDT_Prescaler_Change(void Note: Note: The Watchdog Timer should be reset before ...
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Watchdog Timer Bit Control Register - WDTCSR Read/Write Initial Value • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config- ured for interrupt. WDIF ...
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Table 20. Watchdog Timer Prescale Select WDP3 2543L–AVR–08/10 Number of WDT Oscillator WDP2 WDP1 WDP0 (2048) cycles ...
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Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny2313. For a general explanation of the AVR interrupt handling, refer to page 12. Interrupt Vectors Table 21. Reset and Interrupt Vectors in ATtiny2313 Vector No. 1 ...
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The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny2313 is: Address Labels Code 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 ; ...
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I/O-Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI ...
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Ports as General The ports are bi-directional I/O ports with optional internal pull-ups. description of one I/O-port pin, here generically called Pxn. Digital I/O Figure 22. General Digital I/O Note: Configuring the Pin Each port pin consists of three register ...
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Switching Between When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} Input and Output = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. ...
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Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ...
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The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The ...
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Alternate Port Most port pins have alternate functions in addition to being general digital I/Os. how the port pin control signals from the simplified Functions functions. The overriding signals may not be present in all port pins, but the figure ...
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Table 23. Generic Description of Overriding Signals for Alternate Functions Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to ...
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MCU Control Register Bit – MCUCR Read/Write Initial Value • Bit 7 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured ...
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DI/SDA/PCINT5 - Port B, Bit 5 DI: Three-wire mode Universal Serial Interface Data input. Three-wire mode does not override normal port functions, so pin must be configured as an input. SDA: Two-wire mode Serial Inter- face Data. PCINT5: Pin ...
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Table 26. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 27. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE ...
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Alternate Functions of The Port D pins with alternate functions are shown in Port D Table 28. Port D Pins Alternate Functions Port Pin PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: • ICP ...
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Table 29 Figure 25 on page Table 29. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 30. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV ...
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Register Description for I/O-Ports Port A Data Register – Bit PORTA Read/Write Initial Value Port A Data Direction Bit Register – DDRA Read/Write Initial Value Port A Input Pins Bit Address – PINA Read/Write Initial Value Port B Data Register ...
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External The External Interrupts are triggered by the INT0 pin, INT1 pin or any of the PCINT7..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0, INT1 or PCINT7..0 pins are Interrupts configured as outputs. This ...
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Read/Write Initial Value • Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre- sponding interrupt mask ...
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When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU Control Register – ...
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Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event man- Timer/Counter0 agement) and wave generation. The main features are: with PWM • Two ...
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Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com- pare Unit, in this case Compare ...
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Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02 the timer is stopped. However, ...
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The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is disabled. The double buffering synchronizes the update ...
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Figure 30. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out- put) ...
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TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, ...
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As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = ...
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The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represents special cases when generating a PWM ...
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Figure 33. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches ...
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The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. Timer/Counter The Timer/Counter is a ...
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Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- caler (f clk_I/O clk clk (clk I/O TCNTn (CTC) OCRnx OCFnx ATtiny2313 72 /8) I/O Tn /8) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP 2543L–AVR–08/10 ...
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Timer/Counter Register Description Timer/Counter Control Bit Register A – TCCR0A Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 ...
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Table 36 PWM mode. Table 36. Compare Output Mode, Phase Correct PWM Mode COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one ...
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Table 39 PWM mode. Table 39. Compare Output Mode, Phase Correct PWM Mode COM0B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313 and will always read as ...
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Timer/Counter Control Bit Register B – TCCR0B Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, ...
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Table 41. Clock Select Bit Description CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as ...
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Timer/Counter Bit Interrupt Mask Register – TIMSK Read/Write Initial Value • Bit 4 – Res: Reserved Bit This bit is reserved bit in the ATtiny2313 and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter0 Output Compare Match ...
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When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. 2543L–AVR–08/10 79 ...
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Timer/Counter0 Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and and Timer/Counter0. Timer/Counter1 Prescalers Internal Clock Source The Timer/Counter can be clocked directly by the ...
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However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances recommended that maximum frequency of an external clock source is less than f ...
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The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: Timer/Counter1 • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered ...
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Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are described in the section page 84. The Timer/Counter ...
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The following bits are added to the 16-bit Timer/Counter Control Registers: • FOC1A and FOC1B are added to TCCR1A. • WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. Accessing ...
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Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions ...
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The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNT1: ; Save global interrupt ...
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The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: C Code Example void ...
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Timer/Counter The Timer/Counter can be clocked by an internal or an external clock source. The clock source Clock Sources is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control ...
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The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture ...
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For more information on how to access the 16-bit registers refer to on page Input Capture Trigger The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Source Timer/Counter1 can alternatively use the Analog Comparator ...
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Waveform Generator for handling the special cases of the extreme values in some modes of operation A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In ...
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For more information of how to access the 16-bit registers refer to on page Force Output In non-PWM Waveform Generation modes, the match output of the comparator can be forced by Compare writing a one to the Force Output Compare ...
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Compare Match The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Output Unit Secondly the COM1x1:0 bits control the OC1x pin ...
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Compare Output Mode The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. and Waveform For all modes, setting the COM1x1 tells the Waveform Generator that no action on the Generation OC1x Register is ...
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Figure 45. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag according to the register used to define ...
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Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope ...
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Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 ...
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Phase Correct PWM The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13 Mode 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like ...
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TOP). The interrupt flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or ...
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Phase and Frequency The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM Correct PWM Mode mode (WGM13 provides a high resolution phase and frequency correct PWM wave- form generation option. The ...
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The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OCF1A ...
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Timer/Counter The Timer/Counter is a synchronous design and the timer clock (clk Timing Diagrams clock enable signal in the following figures. The figures include information on when interrupt flags are set, and when the OCR1x Register is updated with the ...
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Figure 51. Timer/Counter Timing Diagram, no Prescaling (PC and PFC PWM) Figure 52 Figure 52. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 2543L–AVR–08/10 clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn ...
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Timer/Counter Register Description Timer/Counter1 Bit Control Register A – TCCR1A Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 ...
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Note: Table 45 rect or the phase and frequency correct, PWM mode. Table 45. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits ...
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Table 46. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...
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Timer/Counter1 Bit Control Register B – TCCR1B Read/Write Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the ...
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Timer/Counter1 Bit Control Register C – TCCR1C Read/Write Initial Value • Bit 7 – FOC1A: Force Output Compare for Channel A • Bit 6 – FOC1B: Force Output Compare for Channel B The FOC1A/FOC1B bits are only active when the ...
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Output Compare Bit Register OCR1BH and OCR1BL Read/Write Initial Value The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare ...
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When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page Timer/Counter Bit Interrupt Flag Register – ...
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USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or ...
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The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The Clock Generation logic consists of synchronization logic for ...
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Figure 54. Clock Generation Logic, Block Diagram Signal description: txclk rxclk xcki xcko fosc Internal Clock Internal clock generation is used for the asynchronous and the synchronous master modes of Generation – The operation. The description in this section refers ...
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BAUD Baud rate (in bits per second, bps) f OSC UBRR Contents of the UBRRH and UBRRL Registers, (0-4095) Some examples of UBRR values for some system clock frequencies are found in page 134). Double Speed The transfer rate can ...
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XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge. Frame Formats A serial frame is defined to be one character of ...
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If used, the parity bit is located between the last data bit and first stop bit of a serial frame. USART The USART has to be initialized before any communication can take place. The initialization pro- Initialization cess ...
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More advanced initialization routines can be made that include frame format as parameters, dis- able interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization ...
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Data Transmission The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB – The USART Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid- den by the USART ...
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Sending Frames with If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB 9 Data Bit before the low byte of the character is written to UDR. The following code ...
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Transmitter Flags and The USART Transmitter has two flags that indicate its state: USART Data Register Empty Interrupts (UDRE) and Transmit Complete (TXC). Both flags can be used for generating interrupts. The Data Register Empty (UDRE) flag indicates whether the ...
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Data Reception – The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Regis- ter to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden The USART by ...
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Receiving Frames with If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB 9 Data Bits before reading the low bits from the UDR. This rule applies to the FE, DOR and ...
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Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as ...
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Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the ...
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Asynchronous Clock The clock recovery logic synchronizes internal clock to the incoming serial frames. Recovery illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and ...
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Figure 59. Stop Bit Sampling and Next Start Bit Sampling Sample (U2X = 0) Sample (U2X = 1) The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop ...
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Table 49. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) # (Data+Parity Bit) Table 50. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X = 1) # (Data+Parity Bit) The recommendations of the ...
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Multi-processor Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a filtering Communication function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. ...
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USART Register Description USART I/O Data Bit Register – UDR Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. The Transmit ...
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Bit 5 – UDRE: USART Data Register Empty The UDRE flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is empty, and therefore ready to be written. The UDRE ...
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USART Control and Bit Status Register B – UCSRB Read/Write Initial Value • Bit 7 – RXCIE: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated ...
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USART Control and Bit Status Register C – UCSRC Read/Write Initial Value • Bit 6 – UMSEL: USART Mode Select This bit selects between asynchronous and synchronous mode of operation. Table 51. UMSEL Bit Settings • Bit 5:4 – UPM1:0: ...
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Table 54. UCSZ Bits Settings UCSZ2 • Bit 0 – UCPOL: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output ...
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Examples of Baud For standard crystal and resonator frequencies, the most commonly used baud rates for asyn- Rate Setting chronous operation can be generated by using the UBRR settings in which yield an actual baud rate differing less than 0.5% ...
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Table 57. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...
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Table 58. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...
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Table 59. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) Baud Rate (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M (1) Max. 1. 2543L–AVR–08/10 U2X = 0 UBRR Error 416 -0.1% ...
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Universal Serial The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly Interface – USI higher transfer rates and uses less code space than ...
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The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start con- dition is detected, or after ...
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The Three-wire mode timing is shown in Figure 62. At the top of the figure is a USCK cycle refer- ence. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is ...
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The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/2): SPITransfer_Fast: ret SPI Slave Operation The following code demonstrates how to use the USI module as a SPI Slave: Example ...
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Master is stored back into the r16 Register. Note that the first two instructions is for initialization only and needs only to be executed once.These instructions sets Three-wire mode and ...
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Figure 64. Two-wire Mode, Typical Timing Diagram SDA SCL Referring to the timing diagram (Figure 64.), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while ...
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Start Condition The start condition detector is shown in Figure 65. The SDA line is delayed (in the range Detector 300 ns) to ensure valid sampling of the SCL line. The start condition detector is working asynchronously ...
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USI Status Register – Bit USISR Read/Write Initial Value The Status Register contains interrupt flags, line status flags and the counter value. • Bit 7 – USISIF: Start Condition Interrupt Flag When Two-wire mode is selected, the USISIF flag is ...
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Bit 7 – USISIE: Start Condition Interrupt Enable Setting this bit to one enables the Start Condition detector interrupt. If there is a pending inter- rupt when the USISIE and the Global Interrupt Enable Flag is set to one, ...
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Table 60. Relations between USIWM1..0 and the USI Operation USIWM1 Note: 2543L–AVR–08/10 USIWM0 Description 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. ...
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Bit 3..2 – USICS1..0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data ...
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Analog The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin Comparator AIN1, the Analog Comparator output, ...
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When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com- parator interrupt is activated. When written logic zero, the interrupt is disabled. • Bit 2 – ACIC: Analog Comparator Input ...
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On- chip Debug System Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or for other ...
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Connecting the RESET pin directly to V • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. Software Break debugWIRE supports Program memory Break Points by the AVR ...
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Self- The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associ- Programming ated protocol to read code and write (program) that code into the ...
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Addressing the The Z-pointer is used to address the SPM commands. Flash During Self- Bit Programming ZH (R31) ZL (R30) Since the Flash is organized in pages (see treated as having two different sections. One section, consisting of the least ...
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Store Program The Store Program Memory Control and Status Register contains the control bits needed to con- Memory Control and trol the Program memory operations. Status Register – Bit SPMCSR Read/Write Initial Value • Bits 7..5 – Res: Reserved Bits ...
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EEPROM Write Note that an EEPROM write operation will block all software programming to Flash. Reading the Prevents Writing to Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It SPMCSR is recommended that ...
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Preventing Flash During periods of low V Corruption too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. ...
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Memory Programming Program And Data The ATtiny2313 provides two Lock bits which can be left unprogrammed (“1”) or can be pro- Memory Lock Bits grammed (“0”) to obtain the additional features listed in erased to “1” with the Chip Erase ...
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Fuse Bits The ATtiny2313 has three Fuse bytes. all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logi- cal zero, “0”, if they are programmed. Table 66. Fuse Extended Byte ...
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... EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space. ...
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Parallel This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATtiny2313. Pulses are assumed Programming least 250 ns unless otherwise noted. Parameters, Pin ...
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Table 71. Pin Name Mapping (Continued) Signal Name in Programming Mode XA0 XA1/BS2 DATA I/O Table 72. Pin Values Used to Enter Programming Mode Table 73. XA1 and XA0 Coding XA1 Table 74. Command Byte Bit ...
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Serial Table 75. Pin Mapping Serial Programming Programming Pin Mapping Parallel Programming Enter Programming The following algorithm puts the device in Parallel programming mode: Mode 1. Set Prog_enable pins listed in 0V. 2. Apply 4.5 - 5.5V between V 3. ...
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Load Command “Chip Erase” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads ...
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Programming the The Flash is organized in pages, see Flash program data is latched into a page buffer. This allows one page of program data to be pro- grammed simultaneously. The following procedure describes how to program the entire Flash ...
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Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 70. Addressing the Flash Which is Organized in Pages Note: Figure 71. Programming the Flash Waveforms RDY/BSY RESET +12V PAGEL Note: ATtiny2313 ...
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Programming the The EEPROM is organized in pages, see EEPROM EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as ...
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Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to on page 165 1. A: Load Command “0000 0011” Load Address High Byte (0x00 - 0xFF Load Address Low Byte (0x00 ...
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Programming the The algorithm for programming the Lock bits is as follows (refer to Lock Bits page 165 1. A: Load Command “0010 0000” Load Data Low Byte. Bit n = “0” programs the Lock bit ...
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Reading the The algorithm for reading the Calibration byte is as follows (refer to Calibration Byte page 165 1. A: Load Command “0000 1000” Load Address Low Byte, 0x00. 3. Set OE to “0”, and BS1 to “1”. ...
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Figure 77. Parallel Programming Timing, Reading Sequence (within the Same Page) with Tim- ing Requirements XTAL1 BS1 DATA XA0 XA1 Note: Table 76. Parallel Programming Characteristics, V Symbol DVXH t XLXH t XHXL t XLDX ...
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Table 76. Parallel Programming Characteristics, V Symbol t BVDV t OLDV t OHDZ Notes: Serial Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while Downloading RESET is pulled to GND. The serial interface ...
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Serial Programming When writing serial data to the ATtiny2313, data is clocked on the rising edge of SCK. Algorithm When reading data from the ATtiny2313, data is clocked on the falling edge of SCK. See 79, Figure 80 To program ...
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Table 77. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol t WD_FLASH t WD_EEPROM t WD_ERASE t WD_FUSE Figure 79. Serial Programming Waveforms SERIAL DATA OUTPUT SERIAL CLOCK INPUT Table 78. Serial Programming Instruction Set Instruction ...
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Table 78. Serial Programming Instruction Set Instruction Byte 1 Read Lock bits 0101 1000 Write Lock bits 1010 1100 Read Signature Byte 0011 0000 Write Fuse bits 1010 1100 Write Fuse High bits 1010 1100 Write Extended Fuse Bits 1010 ...
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Serial Programming Figure 80. Serial Programming Timing Characteristics Table 79. Serial Programming Characteristics, T Otherwise Noted) Symbol 1/t CLCL t CLCL 1/t CLCL t CLCL t SHSL t SLSH t OVSH t SHOX t SLIV Note: ATtiny2313 176 MOSI t ...
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Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0. Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating ...
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T = -40°C to +85° 1.8V to 5.5V (unless otherwise noted Symbol Parameter Power Supply Current I CC Power-down mode Analog Comparator V ACIO Input Offset Voltage Analog Comparator I ACLK Input Leakage Current Analog Comparator ...
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External Clock Figure 81. External Clock Drive Waveforms Drive Waveforms External Clock Table 80. External Clock Drive (Estimated Values) Drive Symbol 1/t CLCL t CLCL t CHCX t CLCX t CLCH t CHCL Δ t CLCL 2543L–AVR–08/10 V IH1 V ...
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... Maximum Speed Maximum frequency is dependent on V vs. V Frequency vs Figure 82. Maximum Frequency vs. V Figure 83. Maximum Frequency vs. V ATtiny2313 180 As shown in CC. curve is linear between 1.8V < ATtiny2313V CC 10 MHz Safe Operating Area 4 MHz 1.8V 2.7V , ATtiny2313 CC 20 MHz 10 MHz Safe Operating Area 2.7V ...
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ATtiny2313 The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and Typical with internal pull-ups enabled. A sine wave generator with rail-to-rail output ...
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Figure 85. Active Supply Current vs. Frequency ( MHz) Figure 86. Active Supply Current vs. V ATtiny2313 182 ACTIVE SUPPLY CURRENT vs. FREQUENCY MHz 1 ...
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Figure 87. Active Supply Current vs. V Figure 88. Active Supply Current vs. V 2543L–AVR–08/10 CC ACTIVE SUPPLY CURRENT vs INTERNAL RC OSCILLATOR, 4 MHz 1 ACTIVE ...
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Figure 89. Active Supply Current vs. V 1.2 0.8 0.6 0.4 0.2 Figure 90. Active Supply Current vs. V 0.14 0.12 0.1 0.08 0.06 0.04 0.02 ATtiny2313 184 (Internal RC Oscillator, 0.5 MHz) CC ACTIVE SUPPLY CURRENT vs ...
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Idle Supply Current Figure 91. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) 0.25 0.15 0.05 Figure 92. Idle Supply Current vs. Frequency ( MHz) 2543L–AVR–08/10 IDLE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 0.2 0.1 ...
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Figure 93. Idle Supply Current vs. V 2.5 1.5 0.5 Figure 94. Idle Supply Current vs. V 1.6 1.4 1.2 0.8 0.6 0.4 0.2 ATtiny2313 186 (Internal RC Oscillator, 8 MHz) CC IDLE SUPPLY CURRENT vs INTERNAL RC ...
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Figure 95. Idle Supply Current vs. V Figure 96. Idle Supply Current vs. V 0.25 0.15 0.05 2543L–AVR–08/10 (Internal RC Oscillator, 1 MHz) CC IDLE SUPPLY CURRENT vs INTERNAL RC OSCILLATOR, 1 MHz 0.5 0.4 0.3 0.2 0.1 ...
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Figure 97. Idle Supply Current vs. V 0.035 0.03 0.025 0.02 0.015 0.01 0.005 Power-down Supply Figure 98. Power-down Supply Current vs. V Current 1.25 0.75 0.25 ATtiny2313 188 (Internal RC Oscillator, 128 KHz) CC IDLE SUPPLY CURRENT vs. V ...
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Figure 99. Power-down Supply Current vs. V Standby Supply Figure 100. Standby Supply Current vs. V Current 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 2543L–AVR–08/10 POWER-DOWN SUPPLY CURRENT vs WATCHDOG TIMER ENABLED ...
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Pin Pull-up Figure 101. I/O Pin Pull-up Resistor Current vs. Input Voltage (V 160 140 85 °C 120 100 Figure 102. I/O Pin Pull-up Resistor Current vs. Input Voltage (V 85 °C ATtiny2313 190 I/O PIN PULL-UP RESISTOR CURRENT vs. ...
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Figure 103. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V -40 °C Figure 104. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V -40 °C 2543L–AVR–08/10 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 120 25 °C 100 85 ...
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Pin Driver Strength Figure 105. I/O Pin Source Current vs. Output Voltage (V Figure 106. I/O Pin Source Current vs. Output Voltage (V ATtiny2313 192 I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = °C 70 ...
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Figure 107. I/O Pin Source Current vs. Output Voltage (V 25 °C Figure 108. I/O Pin Sink Current vs. Output Voltage (V 2543L–AVR–08/10 I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 1.8V 9 -40 ° °C ...
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Figure 109. I/O Pin Sink Current vs. Output Voltage (V Figure 110. I/O Pin Sink Current vs. Output Voltage (V ATtiny2313 194 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 2. ...
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Figure 111. Reset I/O Pin Source Current vs. Output Voltage (V 25 °C Figure 112. Reset I/O Pin Source Current vs. Output Voltage (V 25 °C 2543L–AVR–08/10 RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 16 -40 ° ...
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Figure 113. Reset I/O Pin Source Current vs. Output Voltage (V 1.4 1.2 25 °C 0.8 0.6 0.4 0.2 Figure 114. Reset I/O Pin Sink Current vs. Output Voltage (V ATtiny2313 196 RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ...
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Figure 115. Reset I/O Pin Sink Current vs. Output Voltage (V Figure 116. Reset I/O Pin Sink Current vs. Output Voltage (V 2543L–AVR–08/10 RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 4.5 4 3.5 3 2.5 2 1.5 1 0.5 ...
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Pin Thresholds and Figure 117. I/O Pin Input Threshold Voltage vs. V Hysteresis Figure 118. I/O Pin Input Threshold Voltage vs. V 2.5 1.5 0.5 ATtiny2313 198 I/O PIN INPUT THRESHOLD VOLTAGE vs VIH, IO PIN READ AS ...
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Figure 119. Reset I/O Input Threshold Voltage vs. V Figure 120. Reset I/O Input Threshold Voltage vs. V 2543L–AVR–08/10 RESET I/O PIN INPUT THRESHOLD VOLTAGE vs VIH, IO PIN READ AS '1' 3 2.5 2 1.5 1 0.5 ...
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Figure 121. Reset I/O Input Pin Hysteresis vs. V 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 Figure 122. Reset Input Threshold Voltage vs. V 2.5 1.5 0.5 ATtiny2313 200 RESET I/O INPUT PIN HYSTERESIS vs ...