PIC24F16KA101-I/MQ Microchip Technology, PIC24F16KA101-I/MQ Datasheet - Page 107

IC PIC MCU FLASH 2KX16 20-QFN

PIC24F16KA101-I/MQ

Manufacturer Part Number
PIC24F16KA101-I/MQ
Description
IC PIC MCU FLASH 2KX16 20-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr

Specifications of PIC24F16KA101-I/MQ

Program Memory Type
FLASH
Program Memory Size
16KB (5.5K x 24)
Package / Case
20-VQFN
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24F
Core
PIC
Data Bus Width
16 bit
Data Ram Size
1.5 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24F16KA101-I/MQ
Manufacturer:
SIEMENS
Quantity:
43
REGISTER 10-1:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-2
bit 1
bit 0
Note 1:
R/W-0
DSEN
U-0
2:
All register bits are reset only in the case of a POR event outside of Deep Sleep mode.
Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this
re-arms POR.
DSEN: Deep Sleep Enable bit
1 = Enters Deep Sleep on execution of PWRSAV #0
0 = Enters normal Sleep on execution of PWRSAV #0
Unimplemented: Read as ‘0’
DSBOR: Deep Sleep BOR Event bit
1 = The DSBOR was active and a BOR event was detected during Deep Sleep
0 = The DSBOR was not active, or was active but did not detect a BOR event during Deep Sleep
RELEASE: I/O Pin State Release bit
1 = Upon waking from Deep Sleep, I/O pins maintain their states previous to Deep Sleep entry
0 = Release I/O pins from their state previous to Deep Sleep entry, and allow their respective TRIS and
LAT bits to control their states
U-0
U-0
DSCON: DEEP SLEEP CONTROL REGISTER
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U-0
U-0
U-0
U-0
(2)
Preliminary
PIC24F16KA102 FAMILY
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
(1)
U-0
U-0
x = Bit is unknown
DSBOR
R/W-0
U-0
(2)
DS39927B-page 105
RELEASE
R/C-0, HS
U-0
bit 8
bit 0

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