ATTINY261-20PU Atmel, ATTINY261-20PU Datasheet
ATTINY261-20PU
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ATTINY261-20PU Summary of contents
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... ATtiny261/461/861 • Speed Grade: – ATtiny261V/461V/861V: 0 – 4 MHz @ 1.8 – 5.5V, 0 – 10 MHz @ 2.7 – 5.5V – ATtiny261/461/861: 0 – 10 MHz @ 2.7 – 5.5V, 0 – 20 MHz @ 4.5 – 5.5V • Industrial Temperature Range • Low Power Consumption – ...
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... Pin Configurations Figure 1-1. Pinout ATtiny261/461/861 and ATtiny261V/461V/861V (MOSI/DI/SDA/OC1A/PCINT8) PB0 (MISO/DO/OC1A/PCINT9) PB1 (SCK/USCK/SCL/OC1B/PCINT10) PB2 (ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4 (ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5 (ADC9/INT0/T0/PCINT14) PB6 (ADC10/RESET/PCINT15) PB7 (OC1B/PCINT11) PB3 (ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4 (ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5 Note: To ensure mechanical stability the center pad underneath the QFN/MLF package should be soldered to ground on the board. ...
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Pin Descriptions 1.1.1 VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 AVCC Analog supply voltage. This is the supply voltage pin for the Analog-to-digital Converter (ADC), the analog comparator, the Brown-Out Detector (BOD), the internal voltage reference and Port A. ...
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... Overview ATtiny261/461/861 are low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface conventional non-volatile memory programmer On-chip boot code running on the AVR core. The ATtiny261/461/861 AVR is supported by a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits. ...
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... Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 3.4 Disclaimer Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. ATtiny261/461/861 6 2588E–AVR–08/10 ...
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CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle ...
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... This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. ATtiny261/461/861 8 2588E–AVR–08/10 ...
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The Status Register is neither automatically stored when entering an interrupt routine, nor restored when returning from an interrupt. This must be handled by software. 4.3.1 SREG – AVR Status Register Bit 0x3F (0x5F) Read/Write Initial Value • Bit 7 ...
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... The three indirect address registers X, Y, and Z are defined as described in Figure 4-3. X-register ATtiny261/461/861 10 below shows the structure of the 32 general purpose working registers in the CPU. AVR CPU General Purpose Working Registers ...
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Y-register Z-register In different addressing modes these address registers function as automatic increment and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and ...
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... Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec- tor in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) ATtiny261/461/861 12 The Parallel Instruction Fetches and Instruction Executions ...
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If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATtiny261/461/861 14 /* set Global Interrupt Enable */ /* enter sleep, waiting for interrupt */ ...
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... Since all AVR instructions are bits wide, the Flash is organized as 1024/2048/4096 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny261/461/861 Program Counter (PC) is 10/11/12 bits wide, thus capable of addressing the 1024/2048/4096 Program memory locations. detailed description on Flash data serial downloading using the SPI pins. ...
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... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter- nal data SRAM in the ATtiny261/461/861 are all accessible through all these addressing modes. The Register File is described in Figure 5-2. ...
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EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in tion, however, lets the user software detect when the next byte can be written. If the ...
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... Set up address and data registers */ EEAR = ucAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } Note: ATtiny261/461/861 18 r16, (0<<EEPM1)|(0<<EEPM0) EECR, r16 ; See “Code Examples” on page 6. “OSCCAL – Oscillator Calibration Register” on ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
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... I/O Memory The I/O space definition of the ATtiny261/461/861 is shown in All ATtiny261/461/861 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed using the LD/LDS/LDD and ST/STS/STD instructions, enabling data transfer between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... Bit 7 – EEAR7: EEPROM Address This is the most significant EEPROM address bit of ATtiny461. In devices with less EEPROM, i.e. ATtiny261, this bit is reserved and will always read zero. The initial value of the EEPROM Address Register (EEAR) is undefined and a proper value must therefore be written before the EEPROM is accessed. • ...
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... The user should poll the EEPE bit before starting the read opera- tion write operation is in progress neither possible to read the EEPROM, nor to change the EEAR Register. 5.5.5 GPIOR2 – General Purpose I/O Register 2 Bit 0x0C (0x2C) Read/Write Initial Value ATtiny261/461/861 22 EEPROM Mode Bits Programming EEPM0 Time Operation 0 3.4 ms ...
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GPIOR1 – General Purpose I/O Register 1 Bit 0x0B (0x2B) Read/Write Initial Value 5.5.7 GPIOR0 – General Purpose I/O Register 0 Bit 0x0A (0x2A) Read/Write Initial Value 2588E–AVR–08/ MSB R/W R/W R/W R ...
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... External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. ATtiny261/461/861 24 presents the principal clock systems and their distribution in ATtiny261/461/861. All of 36. Clock Distribution General I/O ...
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Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. 6.1.4 ADC Clock – clk ADC The ADC is provided with a dedicated ...
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... The internal PLL generates a clock signal with a frequency eight times higher than the source input. The PLL uses the output of the internal 8 MHz oscillator as source and the default setting generates a fast peripheral clock signal of 64 MHz. ATtiny261/461/861 26 Number of Watchdog Oscillator Cycles ...
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The fast peripheral clock, clk prescaled version of the PLL output, clk a detailed illustration on the PLL clock system. Figure 6-3. XTAL1 XTAL2 The internal PLL is enabled when CKSEL fuse bits are programmed to ‘0001’and the PLLE bit ...
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... Notes: When this oscillator is selected, start-up times are determined by SUT fuses as shown in 6-7. Table 6-7. SUT1 ( Note: ATtiny261/461/861 28 Table 6-5. Start-up Times for the PLLCK Start-up Time from Power Down Power-On-Reset (V 14CK + 1K (1024 14CK + 16K (16384 14CK + 1K (1024 14CK + 16K (16384 and “ ...
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... Notes: The Low-frequency Crystal Oscillator provides an internal load capacitance, see each TOSC pin. Table 6-10. ATtiny261/461/861 2588E–AVR–08/10 “OSCCAL – Oscillator Calibration Register” on page “Calibration Byte” on page Start-up Times for the 128 kHz Internal Oscillator Start-up Time from Power- ...
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... The operating mode is selected by fuses CKSEL3:1 as shown in The CKSEL0 Fuse together with the SUT1:0 Fuses select the start-up times as shown in 6-12. Table 6-12. CKSEL0 ATtiny261/461/861 30 Crystal Oscillator Connections C2 C1 Table 6-11. For ceramic resonators, the capacitor values given by Crystal Oscillator Operating Modes ...
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... This default setting ensures that all users can make their desired clock source setting using an In-System or High-voltage Programmer. For low-voltage devices (ATtiny261V/461V/861V) it should be noted that unprogramming the CKDIV8 fuse may result in overclocking. At low voltages (below 2.7V) the devices are rated for maximum 4 MHz operation (see internal oscillator directly to the system clock line will run the device at 8 MHz ...
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... Read/Write Initial Value • Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is ATtiny261/461/861 ...
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CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. 2588E–AVR–08/10 33 ...
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... CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selcted clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 6-13. CLKPS3 ATtiny261/461/861 34 Clock Prescaler Select CLKPS2 CLKPS1 ...
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Table 6-13. CLKPS3 2588E–AVR–08/10 Clock Prescaler Select (Continued) CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 1 Reserved 0 Reserved 1 Reserved 35 ...
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... MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.1 Sleep Modes Figure 6-1 on page 24 ATtiny261/461/861. The figure is helpful in selecting an appropriate sleep mode. shows the different sleep modes and their wake up sources. Table 7-1. Sleep Mode Idle ADC Noise Reduct ...
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Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting ...
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... For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR0, DIDR1). ATtiny261/461/861 38 “AC – Analog Comparator” on page 137 for details on ADC operation. ...
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Refer to able Register 1” on page 162 7.4 Register Description 7.4.1 MCUCR – MCU Control Register The MCU Control Register contains control bits for power management. Bit 0x35 (0x55) Read/Write Initial Value • Bit 5 – SE: Sleep Enable ...
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... USI again, the USI should be re initialized to ensure proper operation. • Bit 0 – PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. Also analog comparator needs this clock. ATtiny261/461/861 40 2588E–AVR–08/10 ...
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System Control and Reset 8.0.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP ...
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... Reset Sources The ATtiny261/461/861 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. ...
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... Figure 8-4. 8.1.3 Brown-out Detection ATtiny261/461/861 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection ...
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... Timer” on page 44 Figure 8-6. 8.2 Internal Voltage Reference ATtiny261/461/861 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The bandgap voltage varies with supply voltage and temperature, as can be seen in 216. ...
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The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down. To prevent unintentional disabling of the Watchdog or unintentional change of time-out ...
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... WDT_off(void) { _WDR(); /* Clear WDRF in MCUSR */ MCUSR = 0x00 /* Write logical one to WDCE and WDE */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; } Note: ATtiny261/461/861 46 r16, (0<<WDRF) MCUSR, r16 r16, WDTCSR See “Code Examples” on page 6. 2588E–AVR–08/10 ...
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... Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny261/461/861 and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...
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... To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure described above. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. Note: ATtiny261/461/861 48 Watchdog Timer Configuration WDIE Watchdog Timer State ...
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Bits 5, 2:0 – WDP3:0: Watchdog Timer Prescaler and 0 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in ...
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... Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny261/461/861. For a general explanation of the AVR interrupt handling, refer to on page 9.1 Interrupt Vectors Interrupt vectors of ATtiny261/461/861 are described in Table 9-1. Vector No the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations ...
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External Interrupts The External Interrupts are triggered by the INT0 or INT1 pin or any of ...
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... Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU ATtiny261/461/861 52 24. ...
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Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall- ing edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. ...
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... If PCINT11:8 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin, and if PCINT15:12 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATtiny261/461/861 ...
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I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the ...
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... Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to ATtiny261/461/861 56 (1) SLEEP ...
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The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin ...
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... In this case, the delay tpd through the synchronizer is one system clock period. Figure 10-4. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK INSTRUCTIONS SYNC LATCH ATtiny261/461/861 58 XXX PINxn r17 Figure 10-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of ...
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Digital Input Enable and Sleep Modes As shown in schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some ...
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... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. ATtiny261/461/861 60 See “Code Examples” on page 6 ...
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Figure 10-5. Alternate Port Functions Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: 2588E–AVR–08/10 (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 ...
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... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATtiny261/461/861 62 summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are generated internally ...
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Alternate Functions of Port A The Port A pins with alternate function are shown in Table 10-3. • Port A, Bit 7 – ADC6/AIN0/PCINT7 • ADC6: Analog to Digital Converter, Channel 6 • AIN0: Analog Comparator Input. Configure the ...
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... ADC0: Analog to Digital Converter, Channel 0. • DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions, so pin must be configure as an input for DI function. • SDA: Two-wire mode Serial Interface Data. • PCINT0: Pin Change Interrupt source 0. ATtiny261/461/861 64 2588E–AVR–08/10 ...
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Table 10-4 shown in Table 10-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 10-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 2588E–AVR–08/10 and Table 10-5 relate the ...
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... When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. ATtiny261/461/861 66 Port B Pins Alternate Functions Port Pin ...
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ADC10: ADC input Channel 10. Note that ADC input channel 10 uses analog power. • PCINT15: Pin Change Interrupt source 15. • Port B, Bit 6 – ADC9/ T0/ INT0/ PCINT14 • ADC9: ADC input Channel 9. Note that ...
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... Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: ATtiny261/461/861 68 and Table 10-8 relate the alternate functions of Port B to the overriding signals Figure 10-5 on page 61. Overriding Signals for Alternate Functions in PB7:PB4 PB7/RESET/ dW/ADC10/ PB6/ADC9/T0/ PCINT15 INT0/PCINT14 (1) RSTDISBL • ...
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Table 10-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: 10.3 Register Description 10.3.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 6 – PUD: Pull-up Disable When this ...
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... Read/Write Initial Value 10.3.6 DDRB – Port B Data Direction Register Bit 0x17 (0x37) Read/Write Initial Value 10.3.7 PINB – Port B Input Pins Address Bit 0x16 (0x36) Read/Write Initial Value ATtiny261/461/861 PINA7 PINA6 PINA5 PINA4 R/W R/W R/W R/W N/A ...
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... The general operation of Timer/Counter0 is described in 8/16-bit mode. A simplified block dia- gram of the 8/16-bit Timer/Counter is shown in including I/O bits and I/O pins, are shown in bold. For actual placement of I/O pins, refer to out ATtiny261/461/861 and ATtiny261V/461V/861V” on page bit locations are listed in the Figure 11-1. 8-/16-bit Timer/Counter Block Diagram 11 ...
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... The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f clock source. See Figure 11-2 ATtiny261/461/861 72 must be followed. Table 11-1 are also used extensively throughout the document. Definitions ...
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Figure 11-2. Prescaler for Timer/Counter0 clk I/O PSR0 T0 Note: The prescaled clock has a frequency of f Table 11-4 on page 85 11.3.1.1 Prescaler Reset The prescaler is free running, i.e. it operates independently of the Clock Select logic ...
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... Signal description (internal signals): count clk top The counter is incremented at each timer clock (clk restarts from BOTTOM. The counting sequence is determined by the setting of the CTC0 bit located in the Timer/Counter Control Register (TCCR0A). For more details about counting sequences, see ATtiny261/461/861 Synchronization < ...
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Clock Select bits (CS02:0). When no clock source is selected (CS02 the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk counter clear or ...
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... OCR0B), and whenever the Timer/Counter equals to the Output Compare Regisers, the comparator signals a match. A match will set the Output Compare Flag at the next timer clock cycle. In 8-bit mode the match can set either the Output Compare Flag OCF0A or ATtiny261/461/861 76 (Figure 11-4 on page 85). The edge detector is also 2588E– ...
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OCF0B, but in 16-bit mode the match can set only the Output Compare Flag OCF0A as there is only one Output Compare Unit. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output ...
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... TCNT0H/L becomes zero. The TOV0 Flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special ATtiny261/461/861 78 Table ...
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Normal mode, a new counter value can be written anytime. The Output Compare Unit can be used to generate interrupts at some given time. 11.7.4 8-bit Input Capture Mode The Timer/Counter0 can also be used ...
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... Input Capture mode the ICR0 register formed by the OCR0A and OCR0B registers must be accessed with the temporary register 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. ATtiny261/461/861 80 OCRnx - 1 OCRnx shows the setting of OCF0A and the clearing of TCNT0 in CTC mode ...
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The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR0A/B registers. Assembly Code Example C Code Example unsigned int ...
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... SREG,r18 ret C Code Example unsigned int TIM0_ReadTCNT0( void ) { } Note: The assembly code example returns the TCNT0H/L value in the r17:r16 register pair. ATtiny261/461/861 82 unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT0 into TCNT0L ...
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The following code examples show how atomic write of the TCNT0H/L register con- tents. Writing any of the OCR0A/B registers can be done by using the same principle. Assembly Code Example TIM0_WriteTCNT0: C Code Example void TIM0_WriteTCNT0( ...
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... These bits are reserved and will always read zero. • Bit 0 – CTC0: Waveform Generation Mode This bit controls the counting sequence of the counter, the source for maximum (TOP) counter value, see Normal mode (counter) and Clear Timer on Compare Match (CTC) mode (see ation” on page ATtiny261/461/861 ...
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TCCR0B – Timer/Counter0 Control Register B Bit 0x33 (0x53) Read/Write Initial Value • Bit 4 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written ...
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... Bit 0x39 (0x59) Read/Write Initial Value • Bit 4 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed ATtiny261/461/861 TCNT0H[7:0] ...
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Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0. • Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is ...
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... TOP value, the ICF0 flag is set when the counter reaches the TOP value. ICF0 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF0 can be cleared by writing a logic one to its bit location. ATtiny261/461/861 88 2588E–AVR–08/10 ...
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Timer/Counter1 12.1 Features • 8/10-Bit Accuracy • Three Independent Output Compare Units • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase and Frequency Correct Pulse Width Modulator (PWM) • Variable PWM Period • High Speed Asynchronous ...
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... ATtiny261V/461V/861V” on page in the “Register Description” on page 12.2.1 Speed The maximum speed of the Timer/Counter1 is 64 MHz. However supply voltage below 2.7 volts is used recommended to use the Low Speed Mode (LSM), because the Timer/Counter1 is not running fast enough on low voltage levels. In the Low Speed Mode the fast peripheral clock is scaled down to 32 MHz ...
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TCCR1A, TCCR1B, TCCR1C, TCCR1D, OCR1A, OCR1B, OCR1C and OCR1D can be read back right after writing the register. The read back values are delayed for the Timer/Counter1 (TCNT1) register, Timer/Counter1 High Byte Register (TC1H) and flags (OCF1A, OCF1B, OCF1D and ...
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... Control Register B” on page The frequency of the fast peripheral clock is 64 MHz or 32 MHz in Low Speed mode (the LSM bit in PLLCSR register is set to one). The Low Speed Mode is recommended to use when the sup- ply voltage below 2.7 volts are used. ATtiny261/461/861 92 Definitions Description ...
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Prescaler Reset Setting the PSR1 bit in TCCR1B register resets the prescaler possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. 12.3.1.2 Prescaler Initialization for Asynchronous Mode To change Timer/Counter1 to the asynchronous ...
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... For the normal mode of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-sym- ATtiny261/461/861 94 Figure 12-5 shows a block diagram of the Output Compare unit. ...
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PWM pulses, thereby making the output glitch-free. See During the time between the write and the update operation, a read from OCR1A, OCR1B, OCR1C or OCR1D will read the contents of the temporary location. This means that the most ...
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... DT1H or DT1L value from DT1 I/O register, depending on the edge of the Waveform Output (OCW1x) when the dead time insertion is started. The Output Compare Output are delayed by one timer clock cycle at minimum from the Waveform Output when the Dead Time is adjusted to ATtiny261/461/861 96 Figure 12-7 below ...
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The outputs OC1x and OC1x are inverted, if the PWM Inversion Mode bit PWM1X is set. This will also cause both outputs to be high during the dead time. The length of the counting period is user adjustable by ...
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... Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x and OC1x pins (DDR_OC1x and DDR_OC1x) must be set as output before the OC1x and OC1x values are visible on the pin. The port override function is independent of the Output Compare mode. ATtiny261/461/861 98 WGM11 OC1OE1:0 ...
Page 99
The design of the Output Compare Pin Configuration logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. For Output Compare Pin Configurations refer to ...
Page 100
... Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the Phase and Frequency Correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and ATtiny261/461/861 100 /4 when OCR1C is set to zero. The waveform frequency is defined by the following ...
Page 101
DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. The timing diagram for the fast PWM mode is shown in mented until the counter value matches the TOP value. The counter ...
Page 102
... The TCNT1 value will be equal to TOP for one timer clock cycle. The diagram includes the Waveform Output (OCW1x) in non-inverted and inverted Compare Output Mode. The small horizontal line marks on the TCNT1 slopes represent Compare Matches between OCR1x and TCNT1. ATtiny261/461/861 102 Table 12-3. ...
Page 103
Figure 12-13. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCWnx (COMnx = 2) OCWnx (COMnx = 3) Period The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to ...
Page 104
... TOP value. The counter is then cleared at the following timer clock cycle. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The tim- ing diagram includes Output Compare pins OC1A and OC1A, and the corresponding Output Compare Override Enable bits (OC1OE1:OC1OE0). ATtiny261/461/861 104 Table 12-4. ...
Page 105
Figure 12-14. PWM6 Mode, Single-slope Operation, Timing Diagram TCNT1 OCW1A OC1OE0 OC1A Pin OC1OE1 OC1A Pin OC1OE2 OC1B Pin OC1OE3 OC1B Pin OC1OE4 OC1D Pin OC1OE5 OC1D Pin The general I/O port function is overridden by the Output Compare value ...
Page 106
... Phase and Frequency Correct PWM Mode. Figure 12-16. Timer/Counter Timing Diagram, with Prescaler (f clk PCK clk Tn (clk /8) PCK TCNTn TOVn Figure 12-17 ATtiny261/461/861 106 Configuration of Output Compare Pins OC1D and OC1D in PWM6 Mode COM1D0 OC1D Pin (PB4) 0 Disconnected OC1OE4 1 OC1A • OC1OE4 0 OC1A • ...
Page 107
Figure 12-17. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk PCK clk Tn (clk /8) PCK TCNTn OCRnx OCFnx Figure 12-18 Figure 12-18. Timer/Counter Timing Diagram, with Prescaler (f clk PCK clk Tn (clk /8) PCK TCNTn TOVn ...
Page 108
... If writing to more than one 10-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. ATtiny261/461/861 108 Figure 11-3 on page 74). The edge 2588E– ...
Page 109
Code Examples The following code examples show how to access the 10-bit timer registers assuming that no interrupts updates the TC1H register. The same principle can be used directly for accessing the OCR1A/B/C/D registers. Assembly Code Example C Code ...
Page 110
... SREG,r18 ret C Code Example unsigned int TIM1_ReadTCNT1( void ) { } Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. ATtiny261/461/861 110 unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1 ...
Page 111
The following code examples show how atomic write of the TCNT1 register contents. Writing any of the OCR1A/B/C/D registers can be done by using the same principle. Assembly Code Example TIM1_WriteTCNT1: C Code Example void TIM1_WriteTCNT1( unsigned ...
Page 112
... The function of the COM1A1:0 bits depends on the PWM1A, WGM10 and WGM11 bit settings. Table 12-8 (non-PWM). Table 12-8. COM1A1 Table 12-9 are set to fast PWM mode. Table 12-9. COM1A1 ATtiny261/461/861 112 COM1A1 COM1A0 COM1B1 COM1B0 R/W R/W R/W R ...
Page 113
Table 12-10 are set to Phase and Frequency Correct PWM Mode. Table 12-10. Compare Output Mode, Phase and Frequency Correct PWM Mode COM1A1 Table 12-11 are set to single-slope PWM6 Mode. In the PWM6 Mode the ...
Page 114
... COM1B1 Bits COM1B1 and COM1B0 are shadowed in TCCR1C. Writing to bits COM1B1 and COM1B0 will also change bits COM1B1S and COM1B0S in TCCR1C. Similary, changes written to bits ATtiny261/461/861 114 OCW1B Behaviour Normal port operation. Toggle on Compare Match. Clear on Compare Match. Set on Compare Match. ...
Page 115
COM1B1S and COM1B0S in TCCR1C will show here. See Register C” on page • Bit 3 – FOC1A: Force Output Compare Match 1A The FOC1A bit is only active when the PWM1A bit specify a non-PWM mode. Writing a logical ...
Page 116
... Bits 3:0 – CS13, CS12, CS11, CS10: Clock Select Bits and 0 The Clock Select bits and 0 define the prescaling source of Timer/Counter1. Table 12-17. Timer/Counter1 Prescaler Select CS13 The Stop condition provides a Timer Enable/Disable function. ATtiny261/461/861 116 Table 12-16. DTPS10 Prescaler divides the T/C1 clock (no division CS12 CS11 CS10 Asynchronous Clocking Mode ...
Page 117
TCCR1C – Timer/Counter1 Control Register C Bit 0x27 (0x47) Read/Write Initial value • Bits 7,6 – COM1A1S, COM1A0S: Comparator A Output Mode, Shadow Bits 1 and 0 These are shadow bits of COM1A1 and COM1A0 in TCCR1A. Writing to ...
Page 118
... This bit selects which edge on the Fault Protection pin (INT0) is used to trigger a fault event. When the FPES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the FPES1 bit is written to one, a rising (positive) edge will trigger the fault. ATtiny261/461/861 118 shows the COM1D1:0 bit functionality when the PWM1D and WGM11:10 bits are OCW1D Behaviour Normal port operation ...
Page 119
Bit 3 – FPAC1: Fault Protection Analog Comparator Enable When written logic one, this bit enables the Fault Protection function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to ...
Page 120
... PLL lock-in sequence when PLL frequency overshoots and undershoots, before reaching steady state. The steady state is obtained within 100 µs. After PLL lock- recommended to check the PLOCK bit before enabling PCK for Timer/Counter1. ATtiny261/461/861 120 Output Compare Output ...
Page 121
TCNT1 – Timer/Counter1 Bit 0x2E (0x4E) Read/Write Initial value This 8-bit register contains the value of Timer/Counter1. The Timer/Counter1 is realized as a 10-bit up/down counter with read and write access. Due to synchronization of the CPU, Timer/Counter1 data ...
Page 122
... Timer/Counter1 counts to the OCR1D value. A software write that sets TCNT1 and OCR1D to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1D after a synchronization delay follow- ing the compare event. ATtiny261/461/861 122 7 6 ...
Page 123
Note that, if 10-bit accuracy is used special procedures must be followed when accessing the internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are described in section 12.12.13 TIMSK – Timer/Counter1 Interrupt Mask Register Bit ...
Page 124
... Bits 3:0 – DT1L3:DT1L0: Dead Time Value for OC1x Output The dead time value for the OC1x output. The dead time delay is set as a number of the pres- caled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. ATtiny261/461/861 124 7 6 ...
Page 125
... A transparent latch between the output of the data register and the output pin delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin, regardless of the configuration. 2588E–AVR–08/10 “Pinout ATtiny261/461/861 and ATtiny261V/461V/861V” on page 3 2 USIDR ...
Page 126
... The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. ATtiny261/461/861 126 Bit7 Bit6 ...
Page 127
Figure 13-3. Three-wire Mode, Timing Diagram CYCLE USCK USCK DO DI The Three-wire mode timing is shown in Figure 13-3. At the top of the figure is a USCK cycle ref- erence. One bit is shifted into the USI Data ...
Page 128
... The fourth and fifth instructions set three-wire mode, positive edge clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. The following code demonstrates how to use the USI as an SPI master with maximum speed ( SCK CK SPITransfer_Fast: ret ATtiny261/461/861 128 sts USICR,r16 lds r16, USISR sbrs r16, USIOIF rjmp ...
Page 129
SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ... SlaveSPITransfer: SlaveSPITransfer_loop: The code is size optimized using only eight instructions (+ ret). The code example assumes that the ...
Page 130
... In addition, the start detector will hold the SCL line low after the master has forced a negative edge on this line (B). This allows the slave to wake up from sleep or complete other tasks before setting up the USI Data Register to receive the address. This is done by clearing the start condition flag and resetting the counter. ATtiny261/461/861 130 Bit7 Bit6 ...
Page 131
The master set the first bit to be transferred and releases the SCL line (C). The slave samples the data and shifts it into the USI Data Register at the positive edge of the SCL clock. 4. After eight ...
Page 132
... The output will be changed immediately when a new MSB is written as long as the latch is open. Note that the Data Direction Register bit corresponding to the output pin must be set to one in order to enable data output from the USI Data Register. ATtiny261/461/861 132 7 6 ...
Page 133
USIBR – USI Buffer Register Bit 0x10 (0x30) Read/Write Initial Value The content of the Serial Register is loaded to the USI Buffer Register when the trasfer is com- pleted, and instead of accessing the USI Data Register (the ...
Page 134
... Basically, only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and USI Data Register can therefore be clocked externally, and data input sampled, even when outputs are disabled. Table 13-1. USIWM1 0 0 ATtiny261/461/861 134 USISIE USIOIE ...
Page 135
Table 13-1. USIWM1 1 1 Note: • Bits 3:2 – USICS1:0: Clock Source Select These bits set the clock source for the USI Data Registerr and counter. The data output latch ensures that the output is changed at the opposite ...
Page 136
... Setting this bit to one changes the USI pin position. As default pins PB2:PB0 are used for the USI pin functions, but when writing this bit to one the USIPOS bit is set the USI pin functions are on pins PA2:PA0. ATtiny261/461/861 136 Relations between the USICS1:0 and USICLK Setting (Continued) ...
Page 137
AC – Analog Comparator The analog comparator compares the input values on the selectable positive pin (AIN0, AIN1 or AIN2) and selectable negative pin (AIN0, AIN1 or AIN2). When the voltage on the positive pin is higher than the ...
Page 138
... Table 14-1. ACME ATtiny261/461/861 138 Analog Comparator Multiplexed Input (Continued) ADEN MUX5:0 ACM2:0 x xxxxxx 100 x xxxxxx 101,110,111 1 xxxxxx 000 0 000000 000 0 000000 01x 0 000000 1xx 0 000001 000 0 000001 01x 0 000001 1xx 0 000010 000 0 000010 01x 0 000010 1xx 0 000011 000 0 000011 01x ...
Page 139
Register Description 14.2.1 ACSRA – Analog Comparator Control and Status Register A Bit 0x08 (0x28) Read/Write Initial Value • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the analog comparator ...
Page 140
... Bit 3 – AREFD: AREF Digital Input Disable When this bit is written logic one, the digital input buffer on the AREF pin is disabled. The corre- sponding PIN register bit will always read as zero when this bit is set. When an analog signal is ATtiny261/461/861 140 Table 14-2 ...
Page 141
AREF pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 14.2.4 DIDR1 – Digital Input Disable Register 1 Bit ...
Page 142
... Input Polarity Reversal Mode 15.2 Overview The ATtiny261/461/861 features a 10-bit successive approximation ADC. The ADC is connected to a 11-channel Analog Multiplexer which allows 16 differential voltage input combinations and 11 single-ended voltage inputs constructed from the pins PA7:PA0 or PB7:PB4. The differential input is equipped with a programmable gain stage, providing amplification steps of 1x, 8x, 20x or 32x on the differential input voltage before the A/D conversion ...
Page 143
Figure 15-1. Analog to Digital Converter Block Schematic 8-BIT DATA BUS VCC AREF INTERNAL 2.56/1.1V AGND ADC10 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 15.3 Operation The ADC converts an analog input voltage to a 10-bit digital ...
Page 144
... When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting con- versions at fixed intervals. If the trigger signal still is set when the conversion completes, a new ATtiny261/461/861 144 Table ...
Page 145
If another positive edge occurs on the trigger signal during con- version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global ...
Page 146
... ADC Data Registers, and ADIF is set. In Sin- gle Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. ATtiny261/461/861 146 ADEN Reset ...
Page 147
Figure 15-5. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL When Auto Triggering is used, the prescaler is reset when the trigger event occurs. See 15-6. This assures a fixed delay from the trigger event ...
Page 148
... If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: ATtiny261/461/861 148 One Conversion 11 ...
Page 149
When ADATE or ADEN is cleared. • During conversion, minimum one ADC clock cycle after the trigger event. • After a conversion, before the Interrupt Flag used as trigger source is cleared. When updating ADMUX in one of these ...
Page 150
... If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress. • Place bypass capacitors as close to V Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as described in is above 1 MHz, or when the ADC is used for reading the internal temperature sensor, as ATtiny261/461/861 150 I IH ADCn ...
Page 151
ADC Noise Reduction Mode 15.10 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V (LSBs). The lowest code is read as 0, and the ...
Page 152
... Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 15-11. Integral Non-linearity (INL) Output Code ATtiny261/461/861 152 Gain Error Ideal ADC ...
Page 153
Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 15-12. Differential Non-linearity (DNL) • Quantization Error: Due to the ...
Page 154
... When the temperature sensor is enabled, the ADC converter can be used in sin- gle conversion mode to measure the voltage over the temperature sensor. The measured voltage has a linear relationship to the temperature as described in The sensitivity is approximately 1 LSB / ibration. Typically, the measurement accuracy after a single temperature calibration is ± ATtiny261/461/861 154 ( V POS ...
Page 155
Better accuracies are achieved by using two temperature points for calibration. Table 15-2. Temperature ADC The values described in temperature sensor output voltage varies from one chip to another capable of achieving more ...
Page 156
... These bits and the MUX5 bit from the ADC Control and Status Register B (ADCSRB) select which combination of analog inputs are connected to the ADC. In case of differential input, gain selection is also made with these bits. Selecting the same pin as both inputs to the differential ATtiny261/461/861 156 160. ...
Page 157
Selecting the single-ended channel ADC11 enables the temperature sensor. Refer to Table 15-4. MUX5:0 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 ...
Page 158
... Note: ATtiny261/461/861 158 Input Channel Selections (Continued) Single-Ended Input Positive ADC0(PA0) ADC0(PA0) N/A ADC1(PA1 ADC1(PA1) ADC1(PA1) ADC1(PA1) N/A ADC2(PA2 ADC2(PA2) ADC2(PA2) ADC2(PA2) N/A ...
Page 159
If these bits are changed during a conversion, the change will not go into effect until this conver- sion is complete (ADIF in ADCSRA is set). 15.13.2 ADCSRA – ADC Control and Status Register A Bit 0x06 (0x26) Read/Write Initial ...
Page 160
... The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in page 153. ATtiny261/461/861 160 ADC Prescaler Selections (Continued) ADPS1 ...
Page 161
... Gain Select bit is written to one. • Bit 5 – Res: Reserved Bit This bit is a reserv ed bit in the ATtiny261/461/861 and will always read as zero. • Bit 4 – REFS2: Reference Selection Bit These bit selects either the voltage reference of 1 2.56 V for the ADC, as shown in 15-3 ...
Page 162
... The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC10:7 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. ATtiny261/461/861 162 ADC Auto Trigger Source Selections ...
Page 163
On-chip Debug System 16.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog , except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or ...
Page 164
... Read/Write Initial Value The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. ATtiny261/461/861 164 will not work. CC ® ...
Page 165
Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associ- ated protocol to read code and write (program) that code ...
Page 166
... The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. Figure 17-1. Addressing the Flash During SPM Z - REGISTER Note: ATtiny261/461/861 166 The CPU is halted during the Page Write operation ...
Page 167
EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation recommended ...
Page 168
... Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses. gramming time for Flash accesses from the CPU. Table 17-1. Flash write (Page Erase, Page Write, and write Lock bits by SPM) Note: ATtiny261/461/861 168 FHB7 FHB6 FHB5 Table 18-4 on page 171 for detailed description and mapping of the Fuse High Byte ...
Page 169
Register Description 17.9.1 SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to con- trol the Program memory operations. Bit 0x37 (0x57) Read/Write Initial Value • ...
Page 170
... This section describes the different methods for programming ATtiny261/461/861 memories. 18.1 Program And Data Memory Lock Bits The ATtiny261/461/861 provides two lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in erased to “1” with the Chip Erase command. ...
Page 171
... Fuse Bytes The ATtiny261/461/861 have three fuse bytes. briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 18-3. Fuse High Byte ...
Page 172
... All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and High-voltage Programming mode, also when the device is locked. The three bytes reside in a separate address space. The ATtiny261/461/861signature bytes are given in Table 18-6. ...
Page 173
... Calibration Byte Signature area of the ATtiny261/461/861 has one byte of calibration data for the internal RC Oscillator. This byte resides in the high byte of address 0x000. During reset, this byte is auto- matically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator. ...
Page 174
... High:> 2 CPU clock cycles for f 18.6.1 Serial Programming Algorithm When writing serial data to the ATtiny261/461/861, data is clocked on the rising edge of SCK. When reading, data is clocked on the falling edge of SCK. See timing details. To program and verify the ATtiny261/461/861 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in 1 ...
Page 175
Flash write operation completes can result in incorrect programming The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location ...
Page 176
... Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use a word address. This address may be random within the page range. 7. See http://www.atmel.com/avr for Application Notes regarding programming and programmers. ATtiny261/461/861 176 Instruction Format ...
Page 177
Figure 18-2. Serial Programming Instruction example Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Adr Adr MSB Bit the LSB in RDY/BSY ...
Page 178
... Figure 18-3. Parallel Programming. Table 18-12. Pin Name Mapping Signal Name in Programming Mode XA1/BS2 PAGEL/BS1 RDY/BSY DATA I/O ATtiny261/461/861 178 WR PB0 XA0 PB1 XA1/BS2 PB2 PAGEL/BS1 PB3 XTAL1/PB4 OE PB5 RDY/BSY PB6 +12 V RESET GND Pin Name I/O Function WR PB0 I Write Pulse (Active low). ...
Page 179
Table 18-13. Pin Values Used to Enter Programming Mode The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 18-14. XA1 and XA0 Coding XA1 0 0 ...
Page 180
... Keep BS1 at “0”. This selects low address. c. Set DATA = Address low byte (0x00 - 0xFF). d. Give XTAL1 a positive pulse. This loads the address low byte. ATtiny261/461/861 180 Wait until RDY/BSY goes high before loading a new command. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. ...
Page 181
Load Data Low Byte: a. Set XA1, XA0 to “01”. This enables data loading. b. Set DATA = Data low byte (0x00 - 0xFF). c. Give XTAL1 a positive pulse. This loads the data byte. 4. Load Data High ...
Page 182
... XTAL1 WR RDY / BSY RESET +12V OE 18.7.6 Programming the EEPROM The EEPROM is organized in pages, see EEPROM, the program data is latched into a page buffer. This allows one page of data to be ATtiny261/461/861 182 PCMSB PAGEMSB PROGRAM PCPAGE COUNTER PAGE ADDRESS WITHIN THE FLASH PAGE ...
Page 183
The programming algorithm for the EEPROM data memory is as follows (refer to Data loading Load Command “0001 0001” Load Address High Byte (0x00 - 0xFF Load Address Low Byte (0x00 - ...
Page 184
... Set BS1 to “0” and BS2 to “1”. This selects extended data byte Give WR a negative pulse and wait for RDY/BSY to go high Set BS2 to “0”. This selects low data byte. ATtiny261/461/861 184 for details on Command and Address loading): ...
Page 185
Figure 18-7. Programming the FUSES Waveforms DATA XA1/BS2 XA0 PAGEL/BS1 XTAL1 WR RDY/BSY RESET +12V OE 18.7.12 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to page 180 1. A: Load Command “0010 ...
Page 186
... The algorithm for reading the Calibration byte is as follows (refer to page 180 1. A: Load Command “0000 1000” Load Address Low Byte, 0x00. 3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA. 4. Set OE to “1”. ATtiny261/461/861 186 0 1 BS2 0 ...
Page 187
Electrical Characteristics 19.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0. Voltage on RESET with respect to Ground......-0.5V to +13.0V ...
Page 188
... CC CC exceeds the test conditions 5V 3V) under steady state CC CC exceeds the test condition 20-23, Figure 20-24, Figure 20-25, and 37. Power Reduction . As shown in CC relationship is linear between 1.8V < V (ATtiny261V/461V/861V) 2.7V Units µA µ Figure 20-26 Figure 19-1 and < 2.7V CC 5.5V ...
Page 189
... MHz Calibration Fixed frequency User within: Calibration 7.3 - 8.1 MHz Notes: 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage). 2. Voltage range for ATtiny261V/461V/861V. 3. Voltage range for ATtiny261/461/861. Figure 19-3. External Clock Drive Waveforms V IH1 V IL1 2588E–AVR–08/10 (ATtiny261/461/861) ...
Page 190
... BOD Note: 19.5.1 Power-On Reset Table 19-5. Symbol V POR V POA SR ON Notes: ATtiny261/461/861 190 V = 1.8 - 5.5V CC Min. 0 250 100 100 Reset, Brown-out, and Internal Voltage Characteristics Parameter (1) RESET Pin Threshold Voltage Minimum pulse width on (1) RESET Pin (1) Brown-out Detector Hysteresis Min Pulse Width on ...
Page 191
Brown-Out Detection Table 19-6. Note: 2588E–AVR–08/10 (1) BODLEVEL Fuse Coding BODLEVEL[2:0] Fuses Min V 111 110 101 100 0XX 1. V may be below nominal minimum operating voltage for some devices. For devices where BOT this is the case, ...
Page 192
... Internal 1.1V Reference V INT Internal 2.56V Reference R Reference Input Resistance REF R Analog Input Resistance AIN ADC Conversion Output Note: 1. Values are guidelines, only must be below V . DIFF REF ATtiny261/461/861 192 Condition 4V, REF CC ADC clock = 200 kHz 4V, REF CC ADC clock = 1 MHz 4V, ...
Page 193
... SAMPLE MOSI t OVSH SCK t SHSL MISO Serial Programming Characteristics, T (Unless Otherwise Noted) Parameter Oscillator Frequency (ATtiny261V/461V/861V) Oscillator Period (ATtiny261V/461V/861V) Oscillator Frequency (ATtiny261/461/861 4.5 - 5.5V) CC Oscillator Period (ATtiny261/461/861 4.5 - 5.5V) CC SCK Pulse Width High SCK Pulse Width Low MOSI Setup to SCK High ...
Page 194
... XA0, XA1/BS2, PAGEL/BS1) WR RDY/BSY Figure 19-7. Parallel Programming Timing, Loading Sequence with Timing Requirements LOAD ADDRESS (LOW BYTE) XTAL1 PAGEL/BS1 DATA ADDR0 (Low Byte) XA0 XA1/BS2 Note: The timing requirements shown in ATtiny261/461/861 194 t XLWL t XHXL t t DVXH XLDX t t BVPH PLBX ...
Page 195
Figure 19-8. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements LOAD ADDRESS (LOW BYTE) XTAL1 PAGEL/BS1 OE DATA ADDR0 (Low Byte) XA0 XA1/BS2 Note: The timing requirements shown in Table 19-9. Symbol ...
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... Table 19-9. Symbol t BVDV t OLDV t OHDZ Notes: ATtiny261/461/861 196 Parallel Programming Characteristics, V Parameter BS1 Valid to DATA valid OE Low to DATA Valid OE High to DATA Tri-stated valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits WLRH commands valid for the Chip Erase command. ...
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Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indica- tions of how the part will ...
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... Active Supply Current Figure 20-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 1,2 0,8 0,6 0,4 0,2 ATtiny261/461/861 198 Additional Current Consumption (percentage) in Active and Idle mode. Additional Current consumption compared to Active with external clock (see Figure 20-1 on page 198 ...
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Figure 20-2. Active Supply Current vs. Frequency ( MHz) Figure 20-3. Active Supply Current vs. V 2588E–AVR–08/10 ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 ...
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... Figure 20-4. Active Supply Current vs. V 1,6 1,4 1,2 0,8 0,6 0,4 0,2 Figure 20-5. Active Supply Current vs. V 0,3 0,25 0,2 0,15 0,1 0,05 ATtiny261/461/861 200 CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 1 0 1 ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 128 kHz 0 ...