PIC24F16KA102-I/ML Microchip Technology, PIC24F16KA102-I/ML Datasheet
PIC24F16KA102-I/ML
Specifications of PIC24F16KA102-I/ML
Available stocks
Related parts for PIC24F16KA102-I/ML
PIC24F16KA102-I/ML Summary of contents
Page 1
... XLP™ Technology © 2009 Microchip Technology Inc. PIC24F16KA102 Family 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers Preliminary Data Sheet DS39927B ...
Page 2
... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... Microchip Technology Inc. PIC24F16KA102 FAMILY Analog Features: • 10-Bit 9-Channel Analog-to-Digital Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Analog Comparators with Programmable Input/ Output Configuration • Charge Time Measurement Unit (CTMU): ...
Page 4
... PIC24F16KA102 FAMILY Pin Diagrams (2) 20-Pin PDIP, SSOP, SOIC MCLR PGC2/AN0/V REF PGD2/AN1/V REF PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 PGC1/AN3/C1INC/C2INA/U2RX/U2BCLK/CN5/RB1 U1RX/U1BCLK/CN6/RB2 OSCI/CLKI/AN4/C1INB/C2IND/CN30/RA2 OSCO/CLKO/AN5/C1INA/C2INC/CN29/RA3 PGD3/SOSCI/U2RTS/CN1/RB4 PGC3/SOSCO/T1CK/U2CTS/CN0/RA4 28-Pin SPDIP, SSOP, SOIC MCLR/V AN0/V REF AN1/V PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 PGC1/AN3/C1INC/C2INA/U2RX/U2BCLK/CN5/RB1 AN4/C1INB/C2IND/U1RX/U1BCLK/CN6/RB2 AN5/C1INA/C2INC/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 SOSCI/U2RTS/CN1/RB4 SOSCO/T1CK/U2CTS/CN0/RA4 PGD3/SDA1 Note 1: Alternative multiplexing for SDA1 and SCL1 when the I2CSEL Configuration bit is set. ...
Page 5
... Pin Diagrams (Continued) (1,2) 20-Pin QFN PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 PGC1/AN3/C1INC/C2INA/U2RX/U2BCLK/CN5/RB1 U1RX/U1BCLK/CN6/RB2 OSCI/CLKI/AN4/C1INB/C2IND/CN30/RA2 OSCO/CLKO/AN5/C1INA/C2INC/CN29/RA3 Note 1: The bottom pad of the QFN package should be connected to Vss. 2: All device pins have a maximum voltage of 3.6V and are not 5V tolerant. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY REFO/SS1/T2CK/T3CK/CN11/RB15 1 15 AN10/CV /RTCC/SDI1/OCFA/C1OUT/INT1/CN12/RB14 ...
Page 6
... PIC24F16KA102 FAMILY Pin Diagrams (Continued) (2,3) 28-Pin QFN PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 PGC1/AN3/C1INC/C2INA/U2RX/U2BCLK/CN5/RB1 AN4/C1INB/C2IND/U1RX/U1BCLK/CN6/RB2 AN5/C1INA/C2INC/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 Note 1: Alternative multiplexing for SDA1 and SCL1 when the I2CSEL Configuration bit is set. 2: The bottom pad of the QFN package should be connected to Vss. 3: All device pins have a maximum voltage of 3.6V and are not 5V tolerant. ...
Page 7
... Electrical Characteristics .......................................................................................................................................................... 211 30.0 Packaging Information.............................................................................................................................................................. 231 Appendix A: Revision History............................................................................................................................................................. 243 Index .................................................................................................................................................................................................. 245 The Microchip Web Site ..................................................................................................................................................................... 249 Customer Change Notification Service .............................................................................................................................................. 249 Customer Support .............................................................................................................................................................................. 249 Reader Response .............................................................................................................................................................................. 250 Product Identification System ............................................................................................................................................................ 251 © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Preliminary DS39927B-page 5 ...
Page 8
... PIC24F16KA102 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
Page 9
... Operational performance MIPS © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24F16KA102 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • On-the-Fly Clock Switching: The device clock ...
Page 10
... DS39927B-page 8 1.3 Details on Individual Family Members Devices in the PIC24F16KA102 family are available in 20-pin and 28-pin packages. The general block diagram for all devices is displayed in Figure 1-1. The devices are different from each other in two ways: 1. Flash ...
Page 11
... TABLE 1-1: DEVICE FEATURES FOR THE PIC24F16KA102 FAMILY Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Data EEPROM Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) ...
Page 12
... PIC24F16KA102 FAMILY FIGURE 1-1: PIC24F16KA102 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller PSV and Table Data Access Control Block 23 23 Address Latch Program Memory Data EEPROM Data Latch Address Bus Instruction Decode and Control Power-up Timing OSCO/CLKO Generation Timer OSCI/CLKI Oscillator Start-up Timer ...
Page 13
... TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS Pin Number 20-Pin 28-Pin Function PDIP/SSOP/ 20-Pin SPDIP/ SOIC QFN SSOP/SOIC AN0 AN1 AN2 AN3 AN4 AN5 AN10 AN11 AN12 U1BCLK U2BCLK C1INA C1INB C1INC C1IND C1OUT C2INA C2INB C2INC C2IND C2OUT CLKI CLKO Schmitt Trigger input buffer, ANA = Analog level input/output, I Legend: Alternative multiplexing when the I2C1SEL Configuration bit is cleared ...
Page 14
... PIC24F16KA102 FAMILY TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin 28-Pin Function PDIP/SSOP/ 20-Pin SPDIP/ SOIC QFN SSOP/SOIC CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 — — 7 CN8 CN9 — — 19 CN11 CN12 CN13 CN14 CN15 — — ...
Page 15
... TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin 28-Pin Function PDIP/SSOP/ 20-Pin SPDIP/ SOIC QFN SSOP/SOIC PGC1 PGD1 PGC2 PGD2 PGC3 PGD3 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 — — 19 RB0 RB1 RB2 RB3 — — 7 RB4 ...
Page 16
... PIC24F16KA102 FAMILY TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin 28-Pin Function PDIP/SSOP/ 20-Pin SPDIP/ SOIC QFN SSOP/SOIC T1CK T2CK T3CK U1CTS U1RTS U1RX U1TX 13 REF REF Schmitt Trigger input buffer, ANA = Analog level input/output, I Legend: Alternative multiplexing when the I2C1SEL Configuration bit is cleared. ...
Page 17
... GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC24F16KA102 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All V and V ...
Page 18
... PIC24F16KA102 FAMILY 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 μF (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher ...
Page 19
... V and DDCORE © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible ...
Page 20
... PIC24F16KA102 FAMILY 2.6 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency Primary Oscillator and a low-frequency Secondary Oscillator Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins, with no more than 0 ...
Page 21
... Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
Page 22
... PIC24F16KA102 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCH 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data EEPROM Address Bus Data Latch 24 Instruction Decode and Control Control Signals ...
Page 23
... W0 (WREG) Divider Working Registers W1 W2 Multiplier Registers W10 W11 W12 W13 W14 W15 22 Registers or bits shadowed for PUSH.S and POP.S instructions. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 15 0 Frame Pointer 0 Stack Pointer 0 SPLIM TBLPAG 7 0 PSVPAG 15 0 RCOUNT SRH SRL ...
Page 24
... PIC24F16KA102 FAMILY 3.2 CPU Control Registers REGISTER 3-1: SR: ALU STATUS REGISTER U-0 U-0 — — bit 15 (1) (1) R/W-0, HSC R/W-0, HSC R/W-0, HSC (2) (2) IPL2 IPL1 IPL0 bit 7 HSC = Hardware Settable/Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘ ...
Page 25
... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — — ...
Page 26
... PIC24F16KA102 FAMILY 3.3.2 DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends and the remainder in W1 ...
Page 27
... Program Counter (PC) during program execution, or from a table operation or data space remapping, as described in Section 4.3 “Interfacing Program and Data Memory Spaces”. FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24F16KA102 FAMILY DEVICES PIC24F08KA102 GOTO Instruction Reset Address Interrupt Vector Table Reserved ...
Page 28
... Program Memory ‘Phantom’ Byte (read as ‘0’) DS39927B-page 26 4.1.3 DATA EEPROM In the PIC24F16KA102 family, the data EEPROM is mapped to the top of the user program memory space, organized in starting at address 7FFE00 and expanding up to address 7FFFFF. The data EEPROM is organized as 16-bit wide memory and 256 words deep ...
Page 29
... Memory Using Program Space Visibility”). PIC24F16KA102 family devices implement a total of 768 words of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24F16KA102 FAMILY DEVICES MSB Address 0001h 07FFh 0801h ...
Page 30
... PIC24F16KA102 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations consequence of byte accessibility, all EA calculations are internally scaled to step through word-aligned memory. For example, the core recog- ...
Page 31
TABLE 4-3: CPU CORE REGISTERS MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...
Page 32
TABLE 4-4: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name (1) CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 — CN30IE CN29IE — CNPU1 0068 CN15PUE (1) CN14PUE CN13PUE CN12PUE CNPU2 006A — CN30PUE ...
Page 33
TABLE 4-6: TIMER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — ...
Page 34
TABLE 4-9: I C™ REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — ...
Page 35
TABLE 4-12: PORTA REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — ODCA 02C6 — — — — ...
Page 36
TABLE 4-15: ADC REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...
Page 37
TABLE 4-17: REAL-TIME CLOCK AND CALENDAR REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name ALRMVAL 0620 ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 RTCVAL 0624 RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC — = unimplemented, read ...
Page 38
TABLE 4-20: CLOCK CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR SBOREN — OSCCON 0742 — COSC2 COSC1 COSC0 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 OSCTUN 0748 — — — ...
Page 39
... Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 4.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...
Page 40
... Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of Note 1: the address is PSVPAG<0>. PSVPAG can have only two values (‘00’ to access program memory and FF to access data EEPROM the PIC24F16KA102 family. FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION (1) Program Counter ...
Page 41
... Note that the data will always be ‘0’ when the upper ‘phantom’ byte is selected (byte select = 1). © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 “ ...
Page 42
... PIC24F16KA102 FAMILY FIGURE 4-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG 4.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into an 8K word page (in PIC24F08KA1XX devices) and a 16K word page (in PIC24F16KA1XX devices) of the program space. This provides ...
Page 43
... Program Space PSVPAG The data in the page designated by PSVPAG is mapped into the upper half of the data memory space.... © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Data Space 0 000000h 002BFEh PSV Area 800000h Preliminary 0000h Data EA<14:0> 8000h ...while the lower 15 bits ...
Page 44
... PIC24F16KA102 FAMILY NOTES: DS39927B-page 42 Preliminary © 2009 Microchip Technology Inc. ...
Page 45
... Run-Time Self Programming (RTSP) • Enhanced In-Circuit Serial Programming (Enhanced ICSP) ICSP allows a PIC24F16KA102 device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (which are named PGCx and ...
Page 46
... PIC24F16KA102 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 32 instructions or 96 bytes. RTSP allows the user to erase blocks of 1 row, 2 rows and 4 rows (32, 64 and 128 instructions time and to program one row at a time also possible to program single words ...
Page 47
... Note 1: Available in ICSP™ mode only. Refer to device programming specification. 2: The address in the Table Pointer decides which rows will be erased. 3: This bit is used only while accessing data EEPROM. 4: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 U-0 U-0 (4) PGMONLY — — ...
Page 48
... PIC24F16KA102 FAMILY 5.5.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The user can program one row of Flash program memory at a time by erasing the programmable row. The general process is: 1. Read a row of program (32 instructions) and store in data RAM. 2. Update the program data in RAM with the desired new data ...
Page 49
... NVMCON = 0x4058; asm("DISI #5"); __builtin_write_NVM(); © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON // Block all interrupts for next 5 instructions ...
Page 50
... PIC24F16KA102 FAMILY EXAMPLE 5-3: LOADING THE WRITE BUFFERS – ASSEMBLY LANGUAGE CODE ; Set up NVMCON for row programming operations MOV #0x4004, W0 MOV W0, NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 MOV ...
Page 51
... MOV W0, NVMKEY MOV #0xAA, W0 MOV W0, NVMKEY BSET NVMCON, #WR © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY ; Block all interrupts for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; 2 NOPs required after setting Wait for the sequence to be completed ...
Page 52
... PIC24F16KA102 FAMILY NOTES: DS39927B-page 50 Preliminary © 2009 Microchip Technology Inc. ...
Page 53
... Perform Write/Erase operations asm volatile (“bset NVMCON, #WR “nop “nop © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 6.1 NVMCON Register The NVMCON register (Register 6-1) is also the pri- mary control register for data EEPROM program/erase operations. The upper byte contains the control bits ...
Page 54
... PIC24F16KA102 FAMILY REGISTER 6-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER R/S-0, HC R/W-0 R/W-0 WR WREN WRERR bit 15 U-0 R/W-0 R/W-0 — ERASE NVMOP5 bit Unimplemented bit, read as ‘0’ Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 WR: Write Control bit (program or erase) ...
Page 55
... Bulk erase the entire data EEPROM • Write one word • Read one word © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Like program memory operations, the Least Significant bit (LSb) of NVMADR is restricted to even addresses. This is because any given address in the data EEPROM space consists of only the lower word of the program memory width ...
Page 56
... PIC24F16KA102 FAMILY 6.4.1 ERASE DATA EEPROM The data EEPROM can be fully erased, or can be partially erased, at three different sizes: one word, four words or eight words. The bits, NVMOP<1:0> (NVMCON<1:0>), decide the number of words to be erased. To erase partially from the data EEPROM, the following sequence must be followed: 1 ...
Page 57
... Set up a pointer to the EEPROM location to be erased TBLPAG = __builtin_tblpage(&eeData); offset = __builtin_tbloffset(&eeData); __builtin_tblwtl(offset, newData); asm volatile ("disi #5"); __builtin_write_NVM(); © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 6.4.2 SINGLE-WORD WRITE To write a single word in the data EEPROM, the following sequence must be followed: 1. Erase one data EEPROM word (as mentioned in ...
Page 58
... PIC24F16KA102 FAMILY 6.4.3 READING THE DATA EEPROM To read a word from data EEPROM, the table read instruction is used. Since the EEPROM array is only 16 bits wide, only the TBLRDL instruction is needed. The read operation is performed by loading TBLPAG and WREG with the address of the EEPROM location followed by a TBLRDL instruction ...
Page 59
... Uninitialized W Register © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on Power-on Reset (POR) and unchanged by all other Resets ...
Page 60
... PIC24F16KA102 FAMILY REGISTER 7-1: RCON: RESET CONTROL REGISTER R/W-0, HS R/W-0, HS R/W-0 TRAPR IOPUWR SBOREN bit 15 R/W-0, HS R/W-0, HS R/W-0, HS EXTR SWR SWDTEN bit Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit ...
Page 61
... Reset is chosen as shown in Table 7-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 8.0 “Oscillator Configuration” for further details. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY (1) (CONTINUED) Setting Event TABLE 7-2: OSCILLATOR SELECTION vs. ...
Page 62
... PIC24F16KA102 FAMILY 7.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 7-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire. The time at which the device actually begins to execute ...
Page 63
... Microchip Technology Inc. PIC24F16KA102 FAMILY 7.5 Brown-out Reset (BOR) The PIC24F16KA102 family devices implement a BOR circuit, which provides the user several configuration and power-saving options. The BOR is controlled by the <BORV1:BORV0> and (BOREN<1:0>) Configura- tion bits (FPOR<6:5,1:0>). There are a total of four BOR configurations, which are provided in Table 7-3. The BOR threshold is set by the BORV< ...
Page 64
... PIC24F16KA102 FAMILY 7.5.2 DETECTING BOR When BOR is enabled, the BOR bit (RCON<1>) is always reset to ‘1’ on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR and BOR bits are reset to ‘ ...
Page 65
... Table 8-1 and Table 8-2. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 8.1.1 ALTERNATE INTERRUPT VECTOR TABLE (AIVT) The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as displayed in Figure 8-1. Access to the ...
Page 66
... PIC24F16KA102 FAMILY FIGURE 8-1: PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — ...
Page 67
... SPI1 Error SPI1 Event Timer1 Timer2 Timer3 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch Math Error ...
Page 68
... PIC24F16KA102 FAMILY 8.3 Interrupt Control and Status Registers The PIC24F16KA102 family of devices implements a total of 22 registers for the interrupt controller: • INTCON1 • INTCON2 • IFS0, IFS1, IFS3 and IFS4 • IEC0, IEC1, IEC3 and IEC4 • IPC0 through IPC5, IPC7 and IPC15 through IPC19 • ...
Page 69
... The value in parentheses indicates the interrupt priority level if IPL3 = 1. The IPL Status bits are read-only when NSTDIS (INTCON1<15> Bit 8 and bits 4 through 0 are described in Section 3.0 “CPU”. Note: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — — ...
Page 70
... PIC24F16KA102 FAMILY REGISTER 8-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-4 Unimplemented: Read as ‘0’ ...
Page 71
... Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — — — R/W-0, HS ...
Page 72
... PIC24F16KA102 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER2 R/W-0 R-0, HSC U-0 ALTIVT DISI — bit 15 U-0 U-0 U-0 — — — bit 7 HSC = Hardware Settable/Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit ...
Page 73
... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0, HS R/W-0, HS R/W-0, HS U1TXIF U1RXIF SPI1IF U-0 ...
Page 74
... PIC24F16KA102 FAMILY REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0, HS R/W-0, HS R/W-0, HS U2TXIF U2RXIF INT2IF bit 15 U-0 U-0 U-0 — — — bit Hardware Settable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit ...
Page 75
... Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock and Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 76
... PIC24F16KA102 FAMILY REGISTER 8-8: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0, HS — — CTMUIF bit 15 U-0 U-0 U-0 — — — bit Hardware Settable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 77
... IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 ...
Page 78
... PIC24F16KA102 FAMILY REGISTER 8-10: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit ...
Page 79
... Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock and Calendar Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
Page 80
... PIC24F16KA102 FAMILY REGISTER 8-12: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 — — CTMUIE bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
Page 81
... Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 U-0 R/W-1 IC1IP0 — ...
Page 82
... PIC24F16KA102 FAMILY REGISTER 8-14: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 — T2IP2 T2IP1 bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP< ...
Page 83
... Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 U-0 R/W-1 SPF1IP0 — ...
Page 84
... PIC24F16KA102 FAMILY REGISTER 8-16: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 R/W-1 R/W-0 — NVMIP2 NVMIP1 bit 15 U-0 R/W-1 R/W-0 — AD1IP2 AD1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 NVMIP< ...
Page 85
... SI2C1P<2:0>: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 U-0 R/W-1 MI2C1P0 — ...
Page 86
... PIC24F16KA102 FAMILY REGISTER 8-18: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP< ...
Page 87
... INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 U-0 U-0 INT2IP0 — ...
Page 88
... PIC24F16KA102 FAMILY REGISTER 8-20: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP< ...
Page 89
... U1ERIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 U-0 R/W-1 CRCIP0 — U2ERIP2 R/W-0 U-0 U-0 U1ERIP0 — ...
Page 90
... PIC24F16KA102 FAMILY REGISTER 8-22: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 HLVDIP< ...
Page 91
... VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM< ...
Page 92
... PIC24F16KA102 FAMILY 8.4 Interrupt Setup Procedures 8.4.1 INITIALIZATION To configure an interrupt source: 1. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source ...
Page 93
... Oscillator Configuration, refer to the “PIC24F Family Reference Manual”, Section 38. “Oscillator with 500 kHz Low-Power FRC” (DS39726). The oscillator system for the PIC24F16KA102 family of devices has the following features: • A total of five external and internal oscillator options as clock sources, providing 11 different clock modes. • ...
Page 94
... Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins The PIC24F16KA102 family devices consist of two types of secondary oscillator: - High-Power Secondary Oscillator - Low-Power Secondary Oscillator These can be selected by using the SOSCSEL (FOSC< ...
Page 95
... Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. 2: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY The Clock Divider register (Register 9-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator. ...
Page 96
... PIC24F16KA102 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1 Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit ...
Page 97
... Unimplemented: Read as ‘0’ This bit is automatically cleared when the ROI bit is set and an interrupt occurs. Note 1: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-1 R/W-0 R/W-0 (1) DOZE0 DOZEN ...
Page 98
... PIC24F16KA102 FAMILY REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — TUN5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN< ...
Page 99
... OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits ...
Page 100
... DS39927B-page 98 9.5 Reference Clock Output In addition to the CLKO output (F certain oscillator modes, the device clock in the PIC24F16KA102 family devices can also be configured to provide a reference clock output signal to a port pin. 9Ah to This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to application ...
Page 101
... Base clock value bit 7-0 Unimplemented: Read as ‘0’ The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Note 1: Sleep mode. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 R/W-0 R/W-0 ROSEL RODIV3 RODIV2 U-0 ...
Page 102
... PIC24F16KA102 FAMILY NOTES: DS39927B-page 100 Preliminary © 2009 Microchip Technology Inc. ...
Page 103
... Family Reference ”Section 39. Power-Saving Features with Deep Sleep” (DS39727). The PIC24F16KA102 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power ...
Page 104
... Idle mode has completed. The device will then wake-up from Sleep or Idle mode. 10.2.4 DEEP SLEEP MODE In PIC24F16KA102 family devices, Deep Sleep mode is intended to provide the lowest levels of power con- sumption available without requiring the use of external switches to completely remove all power from the device ...
Page 105
... Deep Sleep mode. After exiting Deep Sleep, software can restore the data by reading the registers and clearing the RELEASE bit (DSCON<0>). © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 10.2.4.4 I/O Pins During Deep Sleep During Deep Sleep, the general purpose I/O pins retain their previous states and the Secondary Oscillator (SOSC) will remain running, if enabled ...
Page 106
... PIC24F16KA102 FAMILY 10.2.4.5 Deep Sleep WDT To enable the DSWDT in Deep Sleep mode, program the Configuration bit, DSWDTEN (FDS<7>). The device Watchdog Timer (WDT) need not be enabled for the DSWDT to function. Entry into Deep Sleep mode automatically resets the DSWDT. The DSWDT clock source is selected by the ...
Page 107
... All register bits are reset only in the case of a POR event outside of Deep Sleep mode. Note 1: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this 2: re-arms POR. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY (1) U-0 U-0 U-0 — ...
Page 108
... PIC24F16KA102 FAMILY REGISTER 10-2: DSWSRC: DEEP SLEEP WAKE-UP SOURCE REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0, HS U-0 U-0 DSFLT — — bit Hardware Settable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ ...
Page 109
... Enabling the automatic return to full-speed CPU operation on interrupts is enabled by set- ting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 10.4 Selective Peripheral Module Control Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock ...
Page 110
... PIC24F16KA102 FAMILY NOTES: DS39927B-page 108 Preliminary © 2009 Microchip Technology Inc. ...
Page 111
... For more information on the I/O Ports, refer to the “PIC24F Family Refer- ence Manual”, Section 12. “I/O Ports with Peripheral Pin Select (PPS)” (DS39711). Note that the PIC24F16KA102 family devices do not support Peripheral Pin Select features. All of the device pins (except V ...
Page 112
... NOP. 11.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24F16KA102 family of devices to generate interrupt requests to the processor in response to a change of state on selected input pins. This feature is capable of detecting input change of states even in Sleep mode, when the clocks are ...
Page 113
... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Figure 12-1 presents a block diagram of the 16-bit Timer1 module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS<1:0> bits. ...
Page 114
... PIC24F16KA102 FAMILY REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...
Page 115
... Timer2 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 interrupt flags. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY To configure Timer2/3 for 32-bit operation: 1. Set the T32 bit (T2CON<3> = 1). 2. ...
Page 116
... PIC24F16KA102 FAMILY FIGURE 13-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T3IF 0 ADC Event Trigger Equal MSB Reset (1) Read TMR2 (1) Write TMR2 Data Bus<15:0> The 32-Bit Timer Configuration (T32) bit must be set for 32-bit timer/counter operation. All control bits Note 1: are respective to the T2CON register. ...
Page 117
... TIMER2 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal FIGURE 13-3: TIMER3 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM T3CK TGATE 1 Set T3IF 0 Reset ADC Event Trigger Equal © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 1x Gate Sync TMR2 Sync Comparator PR2 Sync 1x 01 ...
Page 118
... PIC24F16KA102 FAMILY REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer2 On bit When T2CON<3> Starts 32-bit Timer2 Stops 32-bit Timer2/3 When T2CON< ...
Page 119
... External clock from the T3CK pin (on the rising edge Internal clock (F OSC bit 0 Unimplemented: Read as ‘0’ When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all timer Note 1: functions are set through T2CON. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 (1) — — R/W-0 U-0 (1) ...
Page 120
... PIC24F16KA102 FAMILY NOTES: DS39927B-page 118 Preliminary © 2009 Microchip Technology Inc. ...
Page 121
... IC1CON System Bus © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY The PIC24F16KA102 family devices have one input capture channel. The input capture module has multiple operating modes, which are selected via the IC1CON register. The operating modes include: • Capture timer value on every falling edge of input applied at the IC1 pin • ...
Page 122
... PIC24F16KA102 FAMILY 14.1 Input Capture Registers REGISTER 14-1: IC1CON: INPUT CAPTURE 1 CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI1 ICI0 bit Hardware Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘ ...
Page 123
... OC1IE bit. For further information on peripheral interrupts, refer to Section 8.0 “Interrupt Controller”. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 10. To initiate another single pulse output, change the Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to ‘ ...
Page 124
... PIC24F16KA102 FAMILY 15.3 Pulse-Width Modulation (PWM) Mode The following steps should be taken when configuring the output compare module for PWM operation: 1. Set the PWM period by writing to the selected Timer Period register (PRy). 2. Set the PWM duty cycle by writing to the OC1RS register. ...
Page 125
... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (F PWM Frequency 30.5 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 Based /2, Doze mode and PLL are disabled. Note 1: CY OSC © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY )/log 2) bits 10 2) bits 61 Hz 122 Hz 977 FFFFh 7FFFh 0FFFh 16 15 ...
Page 126
... PIC24F16KA102 FAMILY FIGURE 15-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM (1) OC1RS (1) OC1R Comparator TMR Register Inputs from Time Bases Where ‘x’ is depicted, reference is made to the registers associated with the respective Output Compare Channel 1. Note 1: OCFA pin controls OC1 channel. 2: Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the 3: time bases associated with the module ...
Page 127
... Initialize OC1 pin high, compare event forces OC1 pin low 001 = Initialize OC1 pin low, compare event forces OC1 pin high 000 = Output compare channel is disabled OCFA pin controls OC1 channel. Note 1: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — — ...
Page 128
... PIC24F16KA102 FAMILY REGISTER 15-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 3 OC1TRIS: OC1 Output Tri-State Select bit 1 = OC1 output will not be active on the pin ...
Page 129
... Block diagrams of the module in Standard and Enhanced Buffer modes are displayed in Figure 16-1 and Figure 16-2. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY The devices of the PIC24F16KA102 family offer one SPI module on a device. In this section, the SPI module is referred Note SPI1, or separately as SPI1. Special Function Registers (SFRs) will follow a similar notation ...
Page 130
... PIC24F16KA102 FAMILY FIGURE 16-1: SPI1 MODULE BLOCK DIAGRAM (STANDARD BUFFER MODE) SCK1 SS1/FSYNC1 Sync Control Control Clock SDO1 bit 0 SDI1 SPI1SR Transfer SPI1BUF Read SPI1BUF DS39927B-page 128 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer Write SPI1BUF 16 Internal Data Bus ...
Page 131
... SDI1 SPI1SR Transfer 8-Level FIFO Receive Buffer SPI1BUF Read SPI1BUF © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPI1BUF register using interrupts: a) Clear the respective SPI1IF bit in the IFS0 register ...
Page 132
... PIC24F16KA102 FAMILY REGISTER 16-1: SPI1STAT: SPI1 STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 SPIEN — SPISIDL bit 15 R-0,HSC R/C-0, HS R/W-0, HSC SRMPT SPIROV SRXMPT bit Hardware Settable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPI1 Enable bit ...
Page 133
... Automatically cleared in hardware when core reads SPI1BUF location, reading SPI1RXB. In Enhanced Buffer mode: Automatically set in hardware when SPI1 transfers data from SPI1SR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPI1SR. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Preliminary DS39927B-page 131 ...
Page 134
... PIC24F16KA102 FAMILY REGISTER 16-2: SPI1CON1: SPI1 CONTROL REGISTER 1 U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCK1 pin bit (SPI Master modes only) ...
Page 135
... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode) © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — — — ...
Page 136
... PIC24F16KA102 FAMILY EQUATION 16-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED F SCK Note 1: Based OSC TABLE 16-1: SAMPLE SCK FREQUENCIES MHz CY Primary Prescaler Settings MHz CY Primary Prescaler Settings Based /2; Doze mode and PLL are disabled. Note 1: CY OSC SCK1 frequencies indicated in kHz. ...
Page 137
... Pin assignment is controlled by the I2C1SEL Configuration bit. Programming this bit (= 0) multiplexes the module to the SCL1 and SDA1 pins. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 17.2 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
Page 138
... PIC24F16KA102 FAMILY 2 FIGURE 17-1: I C™ BLOCK DIAGRAM Shift SCL1 Clock SDA1 Shift Clock BRG Down Counter DS39927B-page 136 I2C1RCV I2C1RSR LSB Address Match Match Detect I2C1ADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation ...
Page 139
... Address will be Acknowledged only if GCEN = 1. 2: Match on this address can only occur on the upper byte in 10-Bit Addressing mode. 3: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 17.4 Slave Address Masking The I2C1MSK register (Register 17-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes ...
Page 140
... PIC24F16KA102 FAMILY REGISTER 17-1: I2C1CON: I2C1 CONTROL REGISTER R/W-0 U-0 R/W-0 I2CEN — I2CSIDL bit 15 R/W-0 R/W-0 R/W-0 GCEN STREN ACKDT bit Hardware Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 I2CEN: I2C1 Enable bit 1 = Enables the I2C1 module and configures the SDA1 and SCL1 pins as serial port pins 0 = Disables the I2C1 module ...
Page 141
... Repeated Start condition not in progress bit 0 SEN: Start Condition Enable bit (when operating Initiates Start condition on SDA1 and SCL1 pins; hardware clear at end of master Start sequence 0 = Start condition not in progress © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 2 C master; applicable during master receive master ...
Page 142
... PIC24F16KA102 FAMILY REGISTER 17-2: I2C1STAT: I2C1 STATUS REGISTER R-0, HSC R-0, HSC U-0 ACKSTAT TRSTAT — bit 15 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC IWCOL I2COV D/A bit Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ...
Page 143
... TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2C1TRN is full 0 = Transmit complete, I2C1TRN is empty Hardware set when software writes to I2C1TRN; hardware clear at completion of data transmission. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 2 C slave device address byte. Preliminary DS39927B-page 141 ...
Page 144
... PIC24F16KA102 FAMILY REGISTER 17-3: I2C1MSK: I2C1 SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...
Page 145
... IrDA Hardware Flow Control UARTx Receiver UARTx Transmitter © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY • Fully Integrated Baud Rate Generator (IBRG) with 16-Bit Prescaler • Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS • 4-Deep, First-In-First-Out (FIFO) Transmit Data Buffer • ...
Page 146
... PIC24F16KA102 FAMILY 18.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator (BRG). The UxBRG register controls the period of a free-running, 16-bit timer. Equation 18-1 provides the formula for computation of the baud rate with BRGH = 0. EQUATION 18-1: ...
Page 147
... FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 18.5 Receiving in 8-Bit or 9-Bit Data Mode 1. Set up the UART (as described in Section 18.2 “Transmitting in 8-Bit Data Mode”). ...
Page 148
... PIC24F16KA102 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 UARTEN — USIDL bit 15 R/C-0, HC R/W-0 R/W-0, HC WAKE LPBACK ABAUD bit Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> ...
Page 149
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit This feature is only available for the 16x BRG mode (BRGH = 0). Note 1: Bit availability depends on pin availability. 2: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Preliminary DS39927B-page 147 ...
Page 150
... PIC24F16KA102 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL1 URXISEL0 ADDEN bit Clearable bit Legend Hardware Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL< ...
Page 151
... Receive buffer has not overflowed (clearing a previously set OERR bit (1 → 0 transition) will reset the receiver buffer and the RSR to the empty state) bit 0 URXDA: Receive Buffer Data Available bit (read-only Receive buffer has data; at least one more character can be read 0 = Receive buffer is empty © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Preliminary DS39927B-page 149 ...
Page 152
... PIC24F16KA102 FAMILY REGISTER 18-3: UxTXREG: UARTx TRANSMIT REGISTER U-x U-x U-x — — — bit 15 W-x W-x W-x UTX7 UTX6 UTX5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ bit 8 UTX8: Data of the Transmitted Character bit (in 9-bit mode) bit 7-0 UTX< ...
Page 153
... Comparator Alarm Registers with Masks Repeat Counter © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY • Alarm-configurable for half a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month or one year • Alarm repeat with decrementing counter • ...
Page 154
... PIC24F16KA102 FAMILY 19.2 RTCC Module Registers The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 19.2.1 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Time registers ...
Page 155
... The RCFGCAL register is only affected by a POR. Note 1: A write to the RTCEN bit is only allowed when RTCWREN = 1. 2: This bit is read-only cleared to ‘0’ write to the lower half of the MINSEC register. 3: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R-0, HSC R-0, HSC R/W-0 (3) RTCSYNC HALFSEC ...
Page 156
... PIC24F16KA102 FAMILY REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER bit 7-0 CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute . . . 01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment ...
Page 157
... Alarm will repeat 255 more times . . . 00000000 = Alarm will not repeat The counter decrements on any alarm event prevented from rolling over from 00h to FFh unless CHIME = 1. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 R/W-0 R/W-0 AMASK2 AMASK1 AMASK0 R/W-0 ...
Page 158
... PIC24F16KA102 FAMILY 19.2.5 RTCVAL REGISTER MAPPINGS REGISTER 19-4: YEAR: YEAR VALUE REGISTER U-0 U-0 U-0 — — — bit 15 R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN2 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ ...
Page 159
... SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 R/W-x — — WDAY2 ...
Page 160
... PIC24F16KA102 FAMILY 19.2.6 ALRMVAL REGISTER MAPPINGS REGISTER 19-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-x — — DAYTEN1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘ ...
Page 161
... SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-x R/W-x R/W-x MINTEN0 MINONE3 MINONE2 ...
Page 162
... PIC24F16KA102 FAMILY 19.3 Calibration The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses and storing the value into the lower half of the RCFGCAL register ...
Page 163
... Every minute 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week 1000 - Every month (1) 1001 - Every year Annually, except when configured for February 29. Note 1: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Day of the Week Month Day Hours ...
Page 164
... PIC24F16KA102 FAMILY NOTES: DS39927B-page 162 Preliminary © 2009 Microchip Technology Inc. ...
Page 165
... IN BIT 0 D OUT 1 clk © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY The programmable CRC generator offers the following features: • User-programmable polynomial CRC equation • Interrupt output • Data FIFO The module implements a software-configurable CRC generator. The terms of the polynomial and its length can be programmed using the CRCXOR (X< ...
Page 166
... PIC24F16KA102 FAMILY FIGURE 20-2: CRC GENERATOR RECONFIGURED FOR x XOR SDOx BIT 0 BIT 4 clk clk 20.1 User Interface 20.1.1 DATA INTERFACE To start serial shifting, a value of ‘1’ must be written to the CRCGO bit. The module incorporates a FIFO that is 8-level deep when PLEN<3:0> > 7, and 16 deep, otherwise. The data for which the CRC calculated must first be written into the FIFO ...
Page 167
... CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter turned off bit 3-0 PLEN<3:0>: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R-0, HSC R-0, HSC R-0, HSC VWORD4 VWORD3 VWORD2 ...
Page 168
... PIC24F16KA102 FAMILY REGISTER 20-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER R/W-0 R/W-0 R/W-0 X15 X14 X13 bit 15 R/W-0 R/W-0 R/W bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-1 X<15:1>: XOR of Polynomial Term X bit 0 Unimplemented: Read as ‘0’ ...
Page 169
... V DD HLVDIN HLVDEN © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. ...
Page 170
... PIC24F16KA102 FAMILY REGISTER 21-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 HLVDEN — HLSIDL bit 15 R/W-0 R/W-0 R/W-0 VDIR BGVST IRVST bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 HLVDEN: High/Low-Voltage Detect Power Enable bit ...
Page 171
... Selectable Buffer Fill modes • Four result alignment options • Operation during CPU Sleep and Idle modes On all PIC24F16KA102 family devices, the 10-bit A/D Converter has nine analog input pins, designated AN0 through AN5 and AN10 through AN12. In addition, there are two analog input pins for external voltage ...
Page 172
... PIC24F16KA102 FAMILY FIGURE 22-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM REF V - REF V INH AN0 AN1 AN2 AN1 AN3 V INL AN4 AN5 AN10 AN11 AN12 AN1 DS39927B-page 170 V INH S/H DAC V INL 10-Bit SAR Data Formatting ADC1BUF0: ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS ...
Page 173
... A/D conversion is not done Values of ADC1BUFn registers will not retain their values once the ADON bit is cleared. Read out the Note 1: conversion values from the buffer before disabling the module. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — ...
Page 174
... PIC24F16KA102 FAMILY REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 VCFG2 VCFG1 VCFG0 bit 15 R-0, HSC U-0 R/W-0 BUFS — SMPI3 bit 7 HSC = Hardware Settable/Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits VCFG< ...
Page 175
... ADCS<5:0>: A/D Conversion Clock Select bits 11111 = 64 • 11110 = 63 • · · · 00001 = 3 • 00000 = 2 • © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 R/W-0 R/W-0 SAMC4 SAMC3 SAMC2 R/W-0 R/W-0 R/W-0 ADCS4 ADCS3 ADCS2 U = Unimplemented bit, read as ‘0’ ...
Page 176
... PIC24F16KA102 FAMILY - REGISTER 22-4: AD1CHS: A/D INPUT SELECT REGISTER R/W-0 U-0 U-0 CH0NB — — bit 15 R/W-0 U-0 U-0 CH0NA — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit ...
Page 177
... Unimplemented: Read as ‘0’ bit 5-0 CSSL<5:0>: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 R/W-0 R/W-0 PCFG12 PCFG11 PCFG10 ...
Page 178
... PIC24F16KA102 FAMILY EQUATION 22-1: A/D CONVERSION CLOCK PERIOD Based Note 1: CY FIGURE 22-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL ANx PIN 6-11 pF (Typical) Legend value depends on device package and is not tested. Effect of C Note: PIN DS39927B-page 176 ( ADCS = – • (ADCS + 1) ...
Page 179
... Voltage Level © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Preliminary DS39927B-page 177 ...
Page 180
... PIC24F16KA102 FAMILY NOTES: DS39927B-page 178 Preliminary © 2009 Microchip Technology Inc. ...
Page 181
... INA X CV REF © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. A simplified block diagram of the module is displayed in Figure 23-1 ...
Page 182
... PIC24F16KA102 FAMILY FIGURE 23-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CON = 0 , CREF = x , CCH<1:0> Comparator CxINB > CxINA Compare CON = 1 , CREF = 0 , CCH<1:0> INB INA X Comparator CxIND > CxINA Compare CON = 1 , CREF = 0 , CCH<1:0> IND INA X Comparator CxINB > CV Compare REF CON = 1 , CREF = 1 , CCH<1:0> INB REF Comparator CxIND > CV ...
Page 183
... CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of comparator connects Inverting input of comparator connects to CxIND pin 01 = Inverting input of comparator connects to CxINC pin 00 = Inverting input of comparator connects to CxINB pin © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 U-0 U-0 CLPWR — — ...
Page 184
... PIC24F16KA102 FAMILY REGISTER 23-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER R/W-0 U-0 U-0 CMIDL — — bit 15 U-0 U-0 U-0 — — — bit 7 HSC = Hardware Settable/Clearable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CMIDL: Comparator Stop in Idle Mode bit ...
Page 185
... DD CVRSS = 0 CVREN CVRR V - REF © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 24.1 Configuring the Comparator Voltage Reference The comparator voltage reference module is controlled through the CVRCON register (Register 24-1). The comparator voltage reference provides two ranges of comprehensive output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON< ...
Page 186
... PIC24F16KA102 FAMILY REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ ...
Page 187
... FIGURE 25-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT C APP © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 25.1 Measuring Capacitance The CTMU generating an output pulse with a width equal to the time between edge events on two separate input channels ...
Page 188
... PIC24F16KA102 FAMILY 25.2 Measuring Time Time measurements on the pulse width can be similarly performed using the A/D module’s internal capacitor (C ) and a precision resistor for current calibration. AD Figure 25-2 displays the external connections used for time measurements, and how the CTMU and A/D modules are related in this application ...
Page 189
... CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 4 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 R/W-0 R/W-0 TGEN EDGEN EDGSEQEN R/W-0 R/W-0 ...
Page 190
... PIC24F16KA102 FAMILY REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit ...
Page 191
... Section 36. “High-Level Integration with Programmable High/Low-Voltage Detect (HLVD)” (DS39725) • Section 33. “Programming and Diagnostics” (DS39716) PIC24F16KA102 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • Flexible Configuration • ...
Page 192
... PIC24F16KA102 FAMILY REGISTER 26-2: FGS: GENERAL SEGMENT CONFIGURATION REGISTER U-0 U-0 U-0 — — — bit 7 Legend Readable bit C = Clearable bit -n = Value at POR ‘1’ = Bit is set bit 7-2 Unimplemented: Read as ‘0’ bit 1 GSS0: General Segment Code Flash Code Protection bit ...
Page 193
... POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary oscillator disabled oscillator mode selected oscillator mode selected 00 = External clock mode selected © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/P-1 R/P-1 R/P Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/P-1 ...
Page 194
... PIC24F16KA102 FAMILY REGISTER 26-5: FWDT: WATCHDOG TIMER CONFIGURATION REGISTER R/P-1 R/P-1 U-0 FWDTEN WINDIS — bit 7 Legend Readable bit P = Programmable bit -n = Value at POR ‘1’ = Bit is set bit 7 FWDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) ...
Page 195
... PGC1/PGD1 are used for programming and debugging the device 10 = PGC2/PGD2 are used for programming and debugging the device 01 = PGC3/PGD3 are used for programming and debugging the device 00 = Reserved; do not use © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/P-1 R/P-1 (3) (1) I2C1SEL PWRTEN U = Unimplemented bit, read as ‘ ...
Page 196
... PIC24F16KA102 FAMILY REGISTER 26-8: FDS: DEEP SLEEP CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 DSWDTEN DSLPBOR RTCCKSEL DSWCKSEL DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 bit 7 Legend Readable bit P = Programmable bit -n = Value at POR ‘1’ = Bit is set bit 7 DSWDTEN: Deep Sleep Watchdog Timer Enable bit 1 = DSWDT enabled ...
Page 197
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 23-16 Unimplemented: Read as ‘0’ bit 15-8 FAMID<7:0>: Device Family Identifier bits 00001011 = PIC24F16KA102 family bit 7-0 DEV<7:0>: Individual Device Identifier bits 00000011 = PIC24F16KA102 00001010 = PIC24F08KA102 00000001 = PIC24F16KA101 00001000 = PIC24F08KA101 REGISTER 26-10: DEVREV: DEVICE REVISION REGISTER ...
Page 198
... PIC24F16KA102 FAMILY 26.2 Watchdog Timer (WDT) For the PIC24F16KA102 family of devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation ...
Page 199
... Deep Sleep Watchdog Timer (DSWDT) In PIC24F16KA102 family devices, in addition to the WDT module, a DSWDT module is present which runs while the device is in Deep Sleep, if enabled driven by either the SOSC or LPRC oscillator. The clock source is selected by the Configuration bit, DSWCKSEL (FDS<4>). The DSWDT can be configured to generate a time-out at 2 ...
Page 200
... PIC24F16KA102 FAMILY NOTES: DS39927B-page 198 Preliminary © 2009 Microchip Technology Inc. ...