PIC24F16KA102-I/ML Microchip Technology, PIC24F16KA102-I/ML Datasheet - Page 123

• Manufacturer Part Number: PIC24F16KA102-I/ML
• Description: IC PIC MCU FLASH 16K 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F16KA102-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 16KB (5.5K x 24)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 512 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 1.5 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.0
15.1
When the OCM control bits (OC1CON<2:0>) are set to
‘100’, the selected output compare channel initializes
the OC1 pin to the low state and generates a single
output pulse.
To generate a single output pulse, the following steps
are required (these steps assume the timer source is
initially turned off, but this is not a requirement for the
module operation):
1.
2.
3.
4.
5.
6.
7.
8.
9.
© 2009 Microchip Technology Inc.
Note:
Determine the instruction clock cycle time. Take
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
Calculate time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
Calculate the time to the falling edge of the pulse
based on the desired pulse width and the time to
the rising edge of the pulse.
Write the values computed in steps 2 and 3
above into the Output Compare 1 register,
OC1R, and the Output Compare 1 Secondary
register, OC1RS, respectively.
Set Timer Period register, PRy, to value equal to
or greater than the value in OC1RS, the Output
Compare 1 Secondary register.
Set the OCM bits to ‘100’ and the OCTSEL
(OC1CON<3>) bit to the desired timer source.
The OC1 pin state will now be driven low.
Set the TON (TyCON<15>) bit to ‘1’, which
enables the compare time base to count.
Upon the first match between TMRy and OC1R,
the OC1 pin will be driven high.
When the incrementing timer, TMRy, matches
the Output Compare 1 Secondary register,
OC1RS,
(high-to-low) of the pulse is driven onto the OC1
pin. No additional pulses are driven onto the
OC1 pin and it remains low. As a result of the
second compare match event, the OC1IF inter-
rupt flag bit is set, which will result in an interrupt
if it is enabled, by setting the OC1IE bit. For
further information on peripheral interrupts, refer
to Section 8.0 “Interrupt Controller”.
OUTPUT COMPARE
Setup for Single Output Pulse
Generation
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended
reference source. For more information
on Output Compare, refer to the “PIC24F
Family Reference Manual”, Section 16.
“Output Compare” (DS39706).
the
second
to
be
and
a
trailing
comprehensive
edge
Preliminary
PIC24F16KA102 FAMILY
10. To initiate another single pulse output, change
The output compare module does not have to be
disabled after the falling edge of the output pulse.
Another pulse can be initiated by rewriting the value of
the OC1CON register.
15.2
When the OCM control bits (OC1CON<2:0>) are set to
‘101’, the selected output compare channel initializes
the OC1 pin to the low state and generates output
pulses on each and every compare match event.
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required (these steps assume the timer
source is initially turned off, but this is not a requirement
for the module operation):
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. As a result of the second compare match event,
11. When the compare time base and the value in its
12. Steps 8 through 11 are repeated and a con-
the Timer and Compare register settings, if
needed, and then issue a write to set the OCM
bits to ‘100’. Disabling and re-enabling of the
timer and clearing the TMRy register are not
required, but may be advantageous for defining
a pulse from a known event time boundary.
Determine the instruction clock cycle time. Take
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
Calculate time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
Calculate the time to the falling edge of the pulse
based on the desired pulse width and the time to
the rising edge of the pulse.
Write the values computed in step 2 and 3 above
into the Output Compare 1 register, OC1R, and the
Output Compare 1 Secondary register, OC1RS,
respectively.
Set the Timer Period register, PRy, to a value
equal to or greater than the value in OC1RS.
Set the OCM bits to ‘101’ and the OCTSEL bit to
the desired timer source. The OC1 pin state will
now be driven low.
Enable the compare time base by setting the
TON (TyCON<15>) bit to ‘1’.
Upon the first match between TMRy and OC1R,
the OC1 pin will be driven high.
When the compare time base, TMRy, matches the
OC1RS, the second and trailing edge (high-to-low)
of the pulse is driven onto the OC1 pin.
the OC1IF interrupt flag bit is set.
respective Timer Period register match, the TMRy
register resets to 0x0000 and resumes counting.
tinuous
indefinitely. The OC1IF flag is set on each
OC1RS/TMRy compare match event.
Setup for Continuous Output
Pulse Generation
stream
of
pulses
DS39927B-page 121
is
generated