PIC24F16KA101-I/P Microchip Technology, PIC24F16KA101-I/P Datasheet - Page 166

IC PIC MCU FLASH 16K 20-DIP

PIC24F16KA101-I/P

Manufacturer Part Number
PIC24F16KA101-I/P
Description
IC PIC MCU FLASH 16K 20-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr

Specifications of PIC24F16KA101-I/P

Program Memory Type
FLASH
Program Memory Size
16KB (5.5K x 24)
Package / Case
20-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24F
Core
PIC
Data Bus Width
16 bit
Data Ram Size
1.5 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA240017 - MODULE PLUG-IN PIC24F16KA102 PIMAC164337 - MODULE SOCKET FOR PM3 40DIP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC24F16KA102 FAMILY
FIGURE 20-2:
20.1
20.1.1
To start serial shifting, a value of ‘1’ must be written to
the CRCGO bit.
The module incorporates a FIFO that is 8-level deep
when PLEN<3:0> > 7, and 16 deep, otherwise. The
data for which the CRC is to be calculated must first be
written into the FIFO. The smallest data element that
can be written into the FIFO is one byte.
For example, if PLEN = 5, then the size of the data is
PLEN + 1 = 6. The data must be written as follows:
Once data is written into the CRCWDAT MSb (as
defined by PLEN), the value of the VWORD bits
(CRCCON<12:8>) increments by one. The serial
shifter starts shifting data into the CRC engine when
CRCGO = 1 and VWORD<4:0> > 0. When the Most
Significant bit (MSb) is shifted out, the VWORD bits
decrement by one. The serial shifter continues shifting
until the VWORD bits reach zero. Therefore, for a given
value of PLEN, it will take (PLEN + 1) * VWORD
number of clock cycles to complete the CRC
calculations.
When the VWORD bits reach 8 (or 16), the CRCFUL bit
will be set. When the VWORD bits reach 0, the
CRCMPT bit will be set.
To continually feed data into the CRC engine, the
recommended mode of operation is to initially “prime”
the FIFO with a sufficient number of words so no
interrupt is generated before the next word can be
written. Once that is done, start the CRC by setting the
CRCGO bit to ‘1’. From that point onward, the VWORD
bits should be polled. If they read less than 8 or 16,
another word can be written into the FIFO.
DS39927B-page 164
SDOx
data<5:0> = crc_input<5:0>
data<7:6> = bxx
XOR
User Interface
DATA INTERFACE
D
BIT 0
clk
Q
CRC GENERATOR RECONFIGURED FOR x
D
clk
BIT 4
Q
Preliminary
D
BIT 5
clk
Q
To empty words already written into a FIFO, the
CRCGO bit must be set to ‘1’ and the CRC shifter
allowed to run until the CRCMPT bit is set.
Also, to get the correct CRC reading, it will be
necessary to wait for the CRCMPT bit to go high before
reading the CRCWDAT register.
If a word is written when the CRCFUL bit is set, the
VWORD Pointer will roll over to 0. The hardware will
then behave as if the FIFO is empty. However, the
condition to generate an interrupt will not be met;
therefore, no interrupt will be generated (see
Section 20.1.2 “Interrupt Operation”).
At least one instruction cycle must pass after a write to
CRCWDAT before a read of the VWORD bits is done.
20.1.2
When the VWORD<4:0> bits make a transition from a
value of ‘1’ to ‘0’, an interrupt will be generated.
20.2
20.2.1
If Sleep mode is entered while the module is operating,
the module will be suspended in its current state until
clock execution resumes.
20.2.2
To continue full module operation in Idle mode, the
CSIDL bit must be cleared prior to entry into the mode.
If CSIDL = 1, the module will behave the same way as
it does in Sleep mode; pending interrupt events will be
passed on, even though the module clocks are not
available.
Operation in Power Save Modes
16
INTERRUPT OPERATION
SLEEP MODE
IDLE MODE
+ x
12
CRC Read Bus
D
BIT 12
clk
+ x
Q
5
© 2009 Microchip Technology Inc.
+ 1
CRC Write Bus
BIT 15
D
clk
Q

Related parts for PIC24F16KA101-I/P