PIC18LF24J11-I/ML Microchip Technology, PIC18LF24J11-I/ML Datasheet
PIC18LF24J11-I/ML
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PIC18LF24J11-I/ML Summary of contents
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... High-Performance Microcontrollers © 2009 Microchip Technology Inc. PIC18F46J11 Family 28/44-Pin, Low-Power, with nanoWatt XLP Technology Data Sheet DS39932C ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Hardware Real-Time Clock and Calendar (RTCC): - Provides clock, calendar and alarm functions • High-Current Sink/Source 25 mA/25 mA (PORTB and PORTC) © 2009 Microchip Technology Inc. Peripheral Highlights (Continued): • Four Programmable External Interrupts • Four Input Change Interrupts • Two Enhanced Capture/Compare/PWM (ECCP) ...
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... Device PIC18F24J11 28 16K 3776 16 PIC18F25J11 28 32K 3776 16 PIC18F26J11 28 64K 3776 16 PIC18F44J11 44 16K 3776 22 PIC18F45J11 44 32K 3776 22 PIC18F46J11 44 64K 3776 22 PIC18LF24J11 28 16K 3776 16 PIC18LF25J11 28 32K 3776 16 PIC18LF26J11 28 64K 3776 16 PIC18LF44J11 44 16K 3776 22 PIC18LF45J11 44 32K 3776 22 PIC18LF46J11 44 64K 3776 22 Note 1: See Section 1.3 “Details on Individual Family Devices”, Section 3.6 “Deep Sleep Mode” and Section 25.3 “ ...
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... Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “Peripheral Pin Select (PPS)”. 2: See Section 25.3 “On-Chip Voltage Regulator” for details on how to connect the V 3: For the QFN package recommended that the bottom pad be connected to V © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY ...
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... See Section 25.3 “On-Chip Voltage Regulator” for details on how to connect the V 3: For the QFN package recommended that the bottom pad be connected to V DS39932C-page PIC18F4XJ11 Pins are tolerant OSC2/CLKO/RA6 OSC1/CLKI/RA7 RE2/AN7/PMCS RE1/AN6/PMWR RE0/AN5/PMRD RA5/AN4/SS1/HLVDIN/RP2 ( DDCORE CAP /V pin. DDCORE CAP . SS © 2009 Microchip Technology Inc. ...
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... RPn pins. For a list of the input and output functions, see Table 9-13 and Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “Peripheral Pin Select (PPS)”. 2: See Section 25.3 “On-Chip Voltage Regulator” for details on how to connect the V © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY ...
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... Electrical Characteristics .......................................................................................................................................................... 461 29.0 Packaging Information.............................................................................................................................................................. 499 Appendix A: Revision History............................................................................................................................................................. 511 Appendix B: Device Differences......................................................................................................................................................... 511 The Microchip Web Site ..................................................................................................................................................................... 525 Customer Change Notification Service .............................................................................................................................................. 525 Customer Support .............................................................................................................................................................................. 525 Reader Response .............................................................................................................................................................................. 526 Product Identification System............................................................................................................................................................. 527 DS39932C-page 8 © 2009 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY DS39932C-page 9 ...
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... PIC18F46J11 FAMILY NOTES: DS39932C-page 10 © 2009 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F24J11 • PIC18LF24J11 • PIC18F25J11 • PIC18LF25J11 • PIC18F26J11 • PIC18LF26J11 • PIC18F44J11 • PIC18LF44J11 • PIC18F45J11 • PIC18LF45J11 • PIC18F46J11 • PIC18LF46J11 1.1 Core Features 1.1.1 nanoWatt TECHNOLOGY ...
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... For “LF” parts, an external supply of 2.0V-2.7V has to be supplied to the V 2.0V-3.6V supplied DDCORE exceed For more details about the internal voltage regulator, see Section 25.3 “On-Chip Voltage Regulator”. © 2009 Microchip Technology Inc. , but should DD through a SS pin with DDCORE should never ...
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... Data Memory (Bytes) Interrupt Sources I/O Ports Timers Enhanced Capture/Compare/PWM Modules Serial Communications Parallel Communications (PMP/PSP) 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY PIC18F24J11 PIC18F25J11 DC – 48 MHz DC – 48 MHz 16K 32K 8,192 16,384 3.8K 3 ...
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... Start-up Timer Power-on Reset Watchdog Timer Brown-out (2) Reset MCLR DD SS Timer1 Timer2 Timer3 Timer4 EUSART2 EUSART1 PORTA Data Latch (1) RA0:RA7 (3.8 Kbytes) 12 PORTB (1) RB0:RB7 12 4 Access Bank 12 PORTC (1) RC0:RC7 logic 8 PRODH PRODL Multiply ALU<8> 8 Comparators MSSP1 MSSP2 © 2009 Microchip Technology Inc. ...
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... ADC RTCC LVD 10-Bit PMP CTMU ECCP1 Note 1: See Table 1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-chip voltage regulator is enabled. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Data Latch 8 8 Data Memory (3.8 Kbytes) PCLATU PCLATH ...
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... In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL Digital I/O. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Buffer Type Type 28-QFN PORTA is a bidirectional I/O port. ...
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... Interrupt-on-change pin. I/O DIG Remappable peripheral pin 7. 23 I/O DIG Digital I/O. I/O DIG Parallel Master Port address. I/O DIG Remappable peripheral pin 8. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Buffer Type Type 28-QFN PORTB (continued) 24 ...
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... DIG Remappable peripheral pin 17. 15 I/O ST Digital I/ Asynchronous serial receive data input. I/O ST Synchronous serial data output/input. I/O DIG Remappable peripheral pin 18. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Buffer Type Type 28-QFN 5 P — ...
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... RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL Digital I/O. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Buffer 44- 44- Type Type TQFP PORTA is a bidirectional I/O port ...
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... Remappable peripheral pin I/O DIG Digital I/O. I Analog Analog input CTMU edge 2 input. O DIG Parallel Master Port address. I/O DIG Remappable peripheral pin 6. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Buffer 44- 44- Type Type TQFP ...
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... SPI data input I data I/O. I/O DIG Remappable peripheral pin 15 I/O ST Digital /O. O DIG SPI data output. I/O DIG Remappable peripheral pin 16. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Buffer 44- 44- Type Type TQFP ...
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... Parallel Master Port data. I/O DIG Remappable peripheral pin 23 I/O ST Digital I/O. I/O DIG Parallel Master Port data. I/O DIG Remappable peripheral pin 24. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Buffer 44- 44- Type Type TQFP PORTE is a bidirectional I/O port ...
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... PIC18F46J11 FAMILY NOTES: DS39932C-page 30 © 2009 Microchip Technology Inc. ...
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... RA6, the output frequency will be one fourth of the peripheral clock frequency. The clock output stops when in Sleep mode, but will continue during Idle mode (see Figure 2-1). © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 2-1: OSCILLATOR MODES ...
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... MHz 011 250 kHz 010 125 kHz 001 31 kHz 1 000 0 OSCTUNE<7> HS, EC T1OSC Peripherals Internal Oscillator CPU IDLEN Clock Control FOSC<2:0> OSCCON<1:0> Clock Source Option for Other Modules WDT, PWRT, FSCM and Two-Speed Start-up © 2009 Microchip Technology Inc. ...
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... See the notes following Table 2-3 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 2-3: Osc Type HS Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... Watchdog Timer • Two-Speed Start-up These features are discussed in more detail in Section 25.0 “Special Features of the CPU”. The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (page 38). © 2009 Microchip Technology Inc. ...
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... The low-frequency INTRC oscillator operates indepen- dently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 2.2.5.3 Compensating for INTOSC Drift It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register ...
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... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor (FSCM). R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown clock is available as a © 2009 Microchip Technology Inc. ...
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... If none of these bits are set, the INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY The IDLEN bit determines if the device goes into Sleep mode, or one of the Idle modes, when the SLEEP instruction is executed ...
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... Default output frequency of INTOSC on Reset (4 MHz). 3: Source selected by the INTSRC bit (OSCTUNE<7>). DS39932C-page 38 (1) R/W-0 R-1 U-1 IRCF0 OSTS — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (3) (1) R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Base clock value Note 1: The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY The ROSSLP and ROSEL bits (REFOCON<5:4>) control the availability of the reference output during Sleep mode ...
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... This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the internal oscillator or EC modes are used as the primary clock source. are listed in (parameter 38, CSD © 2009 Microchip Technology Inc. ...
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... Selecting a power-managed mode requires these decisions: • Will the CPU be clocked? • If so, which clock source will be used? © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY The IDLEN bit (OSCCON<7>) controls CPU clocking and the SCS<1:0> bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1 ...
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... SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. In such situa- tions, initial oscillator operation is far from stable and unpredictable operation may result. © 2009 Microchip Technology Inc. ...
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... Note 1024 OST OSC © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock would be providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run ...
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... SCS bits are not affected by the switch. The INTRC clock source will continue to run if either the WDT or the FSCM is enabled. block (see n-1 n Clock Transition (1) (1) T PLL 1 2 n-1 n Clock Transition OSTS Bit Set = 2 ms (approx). These intervals are not shown to scale. PLL © 2009 Microchip Technology Inc. ...
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... OST OSC PLL © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS<1:0> bits becomes ready (see Figure 3-6 will be clocked from the internal oscillator if either the Two-Speed Start-up or the FSCM is enabled (see Section 25 ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. © 2009 Microchip Technology Inc CSD ...
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... TRANSITION TIMING FOR ENTRY TO IDLE MODE OSC1 CPU Clock Peripheral Clock Program PC Counter FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 OSC1 CPU Clock Peripheral Clock Program Counter Wake Event © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY CSD DS39932C-page 47 ...
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... V voltage regulator, Deep Sleep DDCORE capability is available only on PIC18FXXJ members in the device family. The on-chip voltage regulator is not available in PIC18LFXXJ members of the device family, and therefore, they do not support Deep Sleep. © 2009 Microchip Technology Inc. “Run voltage ...
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... DSGPR0 and DSGPR1 registers. The contents of these registers are preserved while the device is in Deep Sleep, and will remain valid throughout an entire Deep Sleep entry and wake-up sequence. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 3.6.2 I/O PINS DURING DEEP SLEEP During Deep Sleep, the general purpose I/O pins will retain their previous states ...
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... INTRC and T1OSC/T1CKI. If the INTRC is used, the RTCC accuracy will directly depend on the INTRC tolerance. For more information on configuring the RTCC peripheral, see Section 16.0 “Real-Time Clock and Calendar (RTCC)”. © 2009 Microchip Technology Inc. supply rail DD ...
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... For more information on configuring this peripheral, see Section 3.7 Low-Power Wake-up”. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 3.6.8 DEEP SLEEP FAULT DETECTION If during Deep Sleep the device is subjected to unusual operating conditions, such as an Electrostatic Dis- charge (ESD) event possible that the internal circuit states used by the Deep Sleep module could become corrupted ...
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... DSBOR arming voltage during Deep Sleep, DD DSBOR did not drop below the DSBOR arming voltage during Deep Sleep DD is initially applied. R/W-0 R/W-0 R/W-0 DSULPEN RTCWDIS bit Bit is unknown (1) (1) R/W-0 R/W-0 R/W-0 DSBOR RELEASE bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Contents are retained even in Deep Sleep mode. Note 1: All register bits are maintained unless: V Sleep, or, the device is in Deep Sleep and the dedicated DSBOR is enabled and V DSBOR threshold, or DSBOR is enabled or disabled, but V © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY (1) R/W-xxxx U = Unimplemented bit, read as ‘0’ ...
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... Bit is cleared R/W-0 R/W-0 R/W-0 (2) (2) (2) DSWDT DSRTC DSMCLR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (2) (2) (2) U-0 U-0 R/W-0 — — DSINT0 bit Bit is unknown U-0 R/W-1 (2) — DSPOR bit Bit is unknown (1) © 2009 Microchip Technology Inc. ...
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... Also in Sleep mode, only the remappable output func- tion, ULPWU, will output this bit value to an RPn pin for externally detecting wake-up events. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY See Example 3-1 for initializing the ULPWU module. Note: ...
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... Deep Sleep OSCCONbits.IDLEN = 0;// enable deep sleep DSCONHbits.DSEN = 1;// Note: must be set just before executing Sleep(); //**************** //Enter Sleep Mode //**************** Sleep(); // for sleep, execution will resume here // for deep sleep, execution will restart at reset vector (use WDTCONbits.DS to detect) DS39932C-page 56 © 2009 Microchip Technology Inc. ...
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... PWRT 32 ms PWRT 11-Bit Ripple Counter INTRC Note 1: The Brown-out Reset is not available in PIC18LF2XJ11 and PIC18LF4XJ11 devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Figure 4-1 provides a simplified block diagram of the on-chip Reset circuit. 4.1 RCON Register Device Reset events are tracked through the RCON register (Register 4-1) ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39932C-page 58 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... POR. All registers will be set back to their POR Reset values and the contents of the DSGPR0 and DSGPR1 holding registers will be lost. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Additionally, if any I/O pins had been configured as out- puts during Deep Sleep, these pins will be tri-stated and the device will no longer be held in Deep Sleep ...
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... PWRT will expire. Bringing MCLR high will begin execution immediately if a clock source is available (Figure 4-4). This is useful for testing purposes synchronize more than one PIC18FXXXX device operating in parallel. T PWRT ) for PWRT , V RISE < PWRT © 2009 Microchip Technology Inc. ...
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... FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-5: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY T PWRT T PWRT , V RISE > 3. PWRT ): CASE 1 ...
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... These bits are used in software to determine the nature of the Reset. Table 4-2 describes the Reset states for all of the Special Function Registers. These are categorized by POR and BOR, MCLR and WDT Resets, and WDT wake-ups. RCON Register ( POR STKPTR Register BOR STKFUL STKUNF © 2009 Microchip Technology Inc. ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu 0uuu uuuu 0uuu uuuu uuuu uxuu ---- -uuu ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uu-- uuuu uu-- uuuu uuuu uuuu uu-u uuuu uuuu uuuu ---- --uu ---- --uu ---- --uu u-uu uuuu uuuu uuuu ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...
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... PIC18F46J11 FAMILY NOTES: DS39932C-page 70 © 2009 Microchip Technology Inc. ...
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... Config. Words Unimplemented Read as ‘0’ Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space ...
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... Additional details on the device Configuration Words are provided in Section 25.1 “Configuration Bits”. TABLE 5-1: FLASH CONFIGURATION WORD FOR PIC18F46J11 FAMILY DEVICES Program Configuration Device Memory (Kbytes) PIC18F24J11 3FF8h to 3FFFh 16 PIC18F44J11 PIC18F25J11 7FF8h to 7FFFh 32 PIC18F45J11 PIC18F26J11 64 FFF8h to FFFFh PIC18F46J11 © 2009 Microchip Technology Inc. Word Addresses ...
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... TOSH TOSL 00h 1Ah 34h © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer (SP), STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable, and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers (SFRs) ...
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... Stack Pointer. The previous value st push pushed onto the stack then becomes the TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 SP1 SP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... SUB1 • RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 5.1.6 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures or look-up tables in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Execute INST ( Fetch INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1 © 2009 Microchip Technology Inc. ...
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... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. this is © 2009 Microchip Technology Inc. ...
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... Bank 15 60h FFh Note 1: Addresses EC0h through F5Fh are not part of the Access Bank. Either the BANKED or the MOVFF instruction should be used to access these SFRs. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Data Memory Map 000h Access RAM 05Fh 060h ...
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... This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upward toward the bottom of the SFR area. GPRs are not initialized by a POR and are unchanged on all other Resets. (2) From Opcode © 2009 Microchip Technology Inc. ...
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... PMADDRH and PMDOUTH share the same address and PMADDRL and PMDOUTL share the same address. PMADDRx is used in Master modes and PMDOUTx is used in Slave modes. 5: Reserved: Do not write to this location. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY ALU’s STATUS register is described later in this section. Registers related to the operation of the peripheral features are described in the chapter for that peripheral ...
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... ECBh RPOR5 RPINR4 ECAh RPOR4 RPINR3 EC9h RPOR3 RPINR2 EC8h RPOR2 RPINR1 EC7h RPOR1 RPINR0 EC6h RPOR0 — EC5h — — EC4h — — EC3h — — EC2h — — EC1h — — EC0h — © 2009 Microchip Technology Inc. ...
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... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY • PMADDRH/L and PMDOUT2H/L: In this case, these named buffer pairs are actually the same physical registers ...
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... ULPSINK SWDTEN 1xx- 0000 64, 400 STRB STRA 00-0 0001 64, 261 PSS1BD1 PSS1BD0 0000 0000 64 P1DC1 P1DC0 65 0000 0000 65 xxxx xxxx 65 xxxx xxxx CCP1M1 CCP1M0 65 0000 0000 2 C™ Slave mode. See Section 18.5.3.2 “Address © 2009 Microchip Technology Inc. ...
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... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Bit 4 Bit 3 Bit 2 — ...
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... SEN 0000 0000 67, 288 (4) ADMSK1 SEN COUT2 COUT1 ---- --11 67, 357 -000 0000 67, 173 0000 0000 67, 173 0000 0000 67, 173 0000 0000 67, 173 67 0000 0000 67 0000 0000 67 xxxx xxxx 2 C™ Slave mode. See Section 18.5.3.2 “Address © 2009 Microchip Technology Inc. ...
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... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Bit 4 Bit 3 Bit 2 — ...
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... C™ Slave mode. See Section 18.5.3.2 “Address © 2009 Microchip Technology Inc. ...
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... For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY register then reads back as ‘000u u1uu’ recom- ...
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... EXAMPLE 5-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H All done with ; Bank1? BRA NEXT ; NO, clear next CONTINUE ; YES, continue © 2009 Microchip Technology Inc. Stack Pointer ...
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... FCCh. This means the contents of location FCCh will be added to that of the W register and stored back in FCCh. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY SFR space but are not physically implemented. Read- ing or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...
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... The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remains unchanged. © 2009 Microchip Technology Inc. ...
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... Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 5.6.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE ...
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... FSR2H F00h Bank 15 F60h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 060h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F60h SFRs FFFh Data Memory © 2009 Microchip Technology Inc. 00h 60h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... F00h BSR. F60h FFFh © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any Indirect or ...
Page 96
... PIC18F46J11 FAMILY NOTES: DS39932C-page 96 © 2009 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 98
... Reset write operation was Reading attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Table Latch (8-bit) TABLAT © 2009 Microchip Technology Inc. ...
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... Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-x R/W-0 FREE ...
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... Figure 6-3 illustrates the relevant boundaries of TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE READ: TBLPTR<21:0> TBLPTRL 0 © 2009 Microchip Technology Inc. ...
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... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 102
... The CPU will stall for the duration of the erase for T (see parameter D133B Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; enable write to memory ; enable Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts © 2009 Microchip Technology Inc. ...
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... Write the 64 bytes into the holding registers with auto-increment. 7. Set the WREN bit (EECON1<2>) to enable byte writes. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device ...
Page 104
... TBLWT holding register. ; loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ; re-enable interrupts ; disable write to memory ; done with one write cycle ; if not done replacing the erase block © 2009 Microchip Technology Inc. ...
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... MOVWF EECON2 BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WPROG BCF EECON1, WREN © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 3. Set the WREN bit (EECON1<2>) to enable writes and the WPROG bit (EECON1<5>) to select Word Write mode. 4. Disable interrupts. 5. Write 55h to EECON2. ...
Page 106
... See Section 25.6 “Program Verification and Code Protection” for details on code protection of Flash program memory. Bit 4 Bit 3 Bit 2 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) INT0IE RBIE TMR0IF FREE WRERR WREN Reset Bit 1 Bit 0 Values on Page INT0IF RBIF — 65 © 2009 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY EXAMPLE 7- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
Page 108
... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2009 Microchip Technology Inc. ...
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... Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 110
... IPEN PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP © 2009 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
Page 111
... None of the RB<7:4> pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB and waiting 1 T condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Note: Interrupt flag bits are set when an interrupt ...
Page 112
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39932C-page 112 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 ...
Page 114
... R-0 R/W-0 R/W-0 TX1IF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... A TMR1/TMR3 register capture occurred (must be cleared in software TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY U-0 R/W-0 R/W-0 BCL1IF LVDIF — ...
Page 116
... RTCCIF: RTCC Interrupt Flag bit 1 = RTCC interrupt occurred (must be cleared in software RTCC interrupt occurred DS39932C-page 116 R/W-0 R/W-0 R/W-0 TX2IF TMR4IF CTMUIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TMR3GIF RTCCIF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: These bits are unimplemented on 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘ ...
Page 118
... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39932C-page 118 U-0 R/W-0 R/W-0 BCL1IE LVDIE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown ...
Page 119
... Enabled 0 = Disabled bit 1 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 RTCCIE: RTCC Interrupt Enable bit 1 = Enabled 0 = Disabled © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 R/W-0 TX2IE TMR4IE CTMUIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 120
... TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: These bits are unimplemented on 28-pin devices. DS39932C-page 120 R/W-1 R/W-1 R/W-1 TX1IP SSP1IP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY U-0 R/W-1 R/W-1 BCL1IP LVDIP — Unimplemented bit, read as ‘0’ ...
Page 122
... Low priority bit 0 RTCCIP: RTCC Interrupt Priority bit 1 = High priority 0 = Low priority DS39932C-page 122 R/W-1 R/W-1 R/W-1 TX2IP TMR4IP CTMUIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TMR3GIP RTCCIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... For details on bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details on bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details on bit operation, see Register 4-1. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘ ...
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... Example 8-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS © 2009 Microchip Technology Inc. ...
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... EN RD PORT Note 1: I/O pins have diode protection © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 9.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 9 ...
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... TTL buffers with the PMPTTL bit in the PADCFG1 reg- ister (Register 9-4). Setting this bit configures all data and control input pins for the PMP to use TTL buffers. By default, these PMP inputs use the port’s ST buffers. © 2009 Microchip Technology Inc. 5V ...
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... U2OD: USART2 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled bit 0 U1OD: USART1 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ...
Page 128
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 R/W-0 (1) — — RTSECSEL1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 SPI2OD SPI1OD bit Bit is unknown R/W-0 R/W-0 (1) RTSECSEL0 PMPTTL bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY EXAMPLE 9-2: INITIALIZING PORTA ...
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... LATA<3> data output; not affected by analog input. I TTL PORTA<3> data input; disabled when analog input enabled. I ANA A/D input channel 3 and Comparator C1+ input. Default input configuration on POR. I ANA A/D and comparator voltage reference high input. I ANA Comparator 1 input B output enabled. REF © 2009 Microchip Technology Inc. ...
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... COE CVRCON CVREN CVROE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: These bits are only available in 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY I/O I/O Type O DIG LATA<5> data output; not affected by analog input. ...
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... PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. The RB5 pin is multiplexed with the Timer0 module clock input and one of the comparator outputs to become the RB5/KBI1/SDI1/SDA1/RP8 pin. © 2009 Microchip Technology Inc. ...
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... Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default when PBADEN is set and digital inputs when PBADEN is cleared. 2: All other pin functions are disabled when ICSP™ or ICD are enabled. 3: This bit is not available on 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY I/O I/O Type 1 TTL PORTB< ...
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... PORTB<7> data input; weak pull-up when RBPU bit is cleared. I TTL Interrupt-on-change pin. O DIG Serial execution data output for ICSP and ICD operation Serial execution data input for ICSP and ICD operation Remappable peripheral pin 10 input Remappable peripheral pin 10 output. Description (1) (2) (2) © 2009 Microchip Technology Inc. ...
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... INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP ADCON0 PCFG7 PCFG6 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 LATB5 ...
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... CLRF LATC ; Alternate method ; to clear output ; data latches MOVLW 0x3F ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<5:0> as inputs ; RC<7:6> as outputs MOVLB 0x0F ; ANCON register is not in Access Bank BSF ANCON1,PCFG11 ;Configure RC2/AN11 as digital input © 2009 Microchip Technology Inc. ...
Page 137
... C/SMBus input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Enhanced PWM output is available only on PIC18F4XJ11 devices. 2: This bit is only available on 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY (1) I/O I/O Type ...
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... Remappable peripheral pin 18 input. O DIG Remappable peripheral pin 18 output. Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATC4 LATC3 LATC2 TRISC5 TRISC4 TRISC3 TRISC2 Description Reset Bit 1 Bit 0 Values on page: RC1 RC0 81 LATC1 LATC0 81 TRISC1 TRISC0 81 © 2009 Microchip Technology Inc. ...
Page 139
... PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Note POR, these pins are configured as digital inputs. ...
Page 140
... Remappable peripheral pin 21 output PORTD<5> data input. O DIG LATD<5> data output. I TTL Parallel Master Port data in. O DIG Parallel Master Port data out Remappable peripheral pin 22 input. O DIG Remappable peripheral pin 22 output. Description 2 2 C/SMB = I C/SMBus © 2009 Microchip Technology Inc. ...
Page 141
... LATD LATD7 LATD6 (1) TRISD TRISD7 TRISD6 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. Note 1: These registers are not available in 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY I/O I/O Type I ST PORTD<6> data input. O DIG LATD< ...
Page 142
... REPU (PORTE<6>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a POR. Note that the pull-ups can be used for any set of features, similar to the pull-ups found on PORTB. © 2009 Microchip Technology Inc. ...
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... Note 1: PORTD Pull-up Enable bit 0 = All PORTD pull-ups are disabled 1 = PORTD pull-ups are enabled for any input pad 2: PORTE Pull-up Enable bit 0 = All PORTE pull-ups are disabled 1 = PORTE pull-ups are enabled for any input pad © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY I/O I/O Type I ST PORTE< ...
Page 144
... The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on whether an input or an output is being mapped. © 2009 Microchip Technology Inc. ...
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... SPI2 Slave Select Input PWM Fault Input Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY with one of the pin selectable peripherals. Programming a given peripheral’s bit field with an appropriate 5-bit value maps the RPn pin with that value to that peripheral ...
Page 146
... ECCP1 Compare or PWM Output Channel A ECCP1 Enhanced PWM Output, Channel B ECCP1 Enhanced PWM Output, Channel C ECCP1 Enhanced PWM Output, Channel D ECCP2 Compare or PWM Output ECCP2 Enhanced PWM Output, Channel B ECCP2 Enhanced PWM Output, Channel C ECCP2 Enhanced PWM Output, Channel D © 2009 Microchip Technology Inc. ...
Page 147
... If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset will be triggered. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 9.7.4.3 Configuration Bit Pin Select Lock As an additional level of safety, the device can be con- figured to prevent more than one write session to the RPINRx and RPORx registers ...
Page 148
... EECON2 PPS Write Protected BSF PPSCON, IOLOCK, BANKED _endasm Note: If the Configuration bit, IOL1WAY = 1, once the IOLOCK bit is set, it cannot be cleared, preventing any future RP register changes. The IOLOCK bit is cleared back to ‘0’ on any device Reset. © 2009 Microchip Technology Inc. ...
Page 149
... I/O lock active, RPORx and RPINRx registers are write-protected 0 = I/O lock not active, pin configurations can be changed Note 1: Register values can only be changed if PPSCON<IOLOCK> © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Note: Input and output register values can only be changed if PPS<IOLOCK> See Example 9-7 for a specific command sequence ...
Page 150
... R/W-1 R/W-1 R/W-1 INTR3R4 INTR3R3 INTR3R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 INTR1R1 INTR1R0 bit Bit is unknown R/W-1 R/W-1 INTR2R1 INTR2R0 bit Bit is unknown R/W-1 R/W-1 INTR3R1 INTR3R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 151
... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC1R<4:0>: Assign Input Capture 1 (ECCP1) to the Corresponding RPn Pin bits © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-1 R/W-1 R/W-1 T0CKR4 T0CKR3 T0CKR2 U = Unimplemented bit, read as ‘ ...
Page 152
... R/W-1 R/W-1 R/W-1 T3GR4 T3GR3 T3GR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 IC2R1 IC2R0 bit Bit is unknown R/W-1 R/W-1 T1GR1 T1GR0 bit Bit is unknown R/W-1 R/W-1 T3GR1 T3GR0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 153
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-1 R/W-1 R/W-1 RX2DT2R4 RX2DT2R3 RX2DT2R2 U = Unimplemented bit, read as ‘0’ ...
Page 154
... R/W-0 R/W-0 R/W-0 OCFAR4 OCFAR3 OCFAR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 SCK2R1 SCK2R0 bit Bit is unknown R/W-1 R/W-1 SS2R1 SS2R0 bit Bit is unknown R/W-0 R/W-0 OCFAR1 OCFAR0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 155
... Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 9-14 for peripheral function numbers) © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 R/W-0 RP0R4 RP0R3 RP0R2 U = Unimplemented bit, read as ‘ ...
Page 156
... R/W-0 R/W-0 R/W-0 RP5R4 RP5R3 RP5R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP3R1 RP3R0 bit Bit is unknown R/W-0 R/W-0 RP4R1 RP4R0 bit Bit is unknown R/W-0 R/W-0 RP5R1 RP5R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 157
... Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table 9-14 for peripheral function numbers) © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 R/W-0 RP6R4 RP6R3 RP6R2 U = Unimplemented bit, read as ‘ ...
Page 158
... R/W-0 R/W-0 R/W-0 RP11R4 RP11R3 RP11R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP9R1 RP9R0 bit Bit is unknown R/W-0 R/W-0 RP10R1 RP10R0 bit Bit is unknown R/W-0 R/W-0 RP11R1 RP11R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 159
... Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 9-14 for peripheral function numbers) © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 R/W-0 RP12R4 RP12R3 RP12R2 U = Unimplemented bit, read as ‘ ...
Page 160
... R/W-0 R/W-0 R/W-0 RP17R4 RP17R3 RP17R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP15R1 RP15R0 bit Bit is unknown R/W-0 R/W-0 RP16R1 RP16R0 bit Bit is unknown R/W-0 R/W-0 RP17R1 RP17R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 161
... Unimplemented: Read as ‘0’ bit 4-0 RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table 9-14 for peripheral function numbers) Note 1: RP20 pins are not available on 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 R/W-0 RP18R4 ...
Page 162
... R/W-0 R/W-0 R/W-0 RP23R4 RP23R3 RP23R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 RP21R1 RP21R0 bit Bit is unknown (1) R/W-0 R/W-0 RP22R1 RP22R0 bit Bit is unknown (1) R/W-0 R/W-0 RP23R1 RP23R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 163
... Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 9-14 for peripheral function numbers) Note 1: RP24 pins are not available on 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 R/W-0 RP24R4 ...
Page 164
... PIC18F46J11 FAMILY NOTES: DS39932C-page 164 © 2009 Microchip Technology Inc. ...
Page 165
... PMP Parallel Slave Port (PSP). FIGURE 10-1: PMP MODULE OVERVIEW PIC18 Parallel Master Port © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Key features of the PMP module are: • bits of Addressing when Using Data/Address Multiplexing • Programmable Address Lines • ...
Page 166
... R/W-0 R/W-0 R/W-0 ADRMUX1 ADRMUX0 PTBEEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (Register 10-1 and registers (Register 10-3 and (Register 10-5 and (1) R/W-0 R/W-0 PTWREN PTRDEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 167
... For Master Mode 1 (PMMODEH<1:0> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: This register is only available in 44-pin devices. 2: These bits have no effect when their corresponding pins are used as address lines. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY (2) (2) U-0 R/W-0 — ...
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... Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>) Note 1: This register is only available in 44-pin devices. DS39932C-page 168 R/W-0 R/W-0 R/W-0 INCM1 INCM0 MODE16 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 MODE1 MODE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 169
... Wait Wait Note 1: This register is only available in 44-pin devices. 2: WAITBx and WAITEx bits are ignored whenever WAITM<3:0> = 0000. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 WAITM2 WAITM1 WAITM0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ; multiplexed address phase ...
Page 170
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PTEN4 PTEN3 PTEN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 — — bit Bit is unknown (1) R/W-0 R/W-0 PTEN1 PTEN0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... OB3E:OB0E: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit Output buffer contains data that has not been transmitted Note 1: This register is only available in 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY U-0 R-0 R-0 — ...
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... This option allows users to select either the normal Schmitt Trigger input buffer on digital I/O pins shared with the PMP, or use TTL level compatible buffers instead. Buffer configuration is controlled by the PMPTTL bit in the PADCFG1 register. © 2009 Microchip Technology Inc. ...
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... Value at POR ‘1’ = Bit is set bit 7-0 Parallel Master Port Address: Low Byte<7:0> bits Note 1: In Enhanced Slave mode, PMADDRL functions as PMDOUT1L, one of the Output Data Buffer registers. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY (1) R/W-0 R/W-0 R/W-0 Parallel Master Port Address High Byte<13:8> ...
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... Figure 10-2 displays the connection of the PSP. When chip select is active and a write strobe occurs and (PMCS = 1 and PMWR = 1), the data from PMD<7:0> is captured into the PMDIN1L register. PIC18 Slave PMD<7:0> PMCS PMRD PMWR Address Bus Data Bus Control Lines © 2009 Microchip Technology Inc. ...
Page 175
... PMCS1 PMWR PMRD PMD<7:0> IBF OBE PMPIF © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 10.2.3 READ FROM SLAVE PORT When chip select is active and a read strobe occurs (PMCS = 1 and PMRD = 1), the data from the PMDOUT1L register (PMDOUT1L<7:0>) is presented onto PMD<7:0>. Figure 10-4 provides the timing for the control signals in Read mode ...
Page 176
... IBxF flags. If these flags are not cleared, then there is a risk of hitting an overflow condition. PIC18 Slave Write Read PMD<7:0> Address Address Pointer Pointer PMDOUT1L (0) PMCS PMDOUT1H (1) PMDOUT2L (2) PMRD PMDOUT2H (3) PMWR © 2009 Microchip Technology Inc. PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) ...
Page 177
... ADDR<1:0>. Table 10-1 provides the corresponding FIGURE 10-7: PARALLEL SLAVE PORT READ WAVEFORMS PMCS PMWR PMRD PMD<7:0> PMA<1:0> OBE PMPIF © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 10-1: SLAVE MODE BUFFER ADDRESSING Output PMA<1:0> Register (Buffer) PMDOUT1L (0) 00 ...
Page 178
... When an input buffer is written, the corresponding IBxF bit is set. The IBF flag bit is set when all the buffers are written. If any buffer is already written (IBxF = 1), the next write strobe to that buffer will generate an OBUF event and the byte will be discarded © 2009 Microchip Technology Inc ...
Page 179
... PMAL and PMCSx) can be individually configured as either positive or negative polarity. Configuration is controlled by separate bits in the PMCONL register. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Note that the polarity of control signals that share the same output pin (for example, PMWR and PMENB) are controlled by the same bit ...
Page 180
... Address Bus PMRD Data Bus PMWR Control Lines PMD<7:0> PMA<7:0> PMCS PMALL Address Bus Multiplexed PMRD Data and Address Bus PMWR Control Lines PMD<7:0> PMA<13:8> PMCS PMALL PMALH Multiplexed Data and PMRD Address Bus PMWR Control Lines © 2009 Microchip Technology Inc. ...
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... The first read data byte is placed into the PMDIN1L register, and the second read data is placed into the PMDIN1H. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Note that the read data obtained from the PMDIN1L register is actually the read value from the previous read operation ...
Page 182
... BUSY FIGURE 10-14: READ TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS PMCS1 Address<7:0> PMD<7:0> PMRD PMWR PMALL PMPIF BUSY WAITB<1:0> DS39932C-page 182 Data Data WAITE<1:0> WAITM<3:0> = 0010 © 2009 Microchip Technology Inc. ...
Page 183
... PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMALL PMPIF BUSY WAITB<1:0> FIGURE 10-17: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE PMCS1 PMD<7:0> Address<7:0> PMRD/PMWR PMENB PMALL PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Data Data WAITE<1:0> WAITM<3:0> = 0010 Data ...
Page 184
... READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS1 Address<7:0> PMD<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY FIGURE 10-20: WRITE TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY DS39932C-page 184 Data Address<13:8> Data Address<13:8> Data © 2009 Microchip Technology Inc. ...
Page 185
... WRITE TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS PMCS1 PMD<7:0> PMA<7:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 10-23: READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMBE PMALL PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY LSB MSB LSB MSB LSB MSB ...
Page 186
... PMBE PMALH PMALL PMPIF BUSY FIGURE 10-26: WRITE TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS1 Address<7:0> PMD<7:0> PMWR PMRD PMBE PMALH PMALL PMPIF BUSY DS39932C-page 186 LSB MSB Address<13:8> LSB Address<13:8> LSB MSB MSB © 2009 Microchip Technology Inc. ...
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... EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION PIC18F PMD<7:0> PMALL PMCS PMRD PMWR © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 10.4.1 MULTIPLEXED MEMORY OR PERIPHERAL Figure 10-27 demonstrates the hookup of a memory or another addressable peripheral in Full Multiplex mode. Consequently, this mode achieves the best pin saving from the microcontroller perspective ...
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... PM<7:0> PMA0 PMRD/PMWR PMCS DS39932C-page 188 Parallel EEPROM A<n:0> D<7:0> Parallel EEPROM A<n:1> D<7:0> LCD Controller D<7:0> RS R/W E Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines © 2009 Microchip Technology Inc. ...
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... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. 2: These bits and/or registers are only available in 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Bit 5 Bit 4 Bit 3 ...
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... PIC18F46J11 FAMILY NOTES: DS39932C-page 190 © 2009 Microchip Technology Inc. ...
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... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. Figure 11-1 provides a simplified block diagram of the Timer0 module in 8-bit mode ...
Page 192
... Sync with Internal TMR0L Clocks Delay There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
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... INTCON GIE/GIEH PEIE/GIEL TMR0IE T0CON TMR0ON T08BIT Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
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... PIC18F46J11 FAMILY NOTES: DS39932C-page 194 © 2009 Microchip Technology Inc. ...
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... Note 1: The F clock source should not be selected if the timer will be used with the ECCP capture/compare OSC features. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Figure 12-1 displays a simplified block diagram of the Timer1 module. The module incorporates its own low-power oscillator to provide an additional clocking option. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation ...
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... TMR2 to match PR2 output Note 1: Programming the T1GCON prior to T1CON is recommended. DS39932C-page 196 (T1GCON), R/W-0 R/W-0 R-x T1GVAL T1GSPM T1GGO/T1DONE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 T1GSS1 T1GSS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... ECCP1 and ECCP2 both use Timer3 (capture/compare) and Timer4 (PWM ECCP1 uses Timer1 (compare/capture) and Timer2 (PWM); ECCP2 uses Timer3 (capture/compare) and Timer4 (PWM ECCP1 and ECCP2 both use Timer1 (capture/compare) and Timer2 (PWM) © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R-0 U-0 ...
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... Timer1 is disabled (TMR1ON = 0) when T1CKI is high, then Timer1 is enabled (TMR1ON = 1) when T1CKI is low. T1OSCEN Clock Source (F x Instruction Clock (F x External Clock on T1CKI Pin 0 Oscillator Circuit on T1OSI/T1OSO Pin 1 system clock or they can run Clock Source ) OSC /4) OSC © 2009 Microchip Technology Inc. ...
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... TMR1H T1OSO/T1CKI OUT T1OSC T1OSI EN T1OSCEN T1CKI Note 1: ST Buffer is high-speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY T1GSPM T1G_IN 0 Single Pulse Acq. Control T1GGO/T1DONE CK R TMR1ON ...
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... C1 and C2 for a given crystal. The optimum value depends in part on the amount of parasitic capacitance in the circuit, which is often unknown. Therefore, after values have been selected highly recommended that thorough testing and validation of the oscillator be performed. © 2009 Microchip Technology Inc external ...