DSPIC33FJ12MC201-I/SO Microchip Technology, DSPIC33FJ12MC201-I/SO Datasheet
DSPIC33FJ12MC201-I/SO
Specifications of DSPIC33FJ12MC201-I/SO
Related parts for DSPIC33FJ12MC201-I/SO
DSPIC33FJ12MC201-I/SO Summary of contents
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... Microchip Technology Inc. High-Performance, 16-bit Digital Signal Controllers Preliminary Data Sheet DS70265D ...
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... PICDEM, PICDEM.net, PICtail, PIC Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... FIFO on each capture • Output Compare (up to two channels): - Single or Dual 16-bit Compare mode - 16-bit Glitchless PWM mode © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Interrupt Controller: • 5-cycle latency • available interrupt sources • three external interrupts • Seven programmable priority levels • ...
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... Motor Control Peripherals: • 6-channel 16-bit Motor Control PWM: - Three duty cycle generators - Independent or Complementary mode - Programmable dead time and output polarity - Edge-aligned or center-aligned - Manual output override control - One Fault input - Trigger for ADC conversions - PWM frequency for 16-bit resolution ...
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... PRODUCT FAMILIES The device names, pin counts, memory sizes, and peripheral availability of each device are listed in Table 1. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ12MC201/202 CONTROLLER FAMILIES Device Pins dsPIC33FJ12MC201 dsPIC33FJ12MC202 Note 1: Only two out of three timers are remappable. ...
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... Pin Diagrams 20-PIN SDIP, SOIC, SSOP PGED2/AN0/V PGEC2/AN1/V PGED1/AN2/RP0 PGEC1/AN3/RP1 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 PGED3/SOSCI/RP4 PGEC3/SOSCO/T1CK/CN0/RA4 28-PIN SDIP, SOIC, SSOP PGED2/AN0/V PGEC2/AN1/V PGED1/AN2/RP0 PGEC1/AN3/RP1 AN4/RP2 AN5/RP3 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 PGED3/SOSCI/RP4 PGEC3/SOSCO/T1CK/CN0/RA4 ASDA1/RP5 Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals ...
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... OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 ...
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... Table of Contents dsPIC33FJ12MC201/202 Product Families ........................................................................................................................................... 3 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 11 3.0 CPU............................................................................................................................................................................................ 15 4.0 Memory Organization ................................................................................................................................................................. 27 5.0 Flash Program Memory .............................................................................................................................................................. 53 6.0 Resets ....................................................................................................................................................................................... 59 7.0 Interrupt Controller ..................................................................................................................................................................... 67 8.0 Oscillator Configuration .............................................................................................................................................................. 99 9.0 Power-Saving Features............................................................................................................................................................ 109 10.0 I/O Ports ................................................................................................................................................................................... 115 11 ...
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... Digital Signal Processor (DSP) functionality with a high-performance, 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ12MC201/ 202 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2009 Microchip Technology Inc. ...
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... FIGURE 1-1: dsPIC33FJ12MC201/202 BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCH PCL PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks Power-up Timing OSC2/CLKO ...
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... Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Description External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
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... TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name PPS Type Type I ST Yes FLTA1 O — No PWM1L1 O — No PWM1H1 O — No PWM1L2 O — No PWM1H2 O — No PWM1L3 O — No PWM1H3 I ST Yes FLTA2 O — No PWM2L1 O — No PWM2H1 PGED1 I PGEC1 PGED2 I PGEC2 I ST ...
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... GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 family of devices not intended comprehensive reference complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”, which is available from ...
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... FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION MCLR C dsPIC33F 0.1 µF Ceramic 0.1 µF Ceramic 10 Ω 2.2.1 TANK CAPACITORS On boards with power traces running longer than six inches in length suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should ...
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... User's Guide” DS51616 ® • “Using MPLAB REAL ICE™” (poster) DS51749 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator Configuration” ...
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... Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < F < 8 MHz to comply with device PLL IN start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in the FRC mode first ...
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... Special MCU Features The dsPIC33FJ12MC201/202 features a 17-bit by 17- bit single-cycle multiplier that is shared by both the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using ...
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... FIGURE 3-1: dsPIC33FJ12MC201/202 CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCH PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode & Control Control Signals to Various Blocks DS70265D-page 16 Y Data Bus ...
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... FIGURE 3-2: dsPIC33FJ12MC201/202 PROGRAMMER’S MODEL DSP Operand Registers DSP Address Registers AD39 DSP ACCA Accumulators ACCB PC22 7 0 TBLPAG Data Table Page Address 7 0 PSVPAG 22 DOSTART OAB SAB DA SRH © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 D15 D0 W0/WREG W10 W11 W12/DSP Offset ...
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... CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER R-0 R-0 R/C bit 15 (2) (3) R/W-0 R/W-0 R/W-0 (2) IPL<2:0> bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 OA: Accumulator A Overflow Status bit ...
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... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 (2) Preliminary DS70265D-page 19 ...
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... REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-1 SATA SATB SATDW bit 7 Legend Clear only bit R = Readable bit W = Writable bit 0’ = Bit is cleared ‘x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ ...
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... Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops Note 1: This bit will always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265D-page 21 ...
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... Arithmetic Logic Unit (ALU) The dsPIC33FJ12MC201/202 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts, and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV), and Digit Carry (DC) Status bits in the SR register ...
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... FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill DS70265D-page 23 ...
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... MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value ...
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... If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 3.6.3 ACCUMULATOR ‘WRITE BACK’ The MAC class of instructions (with the exception of MPY, MPY.N, ED, and EDAC) can optionally write a ...
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... Round Logic The round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value that is passed to the data space write saturation logic ...
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... The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory map for the dsPIC33FJ12MC201/202 family of devices is shown in Figure 4-1. dsPIC33FJ12MC201/202 0x000000 GOTO Instruction 0x000002 ...
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... A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. dsPIC33FJ12MC201/202 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs) ...
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... Data Address Space The dsPIC33FJ12MC201/202 CPU has a separate 16- bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space ...
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... FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ12MC201/202 DEVICES WITH 1 KB RAM MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 0x09FF 0x0A01 1 Kbyte SRAM Space 0x0BFF 0x0C01 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70265D-page 30 LSB 16 bits Address MSb LSb ...
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... X data prefetch path for the dual operand DSP instructions (MAC class). © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N, and MSC) to provide two concurrent data read paths ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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... CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A — CN30PUE CN29PUE — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12MC201 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 — ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — ...
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TABLE 4-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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... POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L P1DC1 01D6 P1DC2 01D8 P1DC3 01DA Legend uninitialized bit, — = unimplemented, read as ‘0’ TABLE 4-9: 4-OUTPUT PWM1 REGISTER MAP FOR dsPIC33FJ12MC201 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P1TCON 01C0 PTEN — PTSIDL — ...
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TABLE 4-10: 2-OUTPUT PWM2 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P2TCON 05C0 PTEN — PTSIDL — P2TMR 05C2 PTDIR P2TPER 05C4 — P2SECMP 05C6 SEVTDIR PWM2CON1 05C8 — — — — PWM2CON2 05CA ...
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TABLE 4-13: UART1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — ...
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TABLE 4-15: ADC1 REGISTER MAP FOR dsPIC33FJ12MC202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
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... TABLE 4-16: ADC1 REGISTER MAP FOR dsPIC33FJ12MC201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0300 ADC1BUF0 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ADC1BUFD ...
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TABLE 4-17: PERIPHERAL PIN SELECT INPUT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — — RPINR1 0682 — — — — RPINR3 0686 — — — RPINR7 068E — — — ...
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... TABLE 4-19: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ12MC201 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — — — RPOR2 06C4 — — — — RPOR3 06C6 — — — RPOR4 06C8 — — — RPOR6 06CC — ...
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TABLE 4-23: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> PLLFBD 0746 — — — — OSCTUN 0748 — ...
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... SOFTWARE STACK In addition to its use as a working register, the W15 register in the dsPIC33FJ12MC201/202 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-4 ...
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... Individual instruc- tions may support different subsets of these addressing modes. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the Effective Address (EA). ...
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... MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Preliminary the difference between the © 2009 Microchip Technology Inc. ...
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... The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 4.5.1 BIT-REVERSED ADDRESSING IMPLEMENTATION Bit-Reversed Addressing mode is enabled in any of these situations: • ...
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... TABLE 4-27: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address DS70265D-page 48 Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word, Bit-Reversed Buffer Bit-Reversed Address Decimal Preliminary A0 Decimal © 2009 Microchip Technology Inc. ...
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... Interfacing Program and Data Memory Spaces The dsPIC33FJ12MC201/202 architecture uses a 24- bit-wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces ...
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... Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. DS70265D-page 50 Program Counter 0 23 bits 1/0 TBLPAG 8 bits 24 bits Select 1 0 PSVPAG 8 bits 23 bits Preliminary 0 EA 1/0 16 bits bits Byte Select © 2009 Microchip Technology Inc. ...
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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 • TBLRDH (Table Read High Word mode, this instruction maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’. ...
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... Preliminary 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2009 Microchip Technology Inc. ...
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... Flash memory can be programmed in two ways: • In-Circuit Serial Programming™ (ICSP™) programming capability • Run-Time Self-Programming (RTSP) ICSP allows a dsPIC33FJ12MC201/202 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming ...
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... RTSP Operation The dsPIC33FJ12MC201/202 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions); and to program one row or one word. Table 24-12 shows typical erase and programming times ...
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... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 (1) U-0 U-0 — — (1) ...
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... REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 — — — bit 15 W-0 W-0 W-0 bit 7 Legend Satiable only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY< ...
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... W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 0x55 to NVMKEY. ...
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... EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 MOV W0, NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 MOV W0, TBLPAG MOV #0x6000 Perform the TBLWT instructions to write the latches ...
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... RESETS Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 family of devices not intended comprehensive reference complement the information in this data sheet, refer to the “dsPIC33F Family Ref- erence Manual”, Section 8. “Reset” (DS70192), which is available from the Microchip web site (www.microchip.com). ...
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... REGISTER 6-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...
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... Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 (1) (CONTINUED) Preliminary DS70265D-page 61 ...
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... System Reset The dsPIC33FJ12MC201/202 family of devices have two types of Reset: • Cold Reset • Warm Reset A cold Reset is the result of a POR or a BOR cold Reset, the FNOSC configuration bits in the FOSC device configuration register selects the device clock source ...
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... BOR BOR extension time 100 μs maximum T BOR T Programmable 0-128 ms nominal PWRT power-up time delay 900 μs maximum T Fail-safe Clock FSCM Monitor Delay © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Vbor V BOR T BOR 3 T PWRT T OSCD Reset Time has elapsed. POR ensures the voltage regulator output becomes stable. ...
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... POR A POR circuit ensures the device is reset from power- on. The POR circuit is active until V V threshold and the delay T has elapsed. The POR POR delay T ensures the internal device bias circuits POR become stable. The device supply voltage characteristics must meet ...
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... Refer to “Watchdog Timer (WDT)” for more information on Watchdog Reset. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 6.7 Trap Conflict Reset If a lower-priority hard trap occurs while a higher-prior- ity trap is being processed, a hard trap conflict Reset occurs. The hard traps include exceptions of priority level 13 through level 15, inclusive ...
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... ILLEGAL OPCODE RESET A device Reset is generated if the device attempts to execute an illegal opcode value that is fetched from program memory. The illegal opcode Reset function can prevent the device from executing program memory sections that are used to store constant data. To take advantage of the illegal opcode Reset, use only the lower 16 bits of each program memory section to store the data values ...
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... Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The dsPIC33FJ12MC201/202 device clears its regis- ters in response to a Reset, forcing the PC to zero. The digital signal controller then begins program execution at location 0x000000. A GOTO instruction at the Reset address can redirect program execution to the appropriate start-up routine ...
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... FIGURE 7-1: dsPIC33FJ12MC201/202 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 Interrupt Vector 52 ...
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... Microchip Technology Inc. dsPIC33FJ12MC201/202 AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – Input Capture 2 0x000120 OC2 – ...
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... TABLE 7-1: INTERRUPT VECTORS (CONTINUED) Interrupt Vector Request (IRQ) IVT Address Number Number 54 46 0x000070 55 47 0x000072 56 48 0x000074 57 49 0x000076 58 50 0x000078 59 51 0x00007A 60 52 0x00007C 61 53 0x00007E 62 54 0x000080 63 55 0x000082 64 56 0x000084 65 57 0x000086 66 58 0x000088 67 59 ...
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... Interrupt Control and Status Registers The dsPIC33FJ12MC201/202 devices implement a total of 22 registers for the interrupt controller: • INTCON1 • INTCON2 • IFSx • IECx • IPCx • INTTREG 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the control and status flags for the processor trap sources ...
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... REGISTER 7-1: SR: CPU STATUS REGISTER R-0 R-0 R/C bit 15 (3) (3) R/W-0 R/W-0 R/W-0 (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits ...
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... Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...
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... REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘ ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — U-0 ...
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... REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265D-page 77 ...
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... REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 — — INT2IF bit 15 R/W-0 R/W-0 U-0 IC8IF IC7IF — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IF: External Interrupt 2 Flag Status bit ...
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... Interrupt request has not occurred bit 9 PWM1IF: PWM1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-0 — — QEIIF U-0 ...
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... REGISTER 7-8: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10 FLTA2IF: PWM2 Fault A Interrupt Flag Status bit ...
Page 83
... T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — ...
Page 84
... REGISTER 7-9: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70265D-page 82 Preliminary © 2009 Microchip Technology Inc. ...
Page 85
... MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — U-0 ...
Page 86
... REGISTER 7-11: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 R/W-0 U-0 U-0 FLTA1IE — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 FLTA1IE: PWM1 Fault A Interrupt Enable bit 1 = Interrupt request enabled ...
Page 87
... Interrupt request not enabled bit 8-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-0 — — FLA2IE U-0 U-0 U-0 — ...
Page 88
... REGISTER 7-13: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 89
... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-1 — — ...
Page 90
... REGISTER 7-15: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP<2:0> bit 15 U-0 R/W-1 R/W-0 — SPI1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 91
... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-1 — — — R/W-0 U-0 R/W-1 — ...
Page 92
... REGISTER 7-17: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP<2:0> bit 15 U-0 R/W-1 R/W-0 — MI2C1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 93
... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — ...
Page 94
... REGISTER 7-19: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-1 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — INT2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 95
... PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — ...
Page 96
... REGISTER 7-21: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 R/W-1 R/W-0 — FLTA1IP<2:0> bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 FLTA1IP<2:0>: PWM1 Fault A Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 97
... PWM2IP<2:0>: PWM2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-0 — — R/W-0 U-0 U-0 — ...
Page 98
... REGISTER 7-24: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R-0 R-0 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • ...
Page 99
... ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...
Page 100
... NOTES: DS70265D-page 98 Preliminary © 2009 Microchip Technology Inc. ...
Page 101
... OSCILLATOR CONFIGURATION Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 family of devices not intended comprehensive reference complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”, “Oscillator” (DS70186), available from the Microchip web site (www.microchip.com). ...
Page 102
... The output of the oscillator (or the output of the PLL if a PLL mode has been selected) F generate the device instruction clock (F peripheral clock time base (F operating speed of the device, and speeds MHz are supported by the dsPIC33FJ12MC201/202 architecture. Instruction execution speed or device operating frequency given by: ...
Page 103
... OSC IN ⎝ ⎠ ⋅ FIGURE 8-2: dsPIC33FJ12MC201/202 PLL BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) Note 1: This frequency range must be satisfied at all times. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 For example, suppose a 10 MHz crystal is being used with the selected oscillator mode of XT with PLL. ...
Page 104
... TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Fast RC Oscillator with Divide-by-N (FRCDIVN) Fast RC Oscillator with Divide-by-16 (FRCDIV16) Low-Power RC Oscillator (LPRC) Secondary (Timer1) Oscillator (SOSC) Primary Oscillator (HS) with PLL (HSPLL) Primary Oscillator (XT) with PLL (XTPLL) Primary Oscillator (EC) with PLL (ECPLL) ...
Page 105
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 (1) R-0 U-0 R/W-y — ...
Page 106
... REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70227) in the “ ...
Page 107
... PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 00000 = Input/2 (default) 00001 = Input/3 • • • 11111 = Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE< ...
Page 108
... REGISTER 8-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) ...
Page 109
... Center frequency -12% (6.49 MHz) Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — ...
Page 110
... Clock Switching Operation Applications are free to switch among any of the four clock sources (Primary, LP, FRC, and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ12MC201/202 devices have a safeguard lock built into the switch process. Note: Primary Oscillator mode has three different submodes (XT, HS, and EC), which are determined by the POSCMD< ...
Page 111
... Clock Frequency and Clock Switching dsPIC33FJ12MC201/202 devices allow a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits (OSCCON< ...
Page 112
... IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions • The WDT is automatically cleared • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “ ...
Page 113
... ADC1 module is enabled Note 1: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 T2MD ...
Page 114
... REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 R/W-0 R/W-0 U-0 IC8MD IC7MD — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 IC8MD: Input Capture 8 Module Disable bit ...
Page 115
... Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4 PWM2MD: PWM2 Module Disable bit 1 = PWM2 module is disabled 0 = PWM2 module is enabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 PWM2MD — ...
Page 116
... NOTES: DS70265D-page 114 Preliminary © 2009 Microchip Technology Inc. ...
Page 117
... I/O PORTS Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 family of devices not intended comprehensive reference complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”, Section 30. “I/O Ports with Peripheral Pin Select” (DS70190), which is Microchip web site (www ...
Page 118
... DS70265D-page 116 10.3 Input Change Notification The input change notification function of the I/O ports allows the dsPIC33FJ12MC201/202 devices to gener- ate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled. Depending on the device ...
Page 119
... The association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 10.4.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it will be mapped to ...
Page 120
... TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name External Interrupt 1 External Interrupt 2 Timer2 External Clock Timer3 External Clock Input Capture 1 Input Capture 2 Input Capture 7 Input Capture 8 Output Compare Fault A PWM1 Fault PWM2 Fault QEI1 Phase A QEI1 Phase B QEI1 Index ...
Page 121
... CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. dsPIC33FJ12MC201/202 devices include three features to prevent alterations to the peripheral map: • Control register lock sequence • Continuous state monitoring • Configuration bit pin select lock 10 ...
Page 122
... REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 INT1R< ...
Page 123
... INTR2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 INT2R<4:0> ...
Page 124
... REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T3CKR< ...
Page 125
... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 R/W-1 IC1R<4:0> Unimplemented bit, read as ‘0’ ...
Page 126
... REGISTER 10-5: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC8R< ...
Page 127
... FLTA1R<4:0>: Assign PWM1 Fault (FLTA1) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 OCFAR<4:0> ...
Page 128
... REGISTER 10-8: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 FLTA2R< ...
Page 129
... QEA1R<4:0>: Assign A (QEA) to the corresponding pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 R/W-1 R/W-1 QEB1R<4:0> R/W-1 R/W-1 R/W-1 QEA1R<4:0> Unimplemented bit, read as ‘0’ ...
Page 130
... REGISTER 10-10: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 INDX1R< ...
Page 131
... U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ...
Page 132
... REGISTER 10-12: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 SCK1R< ...
Page 133
... SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 SS1R< ...
Page 134
... REGISTER 10-14: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP1R< ...
Page 135
... RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 10-2 for peripheral function numbers) © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 RP5R<4:0> R/W-0 R/W-0 R/W-0 RP4R< ...
Page 136
... REGISTER 10-18: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP9R< ...
Page 137
... RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 10-2 for peripheral function numbers) © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 RP13R<4:0> R/W-0 R/W-0 R/W-0 RP12R< ...
Page 138
... NOTES: DS70265D-page 136 Preliminary © 2009 Microchip Technology Inc. ...
Page 139
... TIMER1 Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 family of devices not intended comprehensive reference complement the information in this data sheet, refer to the “dsPIC33F Family Ref- erence Manual”, Section 11. “Timers” (DS70205), which is available from the Microchip web site (www.microchip.com). ...
Page 140
... REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...
Page 141
... TIMER2/3 FEATURE Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 family of devices not intended comprehensive reference complement the information in this data sheet, refer to the “dsPIC33F Family Ref- erence Manual”, Section 11. “Timers” (DS70205), which is available from the Microchip web site (www.microchip.com). ...
Page 142
... FIGURE 12-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T3IF 0 (2) ADC Event Trigger Equal MSb Reset Read TMR2 Write TMR2 Data Bus<15:0> Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
Page 143
... FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70265D-page 141 ...
Page 144
... REGISTER 12-1: T2CON CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer2 On bit When T32 = Starts 32-bit Timer2 Stops 32-bit Timer2/3 ...
Page 145
... Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (T2CON<3>) register, these bits have no effect. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 (1) — ...
Page 146
... NOTES: DS70265D-page 144 Preliminary © 2009 Microchip Technology Inc. ...
Page 147
... Microchip (www.microchip.com). The Input Capture module is useful in applications requiring frequency (period) and pulse measurement. The dsPIC33FJ12MC201/202 devices support up to eight input capture channels. The Input Capture module captures the 16-bit value of the selected Time Base register when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: 1 ...
Page 148
... Input Capture Registers REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 149
... OUTPUT COMPARE Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 family of devices not intended comprehensive reference complement the information in this data sheet, refer to the “dsPIC33F Family Ref- erence Manual”, Section 13. “Output Compare” (DS70209), which is available on the Microchip (www ...
Page 150
... Output Compare Modes Configure the Output Compare modes by setting the appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OCxCON<2:0>) register. Table 14-1 lists the different bit settings for the Output Compare modes. Figure 14-2 illustrates the output compare operation for various modes ...
Page 151
... TMRy OCxR Active-Low One-Shot (OCM = 001) Active-High One-Shot (OCM = 010) Toggle Mode (OCM = 011) Delayed One-Shot (OCM = 100) Continuous Pulse Mode (OCM = 101) PWM Mode (OCM = 110 or 111) © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Timer is reset on period match Preliminary DS70265D-page 149 ...
Page 152
... REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER U-0 U-0 R/W-0 — — OCSIDL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Cleared in Hardware R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 153
... Reference Manual”, Section 14. “Motor Control PWM” (DS70187), which is available from the Microchip web site (www.microchip.com). The dsPIC33FJ12MC201/202 device supports up to two dedicated Pulse Width Modulation (PWM) modules. The PWM1 module is a 6-channel PWM generator, and the PWM2 module is a 2-channel PWM generator ...
Page 154
... FIGURE 15-1: 6-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM1) PWM1CON1 PWM Enable and Mode SFRs PWM1CON2 P1DTCON1 Dead-Time Control SFRs P1DTCON2 Fault Pin Control SFRs P1FLTACON PWM Manual P1OVDCON Control SFR P1TMR Comparator P1TPER P1TPER Buffer P1TCON Comparator P1SECMP PWM Time Base Note: Details of PWM Generator 1 and 2 not shown for clarity ...
Page 155
... P2FLTACON PWM Manual P2OVDCON Control SFR P2TMR Comparator P2TPER P2TPER Buffer P2TCON Comparator P2SECMP PWM Time Base © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 PWM Generator 1 P2DC1Buffer P2DC1 Comparator Channel 1 Dead-Time Generator and Override Logic Special Event Postscaler SEVTDIR PTDIR Preliminary PWM2H1 ...
Page 156
... REGISTER 15-1: PxTCON: PWM TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 PTEN — PTSIDL bit 15 R/W-0 R/W-0 R/W-0 PTOPS<3:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PTEN: PWM Time Base Timer Enable bit 1 = PWM time base is on ...
Page 157
... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-0 PTPER<14:0>: PWM Time Base Period Value bits © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 PTMR<14:8> R/W-0 R/W-0 R/W-0 PTMR<7:0> Unimplemented bit, read as ‘0’ ...
Page 158
... REGISTER 15-4: PxSECMP: SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 (1) SEVTDIR bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SEVTDIR: Special Event Trigger Time Base Direction bit Special Event Trigger will occur when the PWM time base is counting down ...
Page 159
... Note 1: Reset condition of the PENxH and PENxL bits depends on the value of the PWMPIN Configuration bit in the FPOR Configuration register. 2: PWM2 supports only one PWM I/O pin pair. PWM1 on dsPIC33FJ12MC201 devices supports only two PWM I/O pin pairs. © 2009 Microchip Technology Inc. ...
Page 160
... REGISTER 15-6: PWMxCON2: PWM CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits 1111 = 1:16 postscale • ...
Page 161
... Clock period for Dead-Time Unit Clock period for Dead-Time Unit Clock period for Dead-Time Unit Clock period for Dead-Time Unit bit 5-0 DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 DTB<5:0> R/W-0 R/W-0 R/W-0 DTA< ...
Page 162
... REGISTER 15-8: PxDTCON2: DEAD-TIME CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — DTS3A bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5 DTS3A: Dead-Time Select for PWM3 Signal Going Active bit ...
Page 163
... PWMxH2/PWMxL2 pin pair is not controlled by Fault Input A bit 0 FAEN1: Fault Input A Enable bit 1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A Note 1: PWM2 supports only one PWM I/O pin pair. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 (1) R/W-0 R/W-0 R/W-0 FAOV3L FAOV2H ...
Page 164
... REGISTER 15-10: PxOVDCON: OVERRIDE CONTROL REGISTER U-0 U-0 R/W-1 — — POVD3H bit 15 U-0 U-0 R/W-0 — — POUT3H bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 POVDxH<3:1>:POVDxL<3:1>: PWM Output Override bits ...
Page 165
... R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC3<15:0>: PWM Duty Cycle 3 Value bits © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 PDC1<15:8> R/W-0 R/W-0 R/W-0 PDC1<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 166
... NOTES: DS70265D-page 164 Preliminary © 2009 Microchip Technology Inc. ...
Page 167
... QUADRATURE ENCODER INTERFACE (QEI) MODULE Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 family of devices not intended comprehensive reference complement the information in this data sheet, refer to the “dsPIC33F Family Ref- erence Manual”, Section 15. “Quadrature Encoder Interface (QEI)” (DS70208), which is available from the Microchip web site (www ...
Page 168
... REGISTER 16-1: QEIxCON: QEI CONTROL REGISTER R/W-0 U-0 R/W-0 CNTERR — QEISIDL bit 15 R/W-0 R/W-0 R/W-0 SWPAB PCDOUT TQGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CNTERR: Count Error Status Flag bit 1 = Position count error has occurred ...
Page 169
... UPDN_SRC: Position Counter Direction Selection Control bit 1 = QEB pin state defines position counter direction 0 = Control/Status bit, UPDN (QEICON<11>), defines timer counter (POSCNT) direction Note: When configured for QEI mode, control bit is a ‘don’t care’. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265D-page 167 ...
Page 170
... REGISTER 16-2: DFLTxCON: DIGITAL FILTER CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 QEOUT QECK<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 IMV<1:0>: Index Match Value bits – These bits allow the user application to specify the state of the QEA and QEB input pins during an Index pulse when the POSxCNT register reset ...
Page 171
... SERIAL PERIPHERAL INTERFACE (SPI) Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 family of devices not intended comprehensive reference complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”, Section 18. “Serial Peripheral Interface (SPI)” (DS70206), which is available on the Microchip web site (www ...
Page 172
... REGISTER 17-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 SPIEN — SPISIDL bit 15 U-0 R/C-0 U-0 — SPIROV — bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPIx Enable bit ...
Page 173
... Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 DISSCK ...
Page 174
... REGISTER 17-2: SPI CON1: SPIx CONTROL REGISTER 1 (CONTINUED) X bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode Primary prescale 1 Primary prescale 4:1 ...
Page 175
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — ...
Page 176
... NOTES: DS70265D-page 174 Preliminary © 2009 Microchip Technology Inc. ...
Page 177
... INTER-INTEGRATED CIRCUIT™ C™) Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 family of devices not intended comprehensive reference complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”, Section 19. “Inter- 2 Integrated Circuit™ (I C™)” (DS70195), which is available on the Microchip web site (www ...
Page 178
... FIGURE 18-1: I C™ BLOCK DIAGRAM ( Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS70265D-page 176 = 1) X I2CxRCV I2CxRSR LSb Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation ...
Page 179
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
Page 180
... REGISTER 18-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I Value that will be transmitted when the software initiates an Acknowledge sequence Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit 2 (when operating master, applicable during master receive Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit ...
Page 181
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/C-0 HS — — R/C-0 HSC ...
Page 182
... REGISTER 18-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating Read – ...
Page 183
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — ...
Page 184
... NOTES: DS70265D-page 182 Preliminary © 2009 Microchip Technology Inc. ...
Page 185
... UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 family of devices not intended comprehensive reference complement the information in this data sheet, refer to the “dsPIC33F Family Ref- erence Manual”, Section 17. “UART” (DS70188), which is available on the Microchip web site (www ...
Page 186
... REGISTER 19-1: UxMODE: UART R/W-0 U-0 R/W-0 (1) UARTEN — USIDL bit 15 R/W-0 HC R/W-0 R/W-0 HC WAKE LPBACK ABAUD bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> ...
Page 187
... Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 MODE REGISTER (CONTINUED) x Preliminary ...
Page 188
... REGISTER 19-2: U STA: UART x R/W-0 R/W-0 R/W-0 UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL<1:0> ADDEN bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use ...
Page 189
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on enabling the UART module for transmit operation. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 STATUS AND CONTROL REGISTER (CONTINUED) x Preliminary DS70265D-page 187 ...
Page 190
... NOTES: DS70265D-page 188 Preliminary © 2009 Microchip Technology Inc. ...
Page 191
... Section 28. “Analog-to-Digital Converter (ADC) without DMA” (DS70210), which is available on the Microchip web site (www.microchip.com). The dsPIC33FJ12MC201/202 devices have up to six ADC module input channels. The AD12B bit (ADxCON1<10>) allows each of the ADC modules to be configured as either a 10-bit, 4- sample-and-hold ADC (default configuration 12-bit, 1 sample-and-hold ADC ...
Page 192
... FIGURE 20-1: ADC1 BLOCK DIAGRAM FOR dsPIC33FJ12MC201 DEVICES AN0 AN3 CHANNEL SCAN CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 V - REF CH0NA CH0NB AN0 AN3 CH123SA CH123SB (2) CH1 V - REF CH123NA CH123NB AN1 CH123SA CH123SB (2) CH2 V - REF CH123NA CH123NB AN2 CH123SA CH123SB (2) CH3 V - REF ...
Page 193
... AN2 AN5 CH123SA CH123SB (2) CH3 V - REF CH123NA CH123NB Alternate Input Selection Note inputs can be multiplexed with other analog inputs. REF REF 2: Channels 1, 2, and 3 are not applicable for the 12-bit mode of operation. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary (1) ( ...
Page 194
... FIGURE 20-3: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADC Internal (2) RC Clock T CY OSC ( Note 1: Refer to Figure 8-2 for the derivation the clock frequency. T OSC 2: See the ADC Electrical Characteristics for the exact RC clock value. DS70265D-page 192 ADxCON3<5:0> 6 ADC Conversion Clock Multiplier ...
Page 195
... SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or Samples CH0 and CH1 simultaneously (when CHPS<1:0> Samples multiple channels individually in sequence © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 — — U-0 R/W-0 — ...
Page 196
... REGISTER 20-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion. SAMP bit is auto-set Sampling begins when SAMP bit is set bit 1 SAMP: ADC Sample Enable bit 1 = ADC sample-and-hold amplifiers are sampling 0 = ADC sample-and-hold amplifiers are holding If ASAM = 0, software can write ‘ ...
Page 197
... Always starts filling buffer from the beginning bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 — — R/W-0 R/W-0 SMPI< ...
Page 198
... REGISTER 20-3: AD1CON3: ADC1 CONTROL REGISTER 3 R/W-0 U-0 U-0 ADRC — — bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from system clock bit 14-13 Unimplemented: Read as ‘ ...
Page 199
... Reserved 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V bit 8 CH123SB: Channel Positive Input Select for Sample B bit dsPIC33FJ12MC201 devices only: If AD12B = Reserved 0 = Reserved If AD12B = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected ...
Page 200
... Reserved 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V bit 0 CH123SA: Channel Positive Input Select for Sample A bit dsPIC33FJ12MC201 devices only: If AD12B = Reserved 0 = Reserved If AD12B = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected ...