IC DSPIC MCU/DSP 24K 18SOIC

DSPIC30F3012-30I/SO

Manufacturer Part NumberDSPIC30F3012-30I/SO
DescriptionIC DSPIC MCU/DSP 24K 18SOIC
ManufacturerMicrochip Technology
SeriesdsPIC™ 30F
DSPIC30F3012-30I/SO datasheets
 

Specifications of DSPIC30F3012-30I/SO

Program Memory TypeFLASHProgram Memory Size24KB (8K x 24)
Package / Case18-SOIC (7.5mm Width)Core ProcessordsPIC
Core Size16-BitSpeed30 MIPs
ConnectivityI²C, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number Of I /o12Eeprom Size1K x 8
Ram Size2K x 8Voltage - Supply (vcc/vdd)2.5 V ~ 5.5 V
Data ConvertersA/D 8x12bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CProductDSCs
Data Bus Width16 bitProcessor SeriesDSPIC30F
CoredsPICMaximum Clock Frequency30 MHz
Number Of Programmable I/os12Data Ram Size2 KB
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPICDevelopment Tools By SupplierPG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature- 40 CPackage18SOIC W
Device CoredsPICFamily NamedsPIC30
Maximum Speed30 MHzOperating Supply Voltage3.3|5 V
Interface TypeI2C/SPI/UARTOn-chip Adc8-chx12-bit
Number Of Timers3Lead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithXLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEOther namesDSPIC30F301230ISO
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dsPIC30F2011/2012/3012/3013
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
© 2010 Microchip Technology Inc.
DS70139G

DSPIC30F3012-30I/SO Summary of contents

  • Page 1

    ... Microchip Technology Inc. High-Performance, 16-bit Digital Signal Controllers Data Sheet DS70139G ...

  • Page 2

    ... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

  • Page 3

    ... All DSP instructions are single cycle - Multiply-Accumulate (MAC) operation • Single-cycle ±16 shift © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Peripheral Features: • High-current sink/source I/O pins: 25 mA/25 mA • Three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • ...

  • Page 4

    ... Sensor Family Program Memory Device Pins Bytes Instructions dsPIC30F2011 18 12K 4K dsPIC30F3012 18 24K 8K dsPIC30F2012 28 12K 4K dsPIC30F3013 28 24K 8K Pin Diagrams 18-Pin PDIP and SOIC EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin PDIP and SOIC EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin SPDIP and SOIC ...

  • Page 5

    ... Pin Diagrams (1) 28-Pin QFN-S AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 OSC1/CLKI OSC2/CLKO/RC15 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 dsPIC30F2011 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 15 externally. SS DS70139G-page 5 ...

  • Page 6

    ... Pin Diagrams (1) 28-Pin QFN-S AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5 OSC1/CLKI OSC2/CLKO/RC15 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V DS70139G-page AN8/OC1/RB8 2 20 AN9/OC2/RB9 3 19 CN17/RF4 dsPIC30F2012 4 CN18/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 15 externally. SS © 2010 Microchip Technology Inc. ...

  • Page 7

    ... Pin Diagram (1) 44-Pin QFN PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 dsPIC30F3012 OSC2/CLKO/RC15 32 OSC1/CLKI AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 externally. SS DS70139G-page 7 ...

  • Page 8

    ... Pin Diagrams (1) 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 AN9/OC2/RB9 AN8/OC1/RB8 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V DS70139G-page dsPIC30F3013 OSC2/CLKO/RC15 OSC1/CLKI AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 NC AN2/SS1/LVDIN/CN4/RB2 externally. SS © 2010 Microchip Technology Inc. ...

  • Page 9

    ... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 to receive the most current information on all of our products. DS70139G-page 9 ...

  • Page 10

    ... NOTES: DS70139G-page 10 © 2010 Microchip Technology Inc. ...

  • Page 11

    ... MCU and DSC Programmer’s Reference (DS70157). This data sheet contains information specific to the dsPIC30F2011, dsPIC30F2012, dsPIC30F3012 and dsPIC30F3013 Digital Signal Controllers (DSC). These devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture. ...

  • Page 12

    ... PORTB Reg Array Decode PORTC 16 16 DSP Divide Engine Unit ALU<16> PORTD Input Output 2 Compare I C™ Module SPI1 UART1 EMUD3/AN0/V +/CN2/RB0 REF EMUC3/AN1/V -/CN3/RB1 REF AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 AN6/SCK1/INT0/OCFA/RB6 EMUD2/AN7/OC2/IC2/INT2/RB7 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15 EMUC2/OC1/IC1/INT1/RD0 © 2010 Microchip Technology Inc. ...

  • Page 13

    ... Oscillator OSC1/CLKI Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low-Voltage Detect 12-bit ADC Capture Module © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 X Data Bus Data Latch Data Latch Y Data X Data 16 RAM RAM (512 bytes) (512 bytes) 16 Address Address Latch Latch 16 16 ...

  • Page 14

    ... FIGURE 1-3: dsPIC30F3012 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCH PCU Program Counter Stack Address Latch Control Logic Program Memory (24 Kbytes) Data EEPROM (1 Kbytes) 16 Data Latch ROM Latch 24 16 Instruction Decode & ...

  • Page 15

    ... Timer Timing Oscillator OSC1/CLKI Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low-Voltage Detect 12-bit ADC Capture Module © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 X Data Bus Data Latch Data Latch X Data Y Data 16 RAM RAM (1 Kbytes) (1 Kbytes) 16 Address Address Latch Latch RAGU ...

  • Page 16

    ... PORTB is a bidirectional I/O port. PORTC is a bidirectional I/O port. PORTD is a bidirectional I/O port. PORTF is a bidirectional I/O port. Synchronous serial clock input/output for SPI1. SPI1 Data In. SPI1 Data Out. SPI1 Slave Synchronization. Analog = Analog input Output Power © 2010 Microchip Technology Inc. ...

  • Page 17

    ... CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Synchronous serial clock input/output for I Synchronous serial data input/output for I 32 kHz low-power oscillator crystal output. 32 kHz low-power oscillator crystal input. ST buffer when configured in RC mode ...

  • Page 18

    ... NOTES: DS70139G-page 18 © 2010 Microchip Technology Inc. ...

  • Page 19

    ... Each data word consists of 2 bytes and most instructions can address data either as words or bytes. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Two ways to access data in program memory are: • The upper 32 Kbytes of data space memory can ...

  • Page 20

    ... DSP Adder/Subtracter Status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) Status bit. 2.2.3 PROGRAM COUNTER The program counter is 23 bits wide; bit 0 is always clear. Therefore, the PC can address instruction words. DSC devices contain a software stack. modified by exception for SR layout. © 2010 Microchip Technology Inc. ...

  • Page 21

    ... AD39 DSP ACCA Accumulators ACCB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write-Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 ...

  • Page 22

    ... The REPEAT loop count must be setup for 18 iterations of the DIV/DIVF instruction. Thus, a complete divide operation requires 19 cycles. Note: The divide flow is interruptible; however, the user needs to save the context as appropriate. Function © 2010 Microchip Technology Inc. of execution (REPEAT ...

  • Page 23

    ... No change in A MOVSAC • y MPY A = – x • y MPY – x • y MSC © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The DSP engine has several options selected through various bits in the CPU Core Configuration register (CORCON), which are: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...

  • Page 24

    ... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70139G-page 24 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2010 Microchip Technology Inc. ...

  • Page 25

    ... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled through the barrel shifter prior to accumulation. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.2.1 The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true or complement data into the other input ...

  • Page 26

    ... Note that for the MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding Register Indirect with (subject to data saturation, see Saturation”). © 2010 Microchip Technology Inc. ...

  • Page 27

    ... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...

  • Page 28

    ... NOTES: DS70139G-page 28 © 2010 Microchip Technology Inc. ...

  • Page 29

    ... TBLPAG<7> to determine user or configu- ration space access. In Table 3-1, Program Space Address Construction, bit 23 allows access to the Device ID, the User ID and the Configuration bits. Otherwise, bit 23 is always clear. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Manual” for the Table 3-1. Note ...

  • Page 30

    ... F7FFFE F80000 F8000E F80010 FEFFFE FF0000 FFFFFE dsPIC30F3012/3013 Reset - GOTO Instruction 000000 Reset - Target Address 000002 000004 Interrupt Vector Table Vector Tables 00007E Reserved 000080 Alternate Vector Table 000084 0000FE 000100 User Flash ...

  • Page 31

    ... Program 0 Space Visibility Using 1/0 Table Instruction User/ Configuration Space Select Note: Program space visibility cannot be used to access bits <23:16> word in program memory. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select 1 ...

  • Page 32

    ... The destination byte will always when byte select = 1. 4. TBLWTH: Table Write High (refer to “Flash Program Memory” Programming TBLRDL.W TBLRDL.B (Wn<0> Section 5.0 for details on Flash Section 5.0 for details on Flash 0 TBLRDL.B (Wn<0> © 2010 Microchip Technology Inc. ...

  • Page 33

    ... The upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157) for details on instruction encoding. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 TBLRDH TBLRDH.B (Wn< ...

  • Page 34

    ... W0 ; Access program memory location ; using a data space access Note 1: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address. DS70139G-page 34 Program Space 0x0000 (1) PSVPAG 0x00 8 0x8000 23 15 Address Concatenation 15 23 0xFFFF 0x000000 0 0x001200 0x001FFF Data Read © 2010 Microchip Technology Inc. ...

  • Page 35

    ... W8 and W9. Both address spaces are concurrently accessed only with the MAC class instructions. The data space memory map for the dsPIC30F2011 and dsPIC30F2012 is shown in space memory map for the dsPIC30F3012 and dsPIC30F3013 is shown in 16 bits MSB LSB SFR Space ...

  • Page 36

    ... FIGURE 3-7: dsPIC30F3012/3013 DATA SPACE MEMORY MAP MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 0x0BFF 2 Kbyte 0x0C01 SRAM Space 0x0FFF 0x1001 0x1FFF 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70139G-page 36 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE ...

  • Page 37

    ... FIGURE 3-8: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 UNUSED Y SPACE UNUSED MAC Class Ops (Read) Indirect EA using W8, W9 ...

  • Page 38

    ... FIGURE 3-9: MSB 15 0001 Byte 1 Byte 3 0003 0x0000 Byte 5 0x0000 0005 0x0000 backward compatibility with DATA ALIGNMENT LSB 0000 Byte 0 Byte 2 0002 Byte 4 0004 © 2010 Microchip Technology Inc. ...

  • Page 39

    ... MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note push during exception processing concatenates the SRL register to the MSB of the PC prior to the push. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 FIGURE 3-10: 0x0000 15 000000000 There is a Stack Pointer Limit register (SPLIM) ...

  • Page 40

    TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 ...

  • Page 41

    TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN ...

  • Page 42

    ... NOTES: DS70139G-page 42 © 2010 Microchip Technology Inc. ...

  • Page 43

    ... Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...

  • Page 44

    ... As these buffers satisfy the Start and the end address criteria, they can operate in a Bidirectional mode (i.e., address boundary checks are performed on both the lower and upper address boundaries). buffers), or end address © 2010 Microchip Technology Inc. ...

  • Page 45

    ... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control registers: register, MODCON<15:0>, contains enable flags as well register field to specify the W address registers ...

  • Page 46

    ... If Bit-Reversed Addressing has already been enabled by setting the BREN bit (XBREV<15>), then a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. © 2010 Microchip Technology Inc. N bytes, be enabled ...

  • Page 47

    ... TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 1024 512 256 128 © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Sequential Address Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value ...

  • Page 48

    ... NOTES: DS70139G-page 48 © 2010 Microchip Technology Inc. ...

  • Page 49

    ... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 5.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...

  • Page 50

    ... NVMKEY register. Refer to “Programming Operations” DD Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. © 2010 Microchip Technology Inc. Section 5.6 for further details. ...

  • Page 51

    ... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, the ...

  • Page 52

    ... Write PM high byte into program latch ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2010 Microchip Technology Inc. Example 5-3. ...

  • Page 53

    TABLE 5-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — Legend: ...

  • Page 54

    ... NOTES: DS70139G-page 54 © 2010 Microchip Technology Inc. ...

  • Page 55

    ... A word write operation should be preceded by an erase of the corresponding memory location(s). The write typically requires complete, but the write time varies with voltage and temperature. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 A program or erase operation on the data EEPROM does not stop the instruction flow. The user is ...

  • Page 56

    ... Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence Example 6-3. ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence © 2010 Microchip Technology Inc. ...

  • Page 57

    ... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The write does not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...

  • Page 58

    ... EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. © 2010 Microchip Technology Inc. ...

  • Page 59

    ... WR TRIS WR LAT + WR Port Read LAT Read Port © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins and writes to the port pins, write the latch (LATx). Any bit and its associated data and Control registers that are not valid for a particular device are disabled ...

  • Page 60

    ... Typically this instruction have their would be a NOP EXAMPLE 7-1: MOV #0xF0, W0 MOV W0, TRISB NOP btss PORTB, #7 PORT WRITE/READ EXAMPLE ; Configure PORTB<7:4> inputs ; and PORTB<3:0> as outputs ; additional instruction cycle ; bit test RB7 and skip if set © 2010 Microchip Technology Inc. ...

  • Page 61

    TABLE 7-1: PORTB REGISTER MAP FOR dsPIC30F2011/3012 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C6 — — — — PORTB 02C8 — — — — LATB 02CB — — — — Legend: — = unimplemented ...

  • Page 62

    TABLE 7-5: PORTD REGISTER MAP FOR dsPIC30F2012/3013 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISD 02D2 — — — — PORTD 02D4 — — — — LATD 02D6 — — — — Legend: — = unimplemented ...

  • Page 63

    ... CN7PUE CN6PUE CNPU2 00C6 — — Legend: — = unimplemented bit, read as ‘0’ Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Bit 5 Bit 4 Bit 3 Bit 2 CN5IE CN4IE CN3IE CN2IE — ...

  • Page 64

    ... NOTES: DS70139G-page 64 © 2010 Microchip Technology Inc. ...

  • Page 65

    ... The current CPU priority level is explicitly stored in the IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS register (SR) in the processor core. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers ...

  • Page 66

    ... UART2 Transmitter 26-41 34-49 Reserved 42 50 LVD – Low-Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority Note 1: Only the dsPIC30F3013 has UART2 and the U2RX, U2TX interrupts. These locations are reserved for the dsPIC30F2011/2012/3012. © 2010 Microchip Technology Inc. ...

  • Page 67

    ... A momentary dip in the power supply to the device has been detected which may result in malfunction. • Trap Lockout: Occurrence of multiple trap conditions simultaneously causes a Reset. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 8.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere ...

  • Page 68

    ... The device is automatically Reset in a hard trap conflict condition. The TRAPR Status bit (RCON<15>) is set when the Reset occurs, so that the condition may be detected in software. © 2010 Microchip Technology Inc. ...

  • Page 69

    ... The processor then loads the priority level for this interrupt into the STATUS register. This action disables all lower priority interrupts until the completion of the Interrupt Service Routine (ISR). © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 FIGURE 8-2: 0x000000 0x0000 ...

  • Page 70

    ... If an enabled interrupt request of sufficient priority is received by the interrupt controller, then the standard interrupt request is presented to the processor. At the same time, the processor wakes up from Sleep or Idle and begins execution of the ISR needed to process the interrupt request. © 2010 Microchip Technology Inc. ...

  • Page 71

    TABLE 8-2: dsPIC30F2011/2012/3012 INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ...

  • Page 72

    TABLE 8-3: dsPIC30F3013 INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ...

  • Page 73

    ... TGATE SOSCO/ T1CK LPOSCEN SOSCI © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer increments on every instruction cycle match value preloaded into the Period register PR1, then resets to ‘ ...

  • Page 74

    ... When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt is generated if enabled. The T1IF bit must be cleared in software. The respective Timer interrupt flag, T1IF, is located in the IFS0 register in the interrupt controller. © 2010 Microchip Technology Inc. SOSCI dsPIC30FXXXX SOSCO ...

  • Page 75

    ... Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T1IE. The timer interrupt enable bit is located in the IEC0 Control register in the interrupt controller. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139G-page 75 ...

  • Page 76

    TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note: Refer ...

  • Page 77

    ... Interrupt on a 32-bit period register match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 For 32-bit timer/counter operation, Timer2 is the ls word and Timer3 is the ms word of the 32-bit timer. ...

  • Page 78

    ... Timer Configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70139G-page TMR3 TMR2 MSB LSB Comparator x 32 PR3 PR2 TGATE (T2CON<6> Gate Sync ’ for a 32-bit timer/counter operation. All control 1 Sync TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2010 Microchip Technology Inc. ...

  • Page 79

    ... TIMER2 BLOCK DIAGRAM Equal Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 PR2 Comparator x 16 TMR2 TGATE Gate Sync PR3 Comparator x 16 TMR3 ...

  • Page 80

    ... T3IF bit (IFS0<7>) is asserted and an interrupt is generated if enabled. In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T3IE (IEC0<7>). © 2010 Microchip Technology Inc. can generate an ...

  • Page 81

    TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...

  • Page 82

    ... NOTES: DS70139G-page 82 © 2010 Microchip Technology Inc. ...

  • Page 83

    ... ICxCON Data Bus Note 1: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channel (1 or 2). © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 These operating modes are determined by setting the appropriate bits in the IC1CON and IC2CON registers. The dsPIC30F2011/2012/3012/3013 devices have two capture channels ...

  • Page 84

    ... Each channel provides an interrupt flag (ICxIF) bit. The respective capture channel interrupt flag is located in the corresponding IFSx register. Enabling an interrupt is accomplished via the respective capture channel interrupt enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IEC Control register. © 2010 Microchip Technology Inc. satisfied. defined as ...

  • Page 85

    TABLE 11-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — Legend uninitialized bit; — = ...

  • Page 86

    ... NOTES: DS70139G-page 86 © 2010 Microchip Technology Inc. ...

  • Page 87

    ... Timer Module TMR2<15:0 TMR3<15:0> Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channel (1 or 2). © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The key operational features of the output compare module include: • Timer2 and Timer3 Selection mode • ...

  • Page 88

    ... Fault condition has occurred. This state is maintained until both of the following events have occurred: • The external Fault condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits © 2010 Microchip Technology Inc. ...

  • Page 89

    ... PWM OUTPUT TIMING Duty Cycle TMR3 = PR3 T3IF = 1 (Interrupt Flag) OCxR = OCxRS © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • TMRx is cleared. • The OCx pin is set. ...

  • Page 90

    ... IFS0 register and must be cleared in software. The interrupt is enabled via the respective timer interrupt enable bit (T2IE or T3IE) located in the IEC0 Control register. The output compare interrupt flag is never set during the PWM mode of operation. © 2010 Microchip Technology Inc. ...

  • Page 91

    TABLE 12-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — Legend: ...

  • Page 92

    ... NOTES: DS70139G-page 92 © 2010 Microchip Technology Inc. ...

  • Page 93

    ... SDI1 (serial data input) • SDO1 (serial data output) • SCK1 (shift clock input or output) • SS1 (active-low slave select). © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 In Master mode operation, SCK1 is a clock output. In Slave mode clock input. A series of eight (8) or sixteen (16) clock pulses shift out bits from the SPI1SR to SDO1 pin and simultaneously shift in data from SDI1 pin ...

  • Page 94

    ... Synchronization Pulse). The frame pulse is an active-high pulse for a single SPI clock cycle. When Frame Synchronization transmission starts only on the subsequent transmit edge of the SPI clock. Secondary Primary F Prescaler CY Prescaler 1:1 – generates the Frame is enabled, the data © 2010 Microchip Technology Inc. ...

  • Page 95

    ... CPU enters Sleep mode while an SPI transaction is in progress, then the transmission and reception is aborted. The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SDO1 SDI1 SDI1 SDO1 ...

  • Page 96

    TABLE 13-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend: — = unimplemented bit, read ...

  • Page 97

    ... Thus, the I C module can operate either as a slave master bus. FIGURE 14-1: PROGRAMMER’S MODEL Bit 15 Bit 15 © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 14.1.1 VARIOUS I The following types • slave operation with 7-bit addressing 2 • slave operation with 10-bit addressing 2 • ...

  • Page 98

    ... LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2010 Microchip Technology Inc. ...

  • Page 99

    ... SDA is valid during SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 14.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated ...

  • Page 100

    ... C bus have de-asserted SCL. This ensures that a write to the SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. © 2010 Microchip Technology Inc. ...

  • Page 101

    ... When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CRCV to determine if the address was device specific or a general call address. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2 14. Master Support ...

  • Page 102

    ... Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle master event Interrupt Service 2 C bus is free (i.e., the P bit is set), the C bus is free, the user can resume 2 © 2010 Microchip Technology Inc. C ...

  • Page 103

    TABLE 14- REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — — — — I2CCON 0206 I2CEN — ...

  • Page 104

    ... NOTES: DS70139G-page 104 © 2010 Microchip Technology Inc. ...

  • Page 105

    ... Internal Data Bus UTXBRK Data UxTX Parity Note © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...

  • Page 106

    ... Receive Buffer Control 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16x Baud Clock from Baud Rate Generator Read Read Write UxMODE UxSTA – Generate Flags – Generate Interrupt – Shift Data Characters Control Signals UxRXIF © 2010 Microchip Technology Inc. ...

  • Page 107

    ... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.3 Transmitting Data 15.3.1 ...

  • Page 108

    ... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. RXB) X the settings specified by © 2010 Microchip Technology Inc. ...

  • Page 109

    ... The URXISEL control bit does not have any impact on interrupt generation in this mode since an interrupt (if enabled) will be generated every time the received word has the 9th bit set. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.7 Loopback Mode Setting the LPBACK bit enables this special mode in which the UxTX pin is internally connected to the UxRX pin ...

  • Page 110

    ... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode or whether the module will continue on Idle. If USIDL = 0, the module will continue to operate during Idle mode. If USIDL = 1, the module will stop on Idle. DS70139G-page 110 © 2010 Microchip Technology Inc. ...

  • Page 111

    TABLE 15-1: UART1 REGISTER MAP FOR dsPIC30F2011/2012/3012/3013 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — ...

  • Page 112

    ... NOTES: DS70139G-page 112 © 2010 Microchip Technology Inc. ...

  • Page 113

    ... AN6 0111 AN7 1000 AN8 1001 AN9 © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The ADC module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) • A/D Control Register 3 (ADCON3) • A/D Input Select Register (ADCHS) • ...

  • Page 114

    ... The inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. If the number of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused. © 2010 Microchip Technology Inc. number of ...

  • Page 115

    ... There are 64 possible options for T EQUATION 16-1: ADC CONVERSION CLOCK (0.5*(ADCS<5:0> © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The internal RC oscillator is selected by setting the ADRC bit. For correct ADC conversions, the ADC conversion clock (T ) must be selected to ensure a minimum T AD time of 334 nsec (for V “ ...

  • Page 116

    ... dsPIC30F2011 Channel Configuration REF REF CH X ANx S/H ADC REF REF ANx S/H ADC ANx REF Figure 16-2 for recommended See Note μF 0.1 μF 0.01 μ μF 0.1 μF 0.01 μF pin. DD © 2010 Microchip Technology Inc. + ...

  • Page 117

    ... DAC) HOLD Note: C value depends on device package and is not tested. Effect of C PIN © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The following figure shows the timing diagram of the ADC running at 200 ksps. The T conjunction with the guidelines described above allows a conversion speed of 200 ksps ...

  • Page 118

    ... Each of the output formats translates to a 16-bit result on the data bus. d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 © 2010 Microchip Technology Inc. ...

  • Page 119

    ... Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 16.14 Connection Considerations The analog inputs have diodes to V protection ...

  • Page 120

    TABLE 16-2: A/D CONVERTER REGISTER MAP FOR dsPIC30F2011/3012 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — ...

  • Page 121

    TABLE 16-3: A/D CONVERTER REGISTER MAP FOR dsPIC30F2012/3013 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — ...

  • Page 122

    ... NOTES: DS70139G-page 122 © 2010 Microchip Technology Inc. ...

  • Page 123

    ... In the Idle mode, the clock sources are still active but the CPU is shut-off. The RC oscillator option saves system cost while the LP crystal option saves power. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...

  • Page 124

    ... RC oscillator. Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70139G-page 124 Description (1) . (2) . (1) . (1) . (1) . (3) /4 output . OSC (3) . © 2010 Microchip Technology Inc. ...

  • Page 125

    ... FIGURE 17-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Internal FRC Osc Primary Oscillator Stability Detector ...

  • Page 126

    ... OSC2 Function OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 OSC2 0 0 OSC2 1 0 CLKO 1 1 CLKO OSC2 0 0 (Note (Note (Note © 2010 Microchip Technology Inc. ...

  • Page 127

    ... FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are set to ‘00001’, ‘01010’ or ‘00011’, a PLL multiplier (respectively) is applied ...

  • Page 128

    ... To write to the OSCCON high byte, the following instructions must be executed without any other instructions in between: Byte Write 0x78 to OSCCON high Byte Write 0x9A to OSCCON high Byte write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. © 2010 Microchip Technology Inc. ...

  • Page 129

    ... Detect V DD Brown-out Reset BOREN Trap Conflict Illegal Opcode/ Uninitialized W Register © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.3.1 POR: POWER-ON RESET A power-on event will generate an internal POR pulse devices when a V rise is detected. The Reset pulse will occur DD at the POR circuit threshold voltage (V nominally 1 ...

  • Page 130

    ... INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 17-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70139G-page 130 T OST T PWRT T OST T PWRT T OST T PWRT ) DD ): CASE CASE 2 DD © 2010 Microchip Technology Inc. ...

  • Page 131

    ... Refer to the Electrical Specifications in the specific device data sheet for BOR voltage limit specifications. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source based on the device Configuration bit values (FOS< ...

  • Page 132

    ... Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70139G-page 132 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( © 2010 Microchip Technology Inc. ...

  • Page 133

    ... In some devices, the LVD threshold voltage may be applied externally on the LVDIN pin. The LVD module is enabled by setting the LVDEN bit (RCON<12>). © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.6 Power-Saving Modes There are two power-saving states that can be entered through the execution of a special instruction, PWRSAV ...

  • Page 134

    ... For additional information, please refer to the Programming Specifications of the device. Note: If the code protection Configuration fuse bits (FGS<GCP> and FGS<GWRP>) have been programmed, an erase of the entire code-protected device is only possible at voltages V the Configuration bits is ≥ 4.5V. DD © 2010 Microchip Technology Inc. ...

  • Page 135

    ... Control reg- isters are already configured to enable module operation dsPIC30F2011, dsPIC30F3012 and dsPIC30F2012 devices, the U2MD bit is readable and writable and will be read as ‘1’ when set. © 2010 Microchip Technology Inc. ...

  • Page 136

    TABLE 17-7: SYSTEM INTEGRATION REGISTER MAP SFR Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name RCON 0740 TRAPR IOPUWR BGST LVDEN OSCCON 0742 — COSC<2:0> OSCTUN 0744 — — — — PMD1 0770 — — T3MD ...

  • Page 137

    ... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Most bit-oriented rotate/shift instructions) have two operands: • ...

  • Page 138

    ... Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the “MCU and DSC Programmer’s Reference Manual” (DS70157). indirect writes, and Description © 2010 Microchip Technology Inc. ...

  • Page 139

    ... Y data space prefetch address register for DSP instructions ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space prefetch destination register for DSP instructions ∈ {W4..W7} Wyd © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description DS70139G-page 139 ...

  • Page 140

    ... Branch if Accumulator A overflow Branch if Accumulator B overflow Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> © 2010 Microchip Technology Inc Status Flags Cycle Affected OA,OB,SA, C,DC,N,OV,Z ...

  • Page 141

    ... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...

  • Page 142

    ... Move f to WREG Move 16-bit literal to Wn Move 8-bit literal to Wn Move Move Move WREG to f Move Double from W(ns):W(ns+ Move Double from Ws to W(nd+1):W(nd) Prefetch and store accumulator © 2010 Microchip Technology Inc Status Flags Cycle Affected N,Z,C,OV ...

  • Page 143

    ... RLNC Ws,Wd 65 RRC RRC f RRC f,WREG RRC Ws,Wd © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * ...

  • Page 144

    ... Wd = lit5 - nibble swap byte swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink frame pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws © 2010 Microchip Technology Inc Status Flags Cycle Affected N N N,Z ...

  • Page 145

    ... MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...

  • Page 146

    ... Support for the entire device instruction set ® standard HEX • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility © 2010 Microchip Technology Inc. ...

  • Page 147

    ... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- ...

  • Page 148

    ... This usually includes a single application and debug capability, all for DDMAX on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® © 2010 Microchip Technology Inc. ...

  • Page 149

    ... Exposure to maximum rating conditions for extended periods may affect device reliability. Note: All peripheral electrical characteristics are specified. For exact peripherals available on specific devices, please refer to the this data sheet. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 (except V and MCLR) (Note 1) ..................................... -0. .......................................................................................................... ± > ...

  • Page 150

    ... Max MIPS dsPIC30FXXX-20E — 20 — 15 — Min Typ Max Unit -40 — +125 °C -40 — +85 °C -40 — +150 °C -40 — +125 ° INT θ Typ Max Unit Notes 44 — °C — °C — °C — °C — °C/W 1 © 2010 Microchip Technology Inc. ...

  • Page 151

    ... Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: This is the limit to which V DD © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min ...

  • Page 152

    ... OSC1 DD 0.128 MIPS LPRC (512 kHz) (1.8 MIPS) FRC (7.37 MHz) 4 MIPS 10 MIPS 20 MIPS 30 MIPS . DD © 2010 Microchip Technology Inc. ...

  • Page 153

    ... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with Core off, Clock on and all modules turned off. IDLE © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...

  • Page 154

    ... PD (3) Base Power-Down Current Watchdog Timer Current: ΔI (3) WDT (3) Timer1 w/32 kHz Crystal: Δ BOR On: ΔI (3) BOR Low-Voltage Detect: ΔI (3) LVD © 2010 Microchip Technology Inc. ...

  • Page 155

    ... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...

  • Page 156

    ... Industrial A ≤ +125°C for Extended A Units Conditions 8.5 mA 2.0 mA 1.6 mA 2.0 mA -3.0 mA -2.0 mA -1.3 mA -2.0 mA XTL, XT, HS and LP modes when external clock is used to drive OSC1 Osc mode mode © 2010 Microchip Technology Inc. ...

  • Page 157

    ... LV15 V External LVD input pin LVDIN threshold voltage Note 1: These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min (2) transition LVDL = 0000 — ...

  • Page 158

    ... BORV = 10 2.6 — BORV = 01 4.1 — BORV = 00 4.58 — — 5 (Device not in Brown-out Reset) Power-Up Time-out ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions — V Not in operating range 2.71 V 4.4 V 4.73 V — mV © 2010 Microchip Technology Inc. ...

  • Page 159

    ... During Programming EB DD Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...

  • Page 160

    ... Load Condition 2 — for OSC2 Pin Legend: = 464 Ω for all pins except OSC2 for OSC2 output OS20 OS30 OS30 OS25 OS40 ≤ +85°C for Industrial ≤ +125°C for Extended Section 20.1 “ OS31 OS31 OS41 © 2010 Microchip Technology Inc. ...

  • Page 161

    ... Measurements are taken ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 T © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...

  • Page 162

    ... V = 4 ≤ +85° 3 ≤ +125° 3 ≤ +85° 4 ≤ +125° 4 ≤ +85° 3 ≤ +85° 4 ≤ +125° 4 © 2010 Microchip Technology Inc. ...

  • Page 163

    ... TABLE 20-19: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY AC CHARACTERISTICS Param Characteristic No. (1) LPRC @ Freq. = 512 kHz OS65A OS65B OS65C Note 1: Change of LPRC frequency as V © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 (3) MIPS MIPS (2) (μsec) w/o PLL w PLL x4 20.0 0.05 — 1.0 1 ...

  • Page 164

    ... Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended A (1)(2)(3) (4) Min Typ Max — — — — — — CY Units Conditions OSC © 2010 Microchip Technology Inc. ...

  • Page 165

    ... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure 20-2 and Table 20-11 © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SY10 SY13 Note: Refer to Figure 20-3 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...

  • Page 166

    ... Band Gap Stable ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. RCON<13> bit © 2010 Microchip Technology Inc. ...

  • Page 167

    ... TCS (T1CON, bit 1)) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note: Timer1 is a Type A. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...

  • Page 168

    ... T — CY ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TC15 — ns Must also meet parameter TC15 — prescale value (1, 8, 64, 256) 1.5 — © 2010 Microchip Technology Inc. ...

  • Page 169

    ... IC11 TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 IC10 IC11 IC15 for load conditions. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...

  • Page 170

    ... T Operating temperature -40°C ≤ T (1) (2) Min Typ Max — — — — — — ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions ns See Parameter DO32 ns See Parameter DO31 © 2010 Microchip Technology Inc. ...

  • Page 171

    ... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...

  • Page 172

    ... T ≤ +125°C for Extended A Max Units Conditions — ns — — ns — — ns See parameter DO32 — ns See parameter DO31 — ns See parameter DO32 — ns See parameter DO31 30 ns — — ns — — ns — © 2010 Microchip Technology Inc. ...

  • Page 173

    ... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SP10 SP21 SP35 SP20 LSb ...

  • Page 174

    ... Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — — ns — — — — ns See DO32 — ns See DO31 30 ns — — ns — — ns — — ns — — — ns — © 2010 Microchip Technology Inc. ...

  • Page 175

    ... SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 20-3 for load conditions. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SP70 SP73 SP35 SP72 SP52 BIT LSb SP30,SP31 BIT LSb IN SP52 SP72 SP73 SP51 DS70139G-page 175 ...

  • Page 176

    ... T ≤ +125°C for Extended A Max Units Conditions — ns — — ns — — — — ns See parameter DO32 — ns See parameter DO31 30 ns — — ns — — ns — — ns — — — ns — — © 2010 Microchip Technology Inc. ...

  • Page 177

    ... I C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 20-3 for load conditions. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 IM11 IM10 IM26 IM25 IM40 IM34 IM33 Stop Condition IM21 IM33 IM45 ...

  • Page 178

    ... C™ pins (for 1 MHz mode only). © 2010 Microchip Technology Inc. ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions C is specified from 10 to 400 specified from 10 to 400 pF ...

  • Page 179

    ... Fall Time IS21 T : SDA and SCL R SCL Rise Time Note 1: Maximum pin capacitance = 10 pF for all I © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 IS11 IS10 IS26 IS25 IS40 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial ...

  • Page 180

    ... Only relevant for Repeated Start condition μs μs μs After this period the first clock pulse is generated μs μs μs μs μ μs Time the bus must be free before a new transmission μs can start μs pF © 2010 Microchip Technology Inc. ...

  • Page 181

    ... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 CA10 CA11 CA20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...

  • Page 182

    ... See Note 1 V — INL SS REFL 0V REFH Source Impedance = 2.5 kΩ INL SS REFL 0V REFH Source Impedance = 2.5 kΩ Ω Ω INL SS REFL 0V REFH INL SS REFL 0V REFH INL SS REFL 0V REFH INL SS REFL 0V REFH INL SS REFL 0V REFH INL SS REFL 0V REFH © 2010 Microchip Technology Inc. ...

  • Page 183

    ... Effective Number of Bits Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: Measurements taken with external V © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...

  • Page 184

    ... Section 18. “12-bit A/D Converter” in the dsPIC30F Family Reference Manual (DS70046). SAMP 3 - Software clears ADCON. SAMP to Start conversion Sampling ends, conversion sequence starts Convert bit 11 Convert bit 10 Convert bit Convert bit One T for end of conversion. AD DS70139G-page 184 AD55 © 2010 Microchip Technology Inc. ...

  • Page 185

    ... ADC module to stabilize when it is turned on (ADCON1<ADON> = 1). DPU During this time the ADC result is indeterminate. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature-40°C ≤ T Min. ...

  • Page 186

    ... NOTES: DS70139G-page 186 © 2010 Microchip Technology Inc. ...

  • Page 187

    ... Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Example dsPIC30F3012 30I/P Example dsPIC30F2011 e 30I/SO 0610017 Example ...

  • Page 188

    ... Package Marking Information (Continued) 28-Lead SOIC XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead QFN-S XXXXXXX XXXXXXX YYWWNNN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS70139G-page 188 Example dsPIC30F3013 e 3 30I/SO 0610017 Example 30F2011 e 30I/MM 3 0610017 Example dsPIC 30F3013 e 30I/ML 3 0610017 © 2010 Microchip Technology Inc. ...

  • Page 189

    ... N NOTE © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139G-page 189 ...

  • Page 190

    ... D N NOTE DS70139G-page 190 α φ A2 β © 2010 Microchip Technology Inc. ...

  • Page 191

    ... Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139G-page 191 ...

  • Page 192

    ... N NOTE DS70139G-page 192 © 2010 Microchip Technology Inc. c ...

  • Page 193

    ... N NOTE © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 α φ β DS70139G-page 193 ...

  • Page 194

    ... Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70139G-page 194 © 2010 Microchip Technology Inc. ...

  • Page 195

    ... D TOP VIEW A3 © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 EXPOSED PAD NOTE 1 BOTTOM VIEW DS70139G-page 195 ...

  • Page 196

    ... DS70139G-page 196 © 2010 Microchip Technology Inc. ...

  • Page 197

    ... D TOP VIEW A3 © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 EXPOSED PAD NOTE BOTTOM VIEW DS70139G-page 197 ...

  • Page 198

    ... DS70139G-page 198 © 2010 Microchip Technology Inc. ...

  • Page 199

    ... Watchdog Timer time-out limits (see Table 20-21) Revision E (December 2006) This revision includes updates to the packaging diagrams. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Revision F (May 2008) This revision reflects these updates: • Added FUSE Configuration Register (FICD) details (see Registers” ...

  • Page 200

    ... Renamed parameter AD56 to AD56a and added parameter AD56b to the 12-bit A/D Conversion Timing Requirements (see Added the “MM” package definition. “Pin Diagrams”). and AV (see Table 1-1 Section 17.2.5 “Fast RC Table 20-8). Table 20-37). © 2010 Microchip Technology Inc. ...