DSPIC30F3012-30I/SO Microchip Technology, DSPIC30F3012-30I/SO Datasheet
DSPIC30F3012-30I/SO
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DSPIC30F3012-30I/SO Summary of contents
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... Family Silicon Errata and Data Sheet Clarification The dsPIC30F3012/3013 family devices that you have received conform functionally to the current Device Data Sheet (DS70139F), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1 ...
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... TABLE 2: SILICON ISSUE SUMMARY Item Module Feature Number CPU MAC Class 1. Instructions with ±4 Address Modification CPU 2. DAW.b Instruction PSV — 3. Operations CPU Nested DO 4. Loops Interrupt — 5. Controller CPU 6. DISI Instruction Output PWM Mode 7. Compare Output — 8. Compare ADC Sleep Mode 9 ...
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... For this revision of silicon, if the pin RC15 is required for digital input/output, the FPR<4:0> bits in the FOSC Configuration Fuse register may not be set up for FRC w/PLL 4x/8x/16x modes. If the ADC module enabled state when the device enters Sleep Mode, the power-down current (I exceed the device data sheet specifications. dsPIC30F3012/3013 Affected Revisions ® ...
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... Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B1). 1. Module: CPU Sequential MAC class instructions, which prefetch data from Y data space using ± ...
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... Example 2. © 2010 Microchip Technology Inc. dsPIC30F3012/3013 These instructions are identified in Table 3. Example 2 demonstrates one scenario in which this occurs. Also, always use Work around 2 if the C compiler is used to generate code for dsPIC30F3012/3013 devices. (2) Examples of Incorrect Operation ADDC W0, [W1++], W2 ; SUBB.b W0, [++W1 ...
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... Module: CPU When using two DO loops in a nested fashion, terminating the inner-level DO loop by setting the EDT bit (CORCON<11>) will produce unexpected results. Specifically, the device may continue executing code within the outer DO loop forever. This erratum does not affect the operation of the MPLAB C30 compiler ...
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... SET_AND_SAVE_CPU_IPL (save_sr, 7);\ x; \ RESTORE_CPU_IPL (save_sr); } (void INTERRUPT_PROTECT (IEC0bits.U1TXIE=0); Note: If you are using a MPLAB C30 compiler version earlier than version 1.32, you may still use the macros by adding them to your application. Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F3012/3013 DS80448D-page 7 ...
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... Module: CPU When a user executes a DISI #7, for example, this will disable interrupts for cycles (7 + the DISI instruction itself). In this case, the DISI instruction uses a counter which counts down from The counter is loaded with 7 at the end of the DISI instruction. If the user code executes another DISI on the ...
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... Module: PLL PLL mode is used, the input frequency range is 5 MHz-10 MHz instead of 4 MHz-10 MHz. Work around None PLL mode is used, make sure the input crystal or clock frequency is 5 MHz or greater. Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F3012/3013 DS80448D-page 9 ...
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... Module: Sleep Mode Execution of the Sleep instruction (PWRSAV #0) may cause incorrect program operation after the device wakes up from Sleep. The current consumption during Sleep may also increase beyond the specifications listed in the device data sheet. Work arounds To avoid this issue, implement any of the following three work arounds, depending on the application requirements ...
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... Note: The above work around is recommended for users for whom application hardware changes are not possible. © 2010 Microchip Technology Inc. dsPIC30F3012/3013 Work around 3: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 32 kHz Low-Power (LP) Oscillator with a 64:1 postscaler mode ...
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... Module When the I C module is configured as a slave, either in single-master or multi-master mode, the receiver buffer is filled whether a valid slave address is detected or not. Therefore receiver overflow condition occurs and this condition is indicated by the I2COV flag in the I2CSTAT register. This overflow condition inhibits the ability to set the ...
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... Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F3012/3013 16. Module: PLL The PLL LOCK Status bit (OSCCON<5>) can occasionally get cleared and generate an oscillator failure trap even when the PLL is still locked and functioning correctly. Work around The user application must include an oscillator failure trap service routine ...
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... Module 10-bit Addressing mode, some address matches don’t set the RBF flag or load the receive register I2CxRCV, if the lower address byte matches the reserved addresses. In particular, these include all addresses with the form XX0000XXXX and XX1111XXXX, following exceptions: • ...
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... BSET.b [w1], #6;set poscalar to divide by 4 Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F3012/3013 23. Module: OSC2 Pin The port pin, RC15, is multiplexed with the primary oscillator pin, OSC2. When pin RC15 is required for digital input/output, specific bits in the Oscillator Configuration Fuse register, FOSC, may be set up as follows: • ...
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... Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS70139F): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: DC Characteristics: I/O Pin Input ...
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... C), 13 (I/O C), 15 (Timer), 16 (PLL), 17 (PSV Operations), 18-20 (I Low-Power (LP) Oscillator) and 22-23 (OSC2 Pin). This document replaces the following errata documents: • DS80230, “dsPIC30F3012/3013 Rev. B0 Silicon Errata” • DS80255, “dsPIC30F3012/3013 Rev. B1 Silicon Errata” Rev B Document (8/2009) Updated silicon issue 5 (Interrupt Controller). ...
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... NOTES: DS80448D-page 18 © 2010 Microchip Technology Inc. ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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