DSPIC30F3012-30I/SO Microchip Technology, DSPIC30F3012-30I/SO Datasheet - Page 69

• Manufacturer Part Number: DSPIC30F3012-30I/SO
• Description: IC DSPIC MCU/DSP 24K 18SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3012-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 12
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 18SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301230ISO

FIGURE 8-1:
8.4
All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
Interrupt Request (IRQ) is indicated by the flag bit
being equal to a ‘1’ in an IFSx register. The IRQ causes
an interrupt to occur if the corresponding bit in the
Interrupt Enable (IECx) register is set. For the
remainder of the instruction cycle, the priorities of all
pending interrupt requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor is interrupted.
The processor then stacks the current program counter
and the low byte of the processor STATUS register
(SRL), as shown in
STATUS register contains the processor priority level at
the time prior to the beginning of the interrupt cycle.
The processor then loads the priority level for this
interrupt into the STATUS register. This action disables
all lower priority interrupts until the completion of the
Interrupt Service Routine (ISR).
© 2010 Microchip Technology Inc.
AIVT
Interrupt Sequence
IVT
Address Error Trap Vector
Address Error Trap Vector
Oscillator Fail Trap Vector
Oscillator Fail Trap Vector
Reset - GOTO Instruction
Stack Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Math Error Trap Vector
Reset - GOTO Address
Interrupt 52 Vector
Interrupt 53 Vector
Interrupt 52 Vector
Interrupt 53 Vector
Interrupt 0 Vector
Interrupt 1 Vector
Interrupt 0 Vector
Interrupt 1 Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
Figure
TRAP VECTORS
Reserved
Reserved
Reserved
Reserved
—
—
—
—
—
—
8-2. The low byte of the
dsPIC30F2011/2012/3012/3013
0x000000
0x000014
0x000094
0x0000FE
0x000002
0x000004
0x00007E
0x000082
0x000084
0x000080
FIGURE 8-2:
The RETFIE (return from interrupt) instruction unstacks
the program counter and STATUS registers to return
the processor to its state prior to the interrupt
sequence.
8.5
In program memory, the Interrupt Vector Table (IVT) is
followed by the Alternate Interrupt Vector Table (AIVT),
as shown in
table is provided by the ALTIVT bit in the INTCON2
register. If the ALTIVT bit is set, all interrupt and
exception processes use the alternate vectors instead
of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports emulation and debugging efforts by
providing a means to switch between an application
and a support environment without requiring the
interrupt vectors to be reprogrammed. This feature also
enables switching between applications for evaluation
of different software algorithms at run time.
If the AIVT is not required, the program memory
allocated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.
0x0000
Note 1: The user can always lower the priority
2: The IPL3 bit (CORCON<3>) is always
Alternate Vector Table
SRL IPL3 PC<22:16>
15
level by writing a new value into SR. The
Interrupt Service Routine must clear the
interrupt flag bits in the IFSx register
before lowering the processor interrupt
priority, in order to avoid recursive
interrupts.
clear
processed. It is set only during execution
of traps.
Figure
<Free Word>
PC<15:0>
8-1. Access to the alternate vector
when
INTERRUPT STACK
FRAME
interrupts
0
POP : [--W15]
PUSH: [W15++]
W15 (before CALL)
W15 (after CALL)
DS70139G-page 69
are
being