PIC18F46J50-I/ML Microchip Technology, PIC18F46J50-I/ML Datasheet
PIC18F46J50-I/ML
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PIC18F46J50-I/ML Summary of contents
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... High-Performance USB Microcontrollers © 2009 Microchip Technology Inc. PIC18F46J50 Family 28/44-Pin, Low-Power, with nanoWatt XLP Technology Data Sheet DS39931C ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F46J50 FAMILY 28/44-Pin, Low-Power, High-Performance USB Microcontrollers Power Management Features with nanoWatt XLP™ for Extreme Low-Power: • Deep Sleep mode: CPU off, Peripherals off, Currents Down and 850 nA with RTCC - Able to wake-up on external triggers, programmable WDT or RTCC alarm - Ultra Low-Power Wake-up (ULPWU) • ...
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... PIC18F46J50 FAMILY (1) PIC18F/LF Device PIC18F24J50 28 16K 3776 16 PIC18F25J50 28 32K 3776 16 PIC18F26J50 28 64K 3776 16 PIC18F44J50 44 16K 3776 22 PIC18F45J50 44 32K 3776 22 PIC18F46J50 44 64K 3776 22 PIC18LF24J50 28 16K 3776 16 28 32K 3776 16 PIC18LF25J50 28 64K 3776 16 PIC18LF26J50 44 16K 3776 22 PIC18LF44J50 44 32K 3776 22 PIC18LF45J50 44 64K 3776 22 PIC18LF46J50 Note 1: See Section 1.3 “ ...
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... Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “Peripheral Pin Select (PPS)”. 2: See Section 26.3 “On-Chip Voltage Regulator” for details on how to connect the V 3: For the QFN package recommended that the bottom pad be connected to V © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY ...
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... PIC18F46J50 FAMILY Pin Diagrams (Continued) (1,3) 44-Pin QFN RC7/PMA4/RX1/DT1/SDO1/RP18 RD4/PMD4/RP21 RD5/PMD5/RP22 RD6/PMD6/RP23 RD7/PMD7/RP24 RB0/AN12/INT0/RP3 RB1/AN10/PMBE/RTCC/RP4 RB2/AN8/CTEDG1/PMA3/VMO/REFO/RP5 Legend: RPn represents remappable pins. Note 1: Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 9-13 and Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “ ...
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... RPn pins. For a list of the input and output functions, see Table 9-13 and Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “Peripheral Pin Select (PPS)”. 2: See Section 26.3 “On-Chip Voltage Regulator” for details on how to connect the V © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY ...
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... PIC18F46J50 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Oscillator Configurations ............................................................................................................................................................ 29 3.0 Low-Power Modes...................................................................................................................................................................... 41 4.0 Reset .......................................................................................................................................................................................... 57 5.0 Memory Organization ................................................................................................................................................................. 71 6.0 Flash Program Memory .............................................................................................................................................................. 97 7 Hardware Multiplier.......................................................................................................................................................... 107 8.0 Interrupts .................................................................................................................................................................................. 109 9.0 I/O Ports ................................................................................................................................................................................... 125 10.0 Parallel Master Port (PMP)....................................................................................................................................................... 163 11.0 Timer0 Module ......................................................................................................................................................................... 189 12 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY DS39931C-page 9 ...
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... PIC18F46J50 FAMILY NOTES: DS39931C-page 10 © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F46J50 FAMILY 1.1.3 OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F46J50 Family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes, using crystals or ceramic resonators. ...
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... Section 29.0 “Electrical Characteristics” for time-out periods. 1.3 Details on Individual Family Devices Devices in the PIC18F46J50 Family are available in 28-pin and 44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in two ways: • ...
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... Interrupt Sources I/O Ports Timers Enhanced Capture/Compare/PWM Modules Serial Communications Parallel Communications (PMP/PSP) 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY PIC18F24J50 PIC18F25J50 DC – 48 MHz DC – 48 MHz 16K 32K 8,192 16,384 3.8K 3.8K ...
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... PIC18F46J50 FAMILY FIGURE 1-1: PIC18F2XJ50 (28-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 Address Latch Program Memory (16 Kbytes-64 Kbytes) Data Latch 8 Instruction Bus <16> Timing Generation OSC2/CLKO OSC1/CLKI 8 MHz INTOSC INTRC Oscillator V USB USB Module Precision Band Gap Reference Voltage Regulator ...
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... RTCC Timer0 HLVD 10-Bit PMP CTMU ECCP1 Note 1: See Table 1-3 for I/O port pin descriptions. 2: The on-chip voltage regulator is always enabled by default. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Data Latch 8 8 Data Memory (3.8 Kbytes) PCLATU PCLATH Address Latch 20 ...
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... PIC18F46J50 FAMILY TABLE 1-3: PIC18F2XJ50 PINOUT I/O DESCRIPTIONS Pin Number 28-SPDIP/ Pin Name SSOP/ SOIC MCLR 1 OSC1/CLKI/RA7 9 OSC1 CLKI (1) RA7 OSC2/CLKO/RA6 10 OSC2 CLKO (1) RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Pin Buffer Type Type 28-QFN PORTA is a bidirectional I/O port. 27 I/O DIG Digital I/O ...
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... PIC18F46J50 FAMILY TABLE 1-3: PIC18F2XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number 28-SPDIP/ Pin Name SSOP/ SOIC RB0/AN12/INT0/RP3 21 RB0 AN12 INT0 RP3 RB1/AN10/RTCC/RP4 22 RB1 AN10 RTCC RP4 RB2/AN8/CTEDG1/VMO/ 23 REFO/RP5 RB2 AN8 CTEDG1 VMO REFO RP5 RB3/AN9/CTEDG2/VPO/RP6 24 RB3 AN9 CTEDG2 VPO RP6 Legend: TTL = TTL compatible input ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Pin Buffer Type Type 28-QFN PORTB (continued) 22 I/O DIG Digital I/O ...
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... PIC18F46J50 FAMILY TABLE 1-3: PIC18F2XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number 28-SPDIP/ Pin Name SSOP/ SOIC RC0/T1OSO/T1CKI/RP11 11 RC0 T1OSO T1CKI RP11 RC1/T1OSI/UOE/RP12 12 RC1 T1OSI UOE RP12 RC2/AN11/CTPLS/RP13 13 RC2 AN11 CTPLS RP13 RC4/D-/VM 15 RC4 D- VM RC5/D+/VP 16 RC5 D+ VP RC6/TX1/CK1/RP17 17 RC6 ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Pin Buffer Type Type 28-QFN 5 P — Ground reference for logic and I/O pins. ...
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... PIC18F46J50 FAMILY TABLE 1-4: PIC18F4XJ50 PINOUT I/O DESCRIPTIONS Pin Number Pin Name QFN MCLR OSC1/CLKI/RA7 OSC1 CLKI (1) RA7 OSC2/CLKO/RA6 OSC2 CLKO (1) RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Pin Buffer 44- 44- Type Type TQFP PORTA is a bidirectional I/O port. ...
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... PIC18F46J50 FAMILY TABLE 1-4: PIC18F4XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name QFN RB0/AN12/INT0/RP3 RB0 AN12 INT0 RP3 RB1/AN10/PMBE/RTCC/RP4 RB1 AN10 PMBE RTCC RP4 RB2/AN8/CTEDG1/PMA3/VMO/ REFO/RP5 RB2 AN8 CTEDG1 PMA3 VMO REFO RP5 RB3/AN9/CTEDG2/PMA2/VPO/ RP6 RB3 AN9 CTEDG2 PMA2 VPO ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Pin Buffer 44- 44- Type Type TQFP PORTB (continued) ...
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... PIC18F46J50 FAMILY TABLE 1-4: PIC18F4XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name QFN RC0/T1OSO/T1CKI/RP11 RC0 T1OSO T1CKI RP11 RC1/T1OSI/UOE/RP12 RC1 T1OSI UOE RP12 RC2/AN11/CTPLS/RP13 RC2 AN11 CTPLS RP13 RC4/D-/VM RC4 D- VM RC5/D+/VP RC5 D+ VP RC6/PMA5/TX1/CK1/RP17 RC6 PMA5 TX1 CK1 RP17 ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Pin Buffer 44- 44- Type Type TQFP PORTD is a bidirectional I/O port. ...
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... PIC18F46J50 FAMILY TABLE 1-4: PIC18F4XJ50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name QFN RE0/AN5/PMRD RE0 AN5 PMRD RE1/AN6/PMWR RE1 AN6 PMWR RE2/AN7/PMCS RE2 AN7 PMCS DDCORE CAP V DDCORE V CAP USB Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... Phase Locked Loop (PLL). Its use is described in Section 2.2.5.1 “OSCTUNE Register”. 2.2 Oscillator Types PIC18F46J50 Family devices can be operated in eight distinct oscillator modes. Users can program the FOSC<2:0> Configuration bits to select one of the modes listed in Table 2-1. For oscillator modes which ...
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... The USB module cannot be used to communicate unless the primary clock source is selected. DS39931C-page 30 A network of MUXes, clock dividers and a fixed 96 MHz output PLL have been provided, which can be used to derive various microcontroller core and USB module frequencies. Figure 2-1 helps in understanding the oscillator structure of the PIC18F46J50 Family of devices. PLLDIV<2:0> ÷ 12 000 ÷ 10 001 ÷ ...
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... Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY TABLE 2-3: Osc Type HS Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized ...
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... The CPU divider can reduce the incoming frequency by a factor 2.2.5 INTERNAL OSCILLATOR BLOCK The PIC18F46J50 Family devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. The internal oscillator may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins ...
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... INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 2.2.5.3 Compensating for INTOSC Drift It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has no effect on the INTRC clock source frequency ...
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... Minimum frequency 2.3 Oscillator Settings for USB When the PIC18F46J50 Family devices are used for USB connectivity MHz or 48 MHz clock must be provided to the USB module for operation in either Low-Speed or Full-Speed modes, respectively. This may require some forethought in selecting an oscillator frequency and programming the device ...
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... All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz). Bold text highlights the clock selections that are compatible with low-speed USB operation (system clock of 24 MHz, USB clock of 6 MHz). © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Clock Mode MCU Clock Division (FOSC<2:0>) (CPDIV< ...
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... PIC18F46J50 FAMILY 2.4 USB From INTOSC The 8 MHz INTOSC included in all PIC18F46J50 Fam- ily devices is extremely accurate. When the 8 MHz INTOSC is used with the 96 MHz PLL, it may be used to derive the USB module clock. The high accuracy of the INTOSC will allow the application to meet low-speed USB signal rate specifications ...
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... Microchip Technology Inc. PIC18F46J50 FAMILY 2.5.2 OSCILLATOR TRANSITIONS PIC18F46J50 Family devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs dur- ing the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... PIC18F46J50 FAMILY 2.6 Reference Clock Output In addition to the peripheral clock/4 output in certain oscillator modes, the device clock in the PIC18F46J50 Family can also be configured to provide a reference clock output signal to a port pin. This feature is avail- able in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application ...
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... MSSP slave, PMP, INTx pins, etc.). Peripherals that may add significant current Section 29.2 “DC Characteristics: Power-Down and Supply Current PIC18F46J50 Family (Industrial)”. 2.8 Power-up Delays Power-up delays are controlled by two timers so that no of ...
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... PIC18F46J50 FAMILY NOTES: DS39931C-page 40 © 2009 Microchip Technology Inc. ...
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... The power-managed modes include power-saving features offered on previous PIC devices, such as clock switching, ULPWU and Sleep mode. In addition, the PIC18F46J50 family devices add a new power-managed Deep Sleep mode. 3.1 Selecting Power-Managed Modes Selecting a power-managed mode requires these decisions: • Will the CPU be clocked? • ...
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... PIC18F46J50 FAMILY TABLE 3-1: LOW-POWER MODES DSCONH<7> OSCCON<7,1:0> Mode (1) (1) DSEN IDLEN SCS<1:0> Sleep 0 0 Deep Sleep 1 0 PRI_RUN N/A 0 SEC_RUN N/A 0 RC_RUN N/A 0 PRI_IDLE 0 1 SEC_IDLE 0 1 RC_IDLE 0 1 Note 1: IDLEN and DSEN reflect their values when the SLEEP instruction is executed. ...
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... T OST OSC © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock would be providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run ...
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... PIC18F46J50 FAMILY 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shutdown. This mode provides the best power conser- vation of all the Run modes while still executing code. It works well for user applications, which are not highly timing sensitive or do not require high-speed clocks at all times ...
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... T OST OSC PLL © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS<1:0> bits becomes ready (see Figure 3-6 will be clocked from the internal oscillator if either the Two-Speed Start-up or the FSCM are enabled (see Section 26 ...
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... PIC18F46J50 FAMILY 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘1’ when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS< ...
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... Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY T CSD PC On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON< ...
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... PIC18F46J50 FAMILY 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode (where the primary clock source is not stopped) and the primary clock source is the EC mode • PRI_IDLE mode and the primary clock source is ...
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... In all other Deep Sleep wake-up cases, application firmware needs to clear the RELEASE bit in order to reconfigure the I/O pins. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 3.6.3 DEEP SLEEP WAKE-UP SOURCES The device can be awakened from Deep Sleep mode by a MCLR, POR, RTCC, INT0 I/O pin interrupt, DSWDT or ULPWU event ...
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... PIC18F46J50 FAMILY 3.6.5 DEEP SLEEP BROWN-OUT RESET (DSBOR) The Deep Sleep module contains a dedicated Deep Sleep BOR (DSBOR) circuit. This circuit may be optionally enabled through the DSBOREN Configuration bit. The DSBOR circuit monitors the V voltage. The behavior of the DSBOR circuit is described in Section 4.4 “Brown-out Reset (BOR)”. ...
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... Upon waking from Deep Sleep, the I/O pins maintain their previous states. Clearing this bit will release the I/O pins and allow their respective TRIS and LAT bits to control their states. Note 1: This is the value when V DD © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY provided in U-0 U-0 — ...
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... PIC18F46J50 FAMILY REGISTER 3-3: DSGPR0: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 0 (BANKED F4Eh) Deep Sleep Persistent General Purpose bits bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 Deep Sleep Persistent General Purpose bits Contents are retained even in Deep Sleep mode. ...
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... The V supply POR circuit was not active, or was active, but did not detect a POR event DD Note 1: Unlike the other bits in this register, this bit can be set outside of Deep Sleep. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY U-0 U-0 U-0 — — ...
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... PIC18F46J50 FAMILY 3.7 Ultra Low-Power Wake-up The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt-on-change without excess current consumption. Follow these steps to use this feature: 1. Configure a remappable output pin to output the ULPOUT signal. 2. Map an INTx interrupt-on-change input function to the same pin as used for the ULPOUT output func- tion ...
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... OSCCONbits.IDLEN = 0; // enable deep sleep DSCONHbits.DSEN = 1; // Note: must be set just before executing Sleep(); //**************** //Enter Sleep Mode //**************** Sleep(); // for sleep, execution will resume here // for deep sleep, execution will restart at reset vector (use WDTCONbits.DS to detect) © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY DS39931C-page 55 ...
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... PIC18F46J50 FAMILY NOTES: DS39931C-page 56 © 2009 Microchip Technology Inc. ...
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... RESET The PIC18F46J50 Family of devices differentiate among various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset execution) e) Configuration Mismatch (CM) f) Brown-out Reset (BOR) g) RESET Instruction h) Stack Full Reset i) Stack Underflow Reset ...
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... PIC18F46J50 FAMILY REGISTER 4-1: RCON: RESET CONTROL REGISTER (ACCESS FD0h) R/W-0 U-0 R/W-1 IPEN — CM bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘ ...
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... POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. 4.4 Brown-out Reset (BOR) The “F” devices in the PIC18F46J50 Family incorpo- rate two types of BOR circuits: one which monitors V and one which monitors V DDCORE DD circuit can be active at a time ...
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... Electrostatic always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F46J50 Fam- ily devices is a 5-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval μ ms. While the PWRT is counting, the device is held in Reset ...
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... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-5: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY T PWRT T PWRT , V RISE > 3. PWRT ): CASE 1 DD ...
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... PIC18F46J50 FAMILY 4.7 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ50 devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...
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... PIC18F46J50 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices POSTINC2 PIC18F2XJ50 PIC18F4XJ50 POSTDEC2 PIC18F2XJ50 PIC18F4XJ50 PREINC2 PIC18F2XJ50 PIC18F4XJ50 PLUSW2 PIC18F2XJ50 PIC18F4XJ50 FSR2H PIC18F2XJ50 PIC18F4XJ50 FSR2L PIC18F2XJ50 PIC18F4XJ50 STATUS PIC18F2XJ50 PIC18F4XJ50 TMR0H PIC18F2XJ50 PIC18F4XJ50 TMR0L PIC18F2XJ50 PIC18F4XJ50 T0CON ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ50 devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...
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... PIC18F46J50 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices RCSTA2 PIC18F2XJ50 PIC18F4XJ50 OSCTUNE PIC18F2XJ50 PIC18F4XJ50 T1GCON PIC18F2XJ50 PIC18F4XJ50 RTCVALH PIC18F2XJ50 PIC18F4XJ50 RTCVALL PIC18F2XJ50 PIC18F4XJ50 T3GCON PIC18F2XJ50 PIC18F4XJ50 (5) TRISE PIC18F2XJ50 PIC18F4XJ50 (5) TRISD PIC18F2XJ50 PIC18F4XJ50 TRISC PIC18F2XJ50 PIC18F4XJ50 TRISB ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ50 devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...
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... PIC18F46J50 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices PMMODEH PIC18F2XJ50 PIC18F4XJ50 PMMODEL PIC18F2XJ50 PIC18F4XJ50 PMDOUT2H PIC18F2XJ50 PIC18F4XJ50 PMDOUT2L PIC18F2XJ50 PIC18F4XJ50 PMDIN2H PIC18F2XJ50 PIC18F4XJ50 PMDIN2L PIC18F2XJ50 PIC18F4XJ50 PMEH PIC18F2XJ50 PIC18F4XJ50 PMEL PIC18F2XJ50 PIC18F4XJ50 PMSTATH PIC18F2XJ50 PIC18F4XJ50 PMSTATL ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ50 devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...
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... PIC18F46J50 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices RPOR10 PIC18F2XJ50 PIC18F4XJ50 RPOR9 PIC18F2XJ50 PIC18F4XJ50 RPOR8 PIC18F2XJ50 PIC18F4XJ50 RPOR7 PIC18F2XJ50 PIC18F4XJ50 RPOR6 PIC18F2XJ50 PIC18F4XJ50 RPOR5 PIC18F2XJ50 PIC18F4XJ50 RPOR4 PIC18F2XJ50 PIC18F4XJ50 RPOR3 PIC18F2XJ50 PIC18F4XJ50 RPOR2 PIC18F2XJ50 PIC18F4XJ50 RPOR1 ...
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... Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address returns all ‘0’s (a NOP instruction). The PIC18F46J50 Family offers a range of on-chip Flash program memory sizes, from 16 Kbytes (up to 8,192 single-word (32,768 single-word instructions). ...
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... CONFIG1 at the lowest address and ending with the upper byte of CONFIG4. Table 5-1 provides the actual addresses of the Flash Configuration Word for devices in the PIC18F46J50 Family. Figure 5-2 displays their location in the memory map with other memory vectors. Additional details on the device Configuration Words are provided in Section 26.1 “ ...
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... Microchip Technology Inc. PIC18F46J50 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer (SP), STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers (SFRs) ...
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... PIC18F46J50 FAMILY 5.1.4.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 5-1) contains the Stack Pointer value, the STKFUL (Stack Full) and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack ...
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... SUB1 • RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 5.1.6 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures or look-up tables in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... PIC18F46J50 FAMILY 5.2 PIC18 Instruction Cycle 5.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by ‘4’ to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the PC is incremented on every Q1; the instruction is fetched from the program memory and latched into the Instruction Register (IR) during Q4 ...
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... ADDWF © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... Access RAM. 5.3.1 USB RAM All 3.8 Kbytes of the GPRs implemented on the PIC18F46J50 Family devices can be accessed simul- taneously by both the microcontroller core and the Serial Interface Engine (SIE) of the USB module. The SIE uses a dedicated USB DMA engine to store any incoming data packets (OUT/SETUP) directly into main system data memory ...
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... FIGURE 5-6: DATA MEMORY MAP FOR PIC18F46J50 FAMILY DEVICES BSR3:BSR0 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh 00h = 0101 Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 Bank 7 ...
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... PIC18F46J50 FAMILY FIGURE 5-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) (1) BSR (2) Bank Select Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. ...
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... PMADDRx is used in Master modes and PMDOUTx is used in Slave modes. 5: Reserved: Do not write to this location. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY ALU’s STATUS register is described later in this section. Registers related to the operation of the peripheral features are described in the chapter for that peripheral. ...
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... PIC18F46J50 FAMILY TABLE 5-3: NON-ACCESS BANK SPECIAL FUNCTION REGISTER MAP Address Name Address Name F5Fh PMCONH F3Fh RTCCFG F5Eh PMCONL F3Eh RTCCAL F5Dh PMMODEH F3Dh REFOCON F5Ch PMMODEL F3Ch PADCFG1 F5Bh PMDOUT2H F3Bh F5Ah PMDOUT2L F3Ah F59h PMDIN2H F39h UCFG F58h ...
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... SFR address. The operating mode of the MSSP modules determines which register is being accessed. See Section 18.5.3.4 “7-Bit Address Masking Mode” for additional details. TABLE 5-4: REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) File Name Bit 7 Bit 6 Bit 5 TOSU — ...
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... PIC18F46J50 FAMILY TABLE 5-4: REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 FSR1H — — FSR1L Indirect Data Memory Address Pointer 1 Low Byte BSR — — INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) POSTINC2 Uses contents of FSR2 to address data memory – ...
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... TABLE 5-4: REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 ECCP1DEL P1RSEN P1DC6 P1DC5 CCPR1H Capture/Compare/PWM Register 1 HIgh Byte CCPR1L Capture/Compare/PWM Register 1 Low Byte CCP1CON P1M1 P1M0 DC1B1 PSTR2CON CMPL1 CMPL0 ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 ECCP2DEL P2RSEN ...
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... PIC18F46J50 FAMILY TABLE 5-4: REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 T3GCON TMR3GE T3GPOL T3GTM TRISE — — TRISD TRISD7 TRISD6 TRISD5 TRISC TRISC7 TRISC6 TRISC5 TRISB TRISB7 TRISB6 TRISB5 TRISA TRISA7 TRISA6 TRISA5 ALRMCFG ALRMEN CHIME ...
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... TABLE 5-4: REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 SSP2CON2 GCEN ACKSTAT ACKDT GCEN ACKSTAT ADMSK5 CMSTAT — — PMADDRH/ — CS1 Parallel Master Port Address High Byte (5) PMDOUT1H Parallel Port Out Data High Byte (Buffer 1) PMADDRL/ ...
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... PIC18F46J50 FAMILY TABLE 5-4: REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 ANCON1 VBGEN r (5) (5) ANCON0 PCFG7 PCFG6 PCFG5 ODCON1 — — ODCON2 — — ODCON3 — — RTCCFG RTCEN — RTCWREN RTCSYNC RTCCAL CAL7 CAL6 CAL5 REFOCON ROON — ...
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... TABLE 5-4: REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 RPINR3 — — RPINR2 — — RPINR1 — — (5) RPOR24 — — (5) RPOR23 — — (5) RPOR22 — — (5) RPOR21 — — (5) RPOR20 — — (5) RPOR19 — — RPOR18 — ...
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... PIC18F46J50 FAMILY 5.3.6 STATUS REGISTER The STATUS register in Register 5-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC bits, then the write to these five bits is disabled ...
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... Literal Address as their LSB. This address specifies either a register address in one of the banks of data RAM (Section 5.3.4 “General Purpose © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Register File”), or a location in the Access Bank (Section 5.3.3 “Access Bank”) as the data source for the instruction. ...
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... PIC18F46J50 FAMILY 5.4.3.1 FSR Registers and the INDF Operand (INDF) At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value ...
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... Thus, writing to INDF2 or POSTDEC2 will write the same value to the FSR2H:FSR2L. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses Indirect Addressing ...
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... PIC18F46J50 FAMILY 5.6.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair and its associated file operands. Under proper conditions, instructions that use the Access Bank, that is, most bit and byte-oriented instructions, can invoke a form of Indexed Addressing using an offset specified in the instruction ...
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... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 000h 060h Bank 0 100h Bank 1 through Bank 14 F00h ...
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... PIC18F46J50 FAMILY 5.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “ ...
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... Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... PIC18F46J50 FAMILY FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
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... Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-x R/W-0 FREE WRERR WREN U = Unimplemented bit, read as ‘ ...
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... PIC18F46J50 FAMILY 6.2.2 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT 8-bit register mapped into the Special Function Register (SFR) space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TABLE POINTER REGISTER ...
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... MOVF TABLAT, W MOVWF WORD_ODD © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... PIC18F46J50 FAMILY 6.4 Erasing Flash Program Memory The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 1024 bytes of program memory is erased ...
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... The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note 1: Unlike previous PIC the PIC18F46J50 Family do not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten sequence. ...
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... PIC18F46J50 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN BSF EECON1, FREE BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF ...
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... FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PRORAMMING). The PIC18F46J50 Family of devices has a feature that allows programming a single word (two bytes). This feature is enabled when the WPROG bit is set. If the memory location is already erased, the following sequence is required to enable this feature: 1 ...
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... PIC18F46J50 FAMILY 6.5.3 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 6.5.4 UNEXPECTED TERMINATION OF ...
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... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY EXAMPLE 7- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 7-2: ...
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... PIC18F46J50 FAMILY Example 7-3 provides the instruction sequence for unsigned multiplication. Equation 7-1 provides the algorithm that is used. The 32-bit result is stored in four registers (RES<3:0>). EQUATION 7- UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L · ARG2H:ARG2L 16 = (ARG1H · ARG2H · (ARG1H · ARG2L · 2 ...
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... INTERRUPTS Devices of the PIC18F46J50 Family have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-pri- ority level or a low-priority level. The high-priority inter- rupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in prog- ress ...
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... PIC18F46J50 FAMILY FIGURE 8-1: PIC18F46J50 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> DS39931C-page 110 TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF ...
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... Note 1: A mismatch condition will continue to set this bit. Reading PORTB and waiting 1 T condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
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... PIC18F46J50 FAMILY REGISTER 8-2: INTCON2: INTERRUPT CONTROL REGISTER 2 (ACCESS FF1h) R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
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... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 R/W-0 ...
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... PIC18F46J50 FAMILY 8.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ACCESS F9Eh) ...
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... No TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 R/W-0 USBIF BCL1IF HLVDIF U = Unimplemented bit, read as ‘0’ ...
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... PIC18F46J50 FAMILY REGISTER 8-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 (ACCESS FA4h) R/W-0 R/W-0 R-0 SSP2IF BCL2IF RC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) ...
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... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: These bits are unimplemented on 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘0’ ...
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... PIC18F46J50 FAMILY REGISTER 8-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ACCESS FA0h) R/W-0 R/W-0 R/W-0 OSCFIE CM2IE CM1IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CM2IE: Comparator 2 Interrupt Enable bit ...
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... Disabled bit 1 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 RTCCIE: RTCC Interrupt Enable bit 1 = Enabled 0 = Disabled © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 R/W-0 TX2IE TMR4IE CTMUIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 ...
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... PIC18F46J50 FAMILY 8.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
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... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-1 R/W-1 R/W-1 USBIP BCL1IP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC18F46J50 FAMILY REGISTER 8-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 (ACCESS FA5h) R/W-1 R/W-1 R/W-1 SSP2IP BCL2IP RC2IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority ...
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... For details on bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details on bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details on bit operation, see Register 4-1. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘0’ ...
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... PIC18F46J50 FAMILY 8.6 INTx Pin Interrupts External interrupts on the INT0, INT1, INT2 and INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the INTx pin, the corresponding flag bit and INTxIF are set ...
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... RD PORT Note 1: I/O pins have diode protection © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 9.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 9 ...
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... PIC18F46J50 FAMILY 9.1.3 INTERFACING SYSTEM Though the V of the PIC18F46J50 Family is DDMAX 3.6V, these devices are still capable of interfacing with 5V systems, even if the V of the target system is IH above 3.6V. This is accomplished by adding a pull-up resistor to the port pin (Figure 9-2), clearing the LAT bit ...
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... U2OD: USART2 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled bit 0 U1OD: USART1 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ...
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... PIC18F46J50 FAMILY REGISTER 9-3: ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3 (BANKED F40h) U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-2 Unimplemented: Read as ‘0’ bit 1 SPI2OD: SPI2 Open-Drain Output Enable bit ...
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... The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY EXAMPLE 9-2: INITIALIZING PORTA CLRF PORTA ...
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... PIC18F46J50 FAMILY TABLE 9-3: PORTA I/O SUMMARY TRIS Pin Function Setting RA0/AN0/C1INA/ RA0 1 ULPWU/RP0 0 AN0 1 C1INA 1 ULPWU 1 RP0 1 0 RA1/AN1/C2INA/ RA1 1 PMA7/RP1 0 AN1 1 C2INA 1 (1) PMA7 1 0 RP1 1 0 RA2/AN2/ RA2 0 V -/CV / REF REF C2INB 1 AN2 REF CV x REF C2INB I 0 RA3/AN3/V ...
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... CVRCON CVREN CVROE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: These bits are only available in 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY I/O I/O Type O DIG LATA<5> data output; not affected by analog input. ...
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... PIC18F46J50 FAMILY 9.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
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... Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default when PBADEN is set and digital inputs when PBADEN is cleared. 2: All other pin functions are disabled when ICSP™ or ICD are enabled. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY I/O I/O Type 1 TTL PORTB< ...
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... PIC18F46J50 FAMILY TABLE 9-5: PORTB I/O SUMMARY (CONTINUED) TRIS Pin Function Setting RB4/KBI0/ RB4 0 AN11/RP7/ 1 SCK1/SCL1 KBI0 1 AN11 1 RP7 1 0 SCK1 1 0 SCL1 1 0 RB5/KBI1/ RB5 0 SDI1/SDA1/ 1 RP8 KBI1 1 SDI1 1 SDA1 1 0 RP8 1 0 RB6/KBI2/ RB6 0 PGC/RP9 1 KBI2 1 PGC x RP9 1 0 RB7/KBI3/ ...
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... RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP ADCON0 PCFG7 PCFG6 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 LATB5 LATB4 ...
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... PIC18F46J50 FAMILY 9.4 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i ...
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... C/SMBus input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Enhanced PWM output is available only on PIC18F4XJ50 devices. 2: This bit is only available on 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY (1) I/O I/O Type I ST PORTC< ...
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... PIC18F46J50 FAMILY TABLE 9-7: PORTC I/O SUMMARY TRIS Pin Function Setting RC6/PMA5/ RC6 1 TX1/CK1/RP17 0 (2) 1 PMA5 0 TX1 0 CK1 1 0 RP17 1 0 RC7/RX1/DT1/ RC7 1 SDO1/RP18 0 RX1 1 DT1 1 0 SDO1 0 RP18 1 0 Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer; ANA = Analog level ...
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... Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer; I input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY EXAMPLE 9-5: CLRF PORTD ...
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... PIC18F46J50 FAMILY TABLE 9-9: PORTD I/O SUMMARY (CONTINUED) TRIS Pin Function Setting RD3/PMD3/ RD3 1 RP20 0 PMD3 1 0 RP20 1 0 RD4/PMD4/ RD4 1 RP21 0 PMD4 1 0 RP21 1 0 RD5/PMD5/ RD5 1 RP22 0 PMD5 1 0 RP22 1 0 RD6/PMD6/ RD6 1 RP23 0 PMD6 1 0 RP23 1 0 RD7/PMD7/ ...
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... PORTE, TRISE and LATE Registers Note: PORTE is available only in 44-pin devices. Depending on the particular PIC18F46J50 Family device selected, PORTE is implemented in two different ways. For 44-pin devices, PORTE is a 3-bit wide port. Three pins (RE0/AN5/PMRD, RE1/AN6/PMWR and RE2/ AN7/PMCS) are individually configurable as inputs or outputs ...
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... PIC18F46J50 FAMILY TABLE 9-11: PORTE I/O SUMMARY TRIS Pin Function Setting RE0/AN5/ RE0 1 PMRD 0 AN5 1 PMRD 1 0 RE1/AN6/ RE1 1 PMWR 0 AN6 1 PMWR 1 0 RE2/AN7/ RE2 1 PMCS 0 AN7 1 PMCS — — — — — — — DDCORE CAP DDCORE V — CAP — ...
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... I/O pins. The challenge is even greater on low pin count devices similar to the PIC18F46J50 Family application that needs to use more than one peripheral multiplexed on single pin, inconvenient workarounds in application code or a complete redesign may be the only option. ...
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... PIC18F46J50 FAMILY 9.7.3.1 Input Mapping The inputs of the PPS options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 9-6 through Register 9-20). ...
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... The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Because of the mapping technique, the list of peripherals for output mapping also includes a null value of ‘00000’. This permits any given pin to remain disconnected from the output of any of the pin selectable peripherals ...
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... PIC18F46J50 FAMILY 9.7.3.3 Mapping Limitations The control schema of the PPS is extremely flexible. Other than systematic blocks that prevent signal con- tention caused by two physical pins being configured as the same functional input or two functional outputs configured as the same pin, there are no hardware enforced lock outs ...
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... Example 9-7 provides a configuration for bidirectional communication with flow control using EUSART2. The following input and output functions are used: • Input Function RX2 • Output Function TX2 © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY EXAMPLE 9-7: CONFIGURING EUSART2 INPUT AND OUTPUT FUNCTIONS //************************************* ...
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... PIC18F46J50 FAMILY 9.7.6 PERIPHERAL PIN SELECT REGISTERS The PIC18F46J50 Family of devices implements a total of 37 registers for remappable peripheral configuration of 44-pin devices. The 28-pin devices have 31 registers for remappable peripheral configuration. REGISTER 9-5: PPSCON: PERIPHERAL PIN SELECT INPUT REGISTER 0 (BANKED EFFh) U-0 ...
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... Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 INTR3R<4:0>: Assign External Interrupt 3 (INT3) to the Corresponding RPn Pin bits © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-1 R/W-1 R/W-1 INTR1R4 INTR1R3 INTR1R2 U = Unimplemented bit, read as ‘0’ ...
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... PIC18F46J50 FAMILY REGISTER 9-9: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 (BANKED EEAh) U-0 U-0 U-0 — — — bit 7 Legend: R/W = Readable, Writable if IOLOCK = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T0CKR< ...
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... Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T3GR<4:0>: Timer3 Gate Input (T3G) to the Corresponding RPn Pin bits © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-1 R/W-1 R/W-1 IC2R4 IC2R3 IC2R2 U = Unimplemented bit, read as ‘0’ ...
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... PIC18F46J50 FAMILY REGISTER 9-15: RPINR16: PERIPHERAL PIN SELECT INPUT REGISTER 16 (BANKED EF6h) U-0 U-0 U-0 — — — bit 7 Legend: R/W = Readable, Writable if IOLOCK = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RX2DT2R< ...
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... Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 OCFAR<4:0>: Assign PWM Fault Input (FLT0) to the Corresponding RPn Pin bits © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-1 R/W-1 R/W-1 SCK2R4 SCK2R3 SCK2R2 U = Unimplemented bit, read as ‘0’ ...
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... PIC18F46J50 FAMILY REGISTER 9-21: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 (BANKED EC6h) U-0 U-0 U-0 — — — bit 7 Legend: R/W = Readable, Writable if IOLOCK = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP0R< ...
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... Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table 9-14 for peripheral function numbers) © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 R/W-0 RP3R4 RP3R3 RP3R2 U = Unimplemented bit, read as ‘ ...
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... PIC18F46J50 FAMILY REGISTER 9-27: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 (BANKED ECCh) U-0 U-0 U-0 — — — bit 7 Legend: R/W = Readable, Writable if IOLOCK = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R< ...
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... Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 9-14 for peripheral function numbers) © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 R/W-0 RP9R4 RP9R3 RP9R2 U = Unimplemented bit, read as ‘ ...
Page 158
... PIC18F46J50 FAMILY REGISTER 9-33: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 (BANKED ED2h) U-0 U-0 U-0 — — — bit 7 Legend: R/W = Readable, Writable if IOLOCK = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP12R< ...
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... Unimplemented: Read as ‘0’ bit 4-0 RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table 9-14 for peripheral function numbers) Note 1: RP20 pins are not available on 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 R/W-0 RP18R4 RP18R3 RP18R2 U = Unimplemented bit, read as ‘ ...
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... PIC18F46J50 FAMILY REGISTER 9-39: RPOR21: PERIPHERAL PIN SELECT OUTPUT REGISTER 21 (BANKED EDBh) U-0 U-0 U-0 — — — bit 7 Legend: R/W = Readable, Writable if IOLOCK = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP21R< ...
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... Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 9-14 for peripheral function numbers) Note 1: RP24 pins are not available on 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 R/W-0 RP24R4 RP24R3 RP24R2 U = Unimplemented bit, read as ‘ ...
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... PIC18F46J50 FAMILY NOTES: DS39931C-page 162 © 2009 Microchip Technology Inc. ...
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... Slave Port (PSP). FIGURE 10-1: PMP MODULE OVERVIEW PIC18 Parallel Master Port © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Key features of the PMP module are: • bits of addressing when using data/address multiplexing • Programmable Address Lines • One Chip Select Line • ...
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... PIC18F46J50 FAMILY 10.1 Module Registers The PMP module has a total of 14 Special Function Registers (SFRs) for its operation, plus one additional register to set configuration options. Of these, eight registers are used for control and six are used for PMP data transfer. 10.1.1 ...
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... Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: This register is only available in 44-pin devices. 2: These bits have no effect when their corresponding pins are used as address lines. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY (2) (2) U-0 R/W-0 — CS1P U = Unimplemented bit, read as ‘0’ ...
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... PIC18F46J50 FAMILY REGISTER 10-3: PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE (BANKED F5Dh) R-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 BUSY: Busy bit (Master mode only Port is busy 0 = Port is not busy bit 6-5 IRQM< ...
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... Wait Note 1: This register is only available in 44-pin devices. 2: WAITBx and WAITEx bits are ignored whenever WAITM<3:0> = 0000. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 WAITM2 WAITM1 WAITM0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ; multiplexed address phase ...
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... PIC18F46J50 FAMILY REGISTER 10-5: PMEH: PARALLEL PORT ENABLE REGISTER HIGH BYTE (BANKED F57h) R/W-0 R/W-0 R/W-0 PTEN15 PTEN14 PTEN13 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 PTEN<15:14>: PMCS1 Port Enable bits 1 = PMA<15:14> function as either PMA<15:14> or PMCS2 and PMCS1 0 = PMA< ...
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... OB3E:OB0E: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit Output buffer contains data that has not been transmitted Note 1: This register is only available in 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY U-0 R-0 R-0 — IB3F IB2F U = Unimplemented bit, read as ‘ ...
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... PIC18F46J50 FAMILY 10.1.2 DATA REGISTERS The PMP module uses eight registers for transferring data into and out of the microcontroller. They are arranged as four pairs to allow the option of 16-bit data operations: • PMDIN1H and PMDIN1L • PMDIN2H and PMDIN2L • PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L • ...
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... Bit is set bit 7-0 Parallel Master Port Address: Low Byte<7:0> bits Note 1: In Enhanced Slave mode, PMADDRL functions as PMDOUT1L, one of the Output Data Buffer registers. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY (1) R/W-0 R/W-0 R/W-0 Parallel Master Port Address High Byte<13:8> ...
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... PIC18F46J50 FAMILY 10.2 Slave Port Modes The primary mode of operation for the module is configured using the MODE<1:0> PMMODEH register. The setting affects whether the module acts as a slave or a master, and it determines the usage of the control pins. 10.2.1 LEGACY MODE (PSP) ...
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... PMRD PMD<7:0> IBF OBE PMPIF © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 10.2.3 READ FROM SLAVE PORT When chip select is active and a read strobe occurs (PMCS = 1 and PMRD = 1), the data from the PMDOUT1L register (PMDOUT1L<7:0>) is presented onto PMD<7:0>. Figure 10-4 provides the timing for the control signals in Read mode ...
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... PIC18F46J50 FAMILY 10.2.4 BUFFERED PARALLEL SLAVE PORT MODE Buffered Parallel Slave Port mode is functionally identical to the legacy PSP mode with one exception, the implementation of 4-level read and write buffers. Buffered PSP mode is enabled by setting the INCM bits in the PMMODEH register. If the INCM<1:0> bits are set to ‘ ...
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... ADDR<1:0>. Table 10-1 provides the corresponding FIGURE 10-7: PARALLEL SLAVE PORT READ WAVEFORMS PMCS PMWR PMRD PMD<7:0> PMA<1:0> OBE PMPIF © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY TABLE 10-1: SLAVE MODE BUFFER ADDRESSING Output PMA<1:0> Register (Buffer) PMDOUT1L (0) 00 PMDOUT1H (1) 01 ...
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... PIC18F46J50 FAMILY 10.2.5.2 WRITE TO SLAVE PORT When chip select is active and a write strobe occurs (PMCS = 1 and PMWR = 1), the data from PMD<7:0> is captured into one of the four input buffer bytes. Which byte is written depends on the 2-bit address placed on ADDRL<1:0>. Table 10-1 provides the corresponding input registers and their associated address ...
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... Configuration is controlled by separate bits in the PMCONL register. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Note that the polarity of control signals that share the same output pin (for example, PMWR and PMENB) are controlled by the same bit; the configuration depends on which Master Port mode is being used ...
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... PIC18F46J50 FAMILY FIGURE 10-9: DEMULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F FIGURE 10-10: PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F FIGURE 10-11: FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE ...
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... PMDIN1L register, and the second read data is placed into the PMDIN1H. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Note that the read data obtained from the PMDIN1L register is actually the read value from the previous read operation. Hence, the first user read will be a dummy read to initiate the first bus read and fill the read register ...
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... PIC18F46J50 FAMILY 10.3.11 MASTER MODE TIMING This section contains a number of timing examples that represent the common Master mode configuration options. These options vary from 8-bit to 16-bit data, fully demultiplexed to fully multiplexed address and Wait states. FIGURE 10-12: READ AND WRITE TIMING, 8-BIT DATA, DEMULTIPLEXED ADDRESS ...
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... PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMALL PMPIF BUSY WAITB<1:0> FIGURE 10-17: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE PMCS1 PMD<7:0> Address<7:0> PMRD/PMWR PMENB PMALL PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Data Data WAITE<1:0> WAITM<3:0> = 0010 Data ...
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... PIC18F46J50 FAMILY FIGURE 10-18: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE PMCS1 PMD<7:0> Address<7:0> PMRD/PMWR PMENB PMALL PMPIF BUSY FIGURE 10-19: READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS1 Address<7:0> PMD<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY FIGURE 10-20: ...
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... WRITE TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS PMCS1 PMD<7:0> PMA<7:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 10-23: READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMBE PMALL PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY LSB MSB LSB MSB LSB MSB ...
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... PIC18F46J50 FAMILY FIGURE 10-24: WRITE TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMBE PMALL PMPIF BUSY FIGURE 10-25: READ TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMBE PMALH PMALL PMPIF ...
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... PIC18F PMD<7:0> PMALL PMCS PMRD PMWR © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 10.4.1 MULTIPLEXED MEMORY OR PERIPHERAL Figure 10-27 demonstrates the hookup of a memory or another addressable peripheral in Full Multiplex mode. Consequently, this mode achieves the best pin saving from the microcontroller perspective. However, for this configuration, there needs to be some external latches to maintain the address ...
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... PIC18F46J50 FAMILY 10.4.3 PARALLEL EEPROM EXAMPLE Figure 10-30 provides an example connecting parallel EEPROM to the PMP. Figure 10-31 demonstrates a slight variation to this, configuring the connection for 16-bit data from a single EEPROM. FIGURE 10-30: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA) PIC18F PMA< ...
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... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. 2: These bits and/or registers are only available in 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 ...
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... PIC18F46J50 FAMILY NOTES: DS39931C-page 188 © 2009 Microchip Technology Inc. ...
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... Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. Figure 11-1 provides a simplified block diagram of the Timer0 module in 8-bit mode ...
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... PIC18F46J50 FAMILY 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
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... GIE/GIEH PEIE/GIEL TMR0IE T0CON TMR0ON T08BIT Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
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... PIC18F46J50 FAMILY NOTES: DS39931C-page 192 © 2009 Microchip Technology Inc. ...
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... The TMR1ON and TMR3ON bits do not have to be enabled to power up the crystal driver. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Figure 12-1 displays a simplified block diagram of the Timer1 module. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... PIC18F46J50 FAMILY 12.1 Timer1 Gate Control Register The Timer1 Gate Control register displayed in Register 12-2, is used to control the Timer1 gate. REGISTER 12-2: T1GCON: TIMER1 GATE CONTROL REGISTER (ACCESS F9Ah) R/W-0 R/W-0 R/W-0 TMR1GE T1GPOL T1GTM bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘ ...
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... ECCP1 and ECCP2 both use Timer3 (capture/compare) and Timer4 (PWM ECCP1 uses Timer1 (compare/capture) and Timer2 (PWM); ECCP2 uses Timer3 (capture/compare) and Timer4 (PWM ECCP1 and ECCP2 both use Timer1 (capture/compare) and Timer2 (PWM) © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R-0 U-0 U-0 T1RUN — ...
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... PIC18F46J50 FAMILY 12.2 Timer1 Operation The Timer1 module is an 8-bit or 16-bit incrementing counter, which is accessed TMR1H:TMR1L register pair. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module ...
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... T1OSO/T1CKI OUT T1OSC T1OSI EN T1OSCEN T1CKI Note 1: ST Buffer is high-speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY T1GSPM T1G_IN 0 Single Pulse Acq. Control T1GGO/T1DONE CK R TMR1ON ...
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... PIC18F46J50 FAMILY 12.4 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes. When the RD16 control bit (T1CON<1>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L loads the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register ...
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... Figure 12-3, may be helpful when used on a single-sided PCB or in addition to a ground plane. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY FIGURE 12-3: Note: Not drawn to scale. In the Low Drive Level mode, LPT1OSC = critical that the RC2 I/O pin signals be kept away from the oscillator circuit ...
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... PIC18F46J50 FAMILY 12.7 Resetting Timer1 Using the ECCP Special Event Trigger If ECCP1 or ECCP2 is configured to use Timer1 and to generate a Special Event Trigger in Compare mode (CCPxM<3:0> = 1011), this signal will reset Timer3. The trigger from ECCP2 will also start an A/D conver- sion if the A/D module is enabled (see Section 17.3.4 “ ...