PIC18LF2410-I/SO Microchip Technology, PIC18LF2410-I/SO Datasheet - Page 302

• Manufacturer Part Number: PIC18LF2410-I/SO
• Description: IC MCU FLASH 8KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2410-I/SO

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Interface: I2C, SPI, USART
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2X1X/4X1X
MOVSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (dest.)
Description
Words:
Cycles:
Example:
DS39636D-page 304
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Decode
FSR2
Contents
of 85h
Contents
of 86h
FSR2
Contents
of 85h
Contents
of 86h
Q1
source addr
Determine
Determine
dest addr
Move Indexed to Indexed
MOVSS [z
0 ≤ z
0 ≤ z
((FSR2) + z
None
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
7-bit literal offsets ‘z
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
The MOVSS instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h. If the
resultant destination address points to
an indirect addressing register, the
instruction will execute as a
2
2
MOVSS
1110
1111
Q2
=
=
=
=
=
=
s
d
≤ 127
≤ 127
80h
33h
11h
80h
33h
33h
[05h], [06h]
s
s
source addr
1011
xxxx
], [z
) → ((FSR2) + z
Determine
Determine
dest addr
d
Q3
]
s
’ or ‘z
1zzz
xzzz
d
source reg
to dest reg
’,
NOP
d
)
Read
Write
Q4
zzzz
zzzz
.
s
d
PUSHL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FSR2H:FSR2L
Memory (01ECh)
FSR2H:FSR2L
Memory (01ECh)
Q1
Store Literal at FSR2, Decrement FSR2
PUSHL k
0 ≤ k ≤ 255
k → (FSR2),
FSR2 – 1 → FSR2
None
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2
is decremented by 1 after the operation.
This instruction allows users to push values
onto a software stack.
1
1
1111
Read ‘k’
PUSHL
Q2
© 2009 Microchip Technology Inc.
1010
08h
=
=
=
=
Process
data
Q3
01ECh
01EBh
00h
08h
kkkk
destination
Write to
kkkk
Q4