PIC18LF2410-I/SO Microchip Technology, PIC18LF2410-I/SO Datasheet - Page 76

• Manufacturer Part Number: PIC18LF2410-I/SO
• Description: IC MCU FLASH 8KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2410-I/SO

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Interface: I2C, SPI, USART
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2X1X/4X1X
6.2
Two control registers are used in conjunction with the
TBLRD instruction: the TABLAT register and the
TBLPTR register set.
6.2.1
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
6.2.2
The Table Pointer register (TBLPTR) addresses a byte
within the program memory. It is comprised of three
SFR registers: Table Pointer Upper Byte, Table Pointer
High
(TBLPTRU:TBLPTRH:TBLPTRL). Only the lower six
bits of TBLPTRU are used with TBLPTRH and
TBLPTRL, to form a 22-bit wide pointer.
The contents of TBLPTR indicate a location in program
memory space. The low-order 21 bits allow the device
to address the full 2 Mbytes of program memory space.
The 22nd bit allows access to the configuration space,
including the Device ID, user ID locations and the
Configuration bits.
The TBLPTR register set is updated when executing a
TBLRD in one of four ways, based on the instruction’s
arguments. These are detailed in Table 6-1. These
operations on the TBLPTR only affect the low-order
21 bits.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
FIGURE 6-2:
DS39636D-page 78
Byte
Control Registers
Instruction Register
TABLAT – TABLE LATCH REGISTER
TBLPTR – TABLE POINTER
REGISTER
and
(IR)
READS FROM FLASH PROGRAM MEMORY
Table
Pointer
(Even Byte Address)
FETCH
Low
Program Memory
Byte
(Odd Byte Address)
TABLE 6-1:
6.3
The TBLRD instruction is used to retrieve data from
program memory and place it into data RAM. Table
reads from program memory are performed one byte at
a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-2
shows the interface between the internal program
memory and the TABLAT.
A typical method for reading data from program memory
is shown in Example 6-1.
TBLRD*+
TBLRD*-
TBLRD+*
Example
TBLRD*
TBLPTR = xxxxx1
TBLRD
Reading the Flash Program
Memory
TBLPTR is not modified
TBLPTR is incremented after the read
TBLPTR is decremented after the read
TBLPTR is incremented before the read
TABLE POINTER
OPERATIONS WITH TBLRD
INSTRUCTIONS
Operation on Table Pointer
© 2009 Microchip Technology Inc.
Read Register
TABLAT
TBLPTR = xxxxx0