ATMEGA328P-AU Atmel, ATMEGA328P-AU Datasheet - Page 12

• Manufacturer Part Number: ATMEGA328P-AU
• Description: MCU AVR 32K FLASH 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA328P-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Total Internal Ram Size: 2KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 1.8V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: TQFP
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA328P-20AU; ATMEGA328P-20AU; Q3790246

6.4.1
6.5
8271C–AVR–08/10
Stack Pointer
The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage. These reg-
isters are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in
Figure 6-3.
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. Note that the Stack is implemented as
growing from higher to lower memory locations. The Stack Pointer Register always points to the
top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine
and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer.
The Stack in the data SRAM must be defined by the program before any subroutine calls are
executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the
internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see
3 on page
See
Table 6-1.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
X-register
Y-register
Z-register
Instruction
PUSH
CALL
ICALL
RCALL
POP
RET
RETI
Table 6-1
18.
The X-, Y-, and Z-registers
Stack Pointer instructions
Stack pointer
Decremented by 1
Decremented by 2
Incremented by 1
Incremented by 2
for Stack Pointer details.
15
7
R27 (0x1B)
15
7
R29 (0x1D)
15
7
R31 (0x1F)
Description
Data is pushed onto the stack
Return address is pushed onto the stack with a subroutine call or
interrupt
Data is popped from the stack
Return address is popped from the stack with return from
subroutine or return from interrupt
XH
YH
ZH
0
0
0
7
R26 (0x1A)
7
R28 (0x1C)
7
R30 (0x1E)
Figure
6-3.
XL
YL
ZL
0
0
0
0
0
0
Table 7-
12