ATMEGA328P-AU Atmel, ATMEGA328P-AU Datasheet - Page 32

MCU AVR 32K FLASH 32TQFP

ATMEGA328P-AU

Manufacturer Part Number
ATMEGA328P-AU
Description
MCU AVR 32K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA328P-AU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
2KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA328P-20AU
ATMEGA328P-20AU
Q3790246

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9. Datasheet Revision History
9.1
9.2
9.3
Rev. 8271C – 08/10
Rev. 8271B-04/10
Rev. 8271A-12/09
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
1.
2.
3.
1.
2.
3.
4.
5.
1.
2
Updated the “SRAM Data Memory”,
Updated
“32CC1”
“32CC1”
Updated
Corrected use of SBIS instructions in assembly code examples.
Corrected BOD and BODSE bits to R/W in
and
Figures for bandgap characterization added,
374,
ure 29-269 on page
Updated
package.
New datasheet 8271 with merged information for ATmega48PA, ATmega88PA,
ATmega168PA and ATmega48A, ATmega88A andATmega168A. Also included
information on ATmega328 and ATmega328P
Changes done:
Section 13.4 on page 93
– New devices added: ATmega48A/ATmega88A/ATmega168A and
– Updated Feature Description
– Updated
– Added note for BOD Disable on
– Added note on BOD and BODSE in
– Added limitation informatin for the application
– Added limitiation information for
– Added specified DC characteristice per processor
– Added typical characteristics per processor
– Removed execption information in
Figure 29-128 on page
ATmega328
page 93
Read-While-Write Self-Programming” on page 279
page 296
Table 8-8
”Packaging Information” on page 546
Package drawing.
”Ordering Information” on page 15
Package drawing added on
and
Table 2-1 on page 6
with correct value for timer oscilliator at xtal2/tos2
474,
”Register Description” on page 294
Figure 29-316 on page 499
399,
Figure 29-175 on page
Figure 7-3 on page
”Packaging Information” on page
page
”Program And Data Memory Lock Bits” on
Section 9.11.2 on page
Figure 29-34 on page
”Address Match Unit” on page
by replacing 28M1 with a correct corresponding
”MCUCR – MCU Control Register” on
40.
with CCU and CCUR code related to
and
424,
Figure 29-363 on page
”Boot Loader Support –
Figure 29-222 on page
19.
45,
349,
Section 11.5 on page 69
Figure 29-81 on page
23.
223.
523.
449,
Fig-

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