DSPIC30F3013-30I/SO Microchip Technology, DSPIC30F3013-30I/SO Datasheet

IC DSPIC MCU/DSP 24K 28SOIC

DSPIC30F3013-30I/SO

Manufacturer Part Number
DSPIC30F3013-30I/SO
Description
IC DSPIC MCU/DSP 24K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3013-30I/SO

Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
30
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F301330ISO

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F3013-30I/SO
Manufacturer:
NSC
Quantity:
340
Part Number:
DSPIC30F3013-30I/SO
Manufacturer:
PIC
Quantity:
20 000
dsPIC30F Data Sheet
Motor Control and
Power Conversion Family
High Performance
Digital Signal Controllers
Preliminary
 2004 Microchip Technology Inc.
DS70082G

Related parts for DSPIC30F3013-30I/SO

DSPIC30F3013-30I/SO Summary of contents

Page 1

... Power Conversion Family  2004 Microchip Technology Inc. dsPIC30F Data Sheet Motor Control and High Performance Digital Signal Controllers Preliminary DS70082G ...

Page 2

... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... interrupt sources - 8 user selectable priority levels • Vector table with vectors - 54 interrupt vectors - 8 processor exceptions and software traps  2004 Microchip Technology Inc. dsPIC30F Peripheral Features: • High current sink/source I/O pins: 25 mA/25 mA • external interrupt sources • Timer module with programmable prescaler five 16-bit timers/counters ...

Page 4

... Low power consumption Output Motor EEPROM Timer Input Comp/Std Control Bytes 16-bit Cap PWM PWM 1024 1024 1024 1024 1024 1024 4096 Preliminary A/D 10-bit Quad 500 Ksps Enc 6 ch Yes Yes Yes Yes Yes Yes Yes  2004 Microchip Technology Inc. ...

Page 5

... Pin Diagrams 28-Pin QFN AN2/SS1/CN4/RB2 AN3/INDX/CN5 RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 OSC1/CLKIN OSC2/CLKO/RC15 Note: Pinout subject to change. See specific device data sheet for the most current design information.  2004 Microchip Technology Inc PWM2L/RE2 2 20 PWM2H/RE3 3 19 PWM3L/RE4 dsPIC30F2010 4 18 PWM3H/RE5 PGC/EMUC/U1RX/SDI1/SDA/RF2 15 Preliminary ...

Page 6

... PWM1L/RE0 26 4 PWM1H/RE1 PWM2L/RE2 6 PWM2H/RE3 23 7 PWM3L/RE4 PWM3H/RE5 9 DD OSC1/CLKI PGC/EMUC/U1RX/SDI1/SDA/RF2 18 12 PGD/EMUD/U1TX/SDO1/SCL/RF3 FLTA/INT0/SCK1/OCFA/RE8 EMUC2/OC1/IC1/INT1/RD0 1 MCLR REF +/CN2/RB0 REF -/CN3/RB1 26 PWM1L/RE0 4 25 PWM1H/RE1 5 24 PWM2L/RE2 6 PWM2H/RE3 23 7 PWM3L/RE4 PWM3H/RE5 9 OSC1/CLKI PGC/EMUC/U1RX/SDI1/SDA/C1RX/RF2 18 12 PGD/EMUD/U1TX/SDO1/SCL/C1TX/RF3 FLTA/INT0/SCK1/OCFA/RE8 EMUC2/OC1/IC1/INT1/RD0 Preliminary  2004 Microchip Technology Inc. ...

Page 7

... Note: Pinout subject to change. See specific device data sheet for the most current design information. 40-Pin PDIP EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 Note: Pinout subject to change. See specific device data sheet for the most current design information.  2004 Microchip Technology Inc. MCLR REF 2 39 +/CN2/RB0 AV REF ...

Page 8

... PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 Note: Pinout subject to change. See specific device data sheet for the most current design information. DS70082G-page EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 2 31 OSC2/CLKO/RC15 3 30 OSC1/CLKI dsPIC30F3011 AN8/RB8 7 26 AN7/RB7 8 25 AN6/OCFA/RB6 9 24 AN5/QEB/IC8/CN7/RB5 10 23 AN4/QEA/IC7/CN6/RB4 11 Preliminary  2004 Microchip Technology Inc. ...

Page 9

... Pin Diagrams (Continued) 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 Note: Pinout subject to change. See specific device data sheet for the most current design information.  2004 Microchip Technology Inc RF1 5 29 RF0 6 dsPIC30F3011 Preliminary dsPIC30F OSC2/CLKO/RC15 OSC1/CLKI AN8/RB8 AN7/RB7 ...

Page 10

... DD V PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 Note: Pinout subject to change. See specific device data sheet for the most current design information. DS70082G-page EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 32 2 OSC2/CLKO/RC15 31 3 OSC1/CLKIN dsPIC30F4011 AN8/RB8 27 7 AN7/RB7 8 26 AN6/OCFA/RB6 9 25 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 11 Preliminary  2004 Microchip Technology Inc. ...

Page 11

... Pin Diagrams (Continued) 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 CTX1/RF1 CRX1/RF0 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 Note: Pinout subject to change. See specific device data sheet for the most current design information.  2004 Microchip Technology Inc dsPIC30F4011 Preliminary dsPIC30F OSC2/CLKO/RC15 OSC1/CLKIN AN8/RB8 AN7/RB7 AN6/OCFA/RB6 ...

Page 12

... AN0/V REF +/CN2/RB0 16 Note: Pinout subject to change. See specific device data sheet for the most current design information. DS70082G-page 10 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 INT4/RD11 44 INT3/RD10 43 IC2/FLTB/INT2/RD9 42 IC1/FLTA/INT1/RD8 dsPIC30F5015 OSC2/CLKO/RC15 39 OSC1/CLKIN SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 Preliminary  2004 Microchip Technology Inc. ...

Page 13

... SDO2/CN10/RG8 9 MCLR 10 SS2/CN11/RG9 FLTA/INT1/RE8 14 FLTB/INT2/RE9 15 AN5/QEB/CN7/RB5 16 AN4/QEA/CN6/RB4 AN3/INDX/CN5/RB3 17 18 AN2/SS1/LVDIN/CN4/RB2 19 PGC/EMUC/AN1/CN3/RB1 20 PGD/EMUD/AN0/CN2/RB0 Note: Pinout subject to change. See specific device data sheet for the most current design information.  2004 Microchip Technology Inc dsPIC30F6010 Preliminary dsPIC30F EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 ...

Page 14

... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS70082G-page 12 Preliminary  2004 Microchip Technology Inc. ...

Page 15

... Digital Signal Processor (DSP) functionality within a high performance 16-bit microcontroller architecture.  2004 Microchip Technology Inc. Figure 1-1 shows a sample device block diagram. Note: The device(s) depicted in this block dia- gram are representative of the correspond- ing device family. Other devices of the same family may vary in terms of number of pins and multiplexing of pin functions ...

Page 16

... OC3/RD2 OC4/RD3 OC5/CN13/RD4 OC6/CN14/RD5 OC7/CN15/RD6 OC8/CN16/UPDN/RD7 IC1/RD8 IC2/RD9 IC3/RD10 IC4/RD11 IC5/RD12 IC6/CN19/RD13 IC7/CN20/RD14 IC8/CN21/RD15 PORTD PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 FLTA/INT1/RE8 FLTB/INT2/RE9 PORTE C1RX/RF0 C1TX/RF1 U1RX/RF2 U1TX/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 PORTF  2004 Microchip Technology Inc. ...

Page 17

... CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input  2004 Microchip Technology Inc. Description Analog input channels. AN0 and AN1 are also used for device programming data and clock inputs, respectively. Positive supply for analog module. Ground reference for analog module. ...

Page 18

... Synchronous serial clock input/output for I Synchronous serial data input/output for I 32 kHz low power oscillator crystal output. 32 kHz low power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Analog = Preliminary Analog input Output Power  2004 Microchip Technology Inc. ...

Page 19

... CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input  2004 Microchip Technology Inc. Description Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. UART1 Receive. UART1 Transmit. ...

Page 20

... NOTES: DS70082G-page 18 Preliminary  2004 Microchip Technology Inc. ...

Page 21

... Table read and write instructions can be used to access all 24 bits of an instruction word.  2004 Microchip Technology Inc. Overhead-free circular buffers (modulo addressing) are supported in both X and Y address spaces. This is pri- marily intended to remove the loop overhead for DSP algorithms ...

Page 22

... All results must be zero for the Z flag to remain set by the end of the sequence. All other instructions can set as well as clear the Z bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address instruction words. Preliminary  2004 Microchip Technology Inc. ...

Page 23

... AD39 DSP AccA Accumulators AccB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH  2004 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 0 ...

Page 24

... CY Fetch 1 1. MOV #0x55,W0 2. BTSC W1,#3 3. ADD W0,W1,W2 4. BRA SUB_1 5. SUB W0,W1,W3 6. Instruction @ address SUB_1 DS70082G-page Execute 1 Fetch 2 Execute 2 Fetch 3 Execute Execute 1 Fetch 2 Execute 2 Skip Taken Fetch 3 Flush Fetch 4 Preliminary Execute 4 Fetch 5 Flush Fetch SUB_1  2004 Microchip Technology Inc. ...

Page 25

... Figure 2-6. FIGURE 2-6: INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE GOTO, CALL Fetch 1 1. MOV #0x1234,W0 2. GOTO LABEL 2a.Second Word 3. Instruction @ address LABEL 4. BSET W1, #BIT3  2004 Microchip Technology Inc Execute 1 Fetch 2 Execute 2 R/W Cycle 1 ...

Page 26

... CY Fetch 1 1. MOV.b W0,[W1] 2. MOV.b [W1],PORTB 2a.Stall (NOP) 3. MOV.b W0,PORTB 8. Interrupt recognition execution. Section 5.0 for details on interrupts. DS70082G-page Execute 1 Fetch 2L NOP Fetch 2H Execute 2 Fetch Execute 1 Fetch 2 NOP Stall Execute 2 Fetch 3 Refer to Preliminary Execute Execute 3  2004 Microchip Technology Inc. ...

Page 27

... DIV.sd DIV.sw (or DIV.s) DIV.ud DIV.uw (or DIV.u)  2004 Microchip Technology Inc. The non-restoring divide algorithm requires one cycle for an initial dividend shift (for integer divides only), one cycle per divisor bit, and a remainder/quotient correc- tion cycle. The correction cycle is the last cycle of the ...

Page 28

... Automatic saturation on/off for AccB (SATB). 6. Automatic saturation on/off for writes to data memory (SATDW). 7. Accumulator Saturation (ACCSAT). Note: For CORCON layout, see Table 4-3. A block diagram of the DSP engine is shown in Figure 2-9. Preliminary  2004 Microchip Technology Inc. operations, which mode selection ...

Page 29

... FIGURE 2-9: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In  2004 Microchip Technology Inc. 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary dsPIC30F Round u Logic Zero Backfill DS70082G-page 27 ...

Page 30

... IF bit, the result must be explicitly shifted left by the user program after multiplication in order to obtain the correct result. Preliminary 1-N ). For fractional mode, a 16x16 mul- - -15 2 -30 , but has no other effect on the  2004 Microchip Technology Inc. ...

Page 31

... SB: AccB saturated (bit 31 overflow and saturation) or AccB overflowed into guard bits and saturated (bit 39 overflow and saturation)  2004 Microchip Technology Inc. 5. OAB: Logical and OB 6. SAB: Logical and SB The OA and OB bits are modified each time data passes through the adder/Subtractor ...

Page 32

... The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is pre- sented to the barrel shifter between bit positions for right shifts, and bit positions for left shifts. Preliminary  2004 Microchip Technology Inc. ...

Page 33

... Configuration Space Select Note: Program Space Visibility cannot be used to access bits <23:16> word in program memory.  2004 Microchip Technology Inc. User program space access is restricted to the lower 4M instruction word address range (0x000000 to 0x7FFFFE), for all accesses other than TBLRD/TBLWT, which use TBLPAG<7> to determine user or configura- tion space access ...

Page 34

... Byte: Read one of the MS Bytes of the program address; P<23:16> maps to the destination byte when byte select = 0; The destination byte will always when byte select = 1. 4. TBLWTH: Table Write High (refer to Section 6.0 for details on Flash Programming TBLRDL.B (Wn<0> TBLRDL.W TBLRDL.B (Wn<0> Preliminary 0  2004 Microchip Technology Inc. ...

Page 35

... The upper 8 bits should be programmed to force an illegal instruction to maintain machine robust- ness. Refer to the Programmer’s Reference Manual (DS70030) for details on instruction encoding.  2004 Microchip Technology Inc. TBLRDH TBLRDH.B (Wn<0> TBLRDH.B (Wn< ...

Page 36

... Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines the page in program space to which the upper half of data space is being mapped). DS70082G-page 34 Program Space 0x0000 (1) PSVPAG 0x21 8 0x8000 23 15 Address Concatenation 15 23 0xFFFF Preliminary  2004 Microchip Technology Inc. 0x108000 0 0x108200 0x10FFFF Data Read ...

Page 37

... Device Configuration Registers Reserved DEVID (2) Note: These address boundaries may vary from one device to another.  2004 Microchip Technology Inc. 3.2 Data Address Space The core has two data spaces. The data spaces can be 000000 considered either separate (for some DSP instruc- ...

Page 38

... W8 and W9. Both address spaces are concurrently accessed only with the MAC class instructions. An example data space memory map is shown in Figure 3-8. Preliminary DATA ALIGNMENT LS Byte 0000 Byte 1 Byte 0 Byte 3 Byte 2 0002 Byte 5 Byte 4 0004  2004 Microchip Technology Inc. ...

Page 39

... MSB is always clear. Note push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push.  2004 Microchip Technology Inc. 3.2.6 SOFTWARE STACK The dsPIC device contains a software stack. W15 is used as the Stack Pointer. ...

Page 40

... The address map shown is conceptual, and may vary across individual devices depending on available memory. DS70082G-page 38 LS Byte 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 0x1FFE Y Data RAM (Y) 0x27FE 0x2800 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space  2004 Microchip Technology Inc. ...

Page 41

... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA from any W  2004 Microchip Technology Inc. SFR SPACE UNUSED Y SPACE UNUSED MAC Class Ops (Read) Indirect EA from W8, W9 ...

Page 42

... DS70082G-page 40 Preliminary  2004 Microchip Technology Inc. ...

Page 43

... Microchip Technology Inc. Preliminary dsPIC30F DS70082G-page 41 ...

Page 44

... NOTES: DS70082G-page 42 Preliminary  2004 Microchip Technology Inc. ...

Page 45

... Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset  2004 Microchip Technology Inc. When executing instructions which require just one source operand to be fetched from data space, the X RAGU and X WAGU are used to calculate the effective address ...

Page 46

... DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. Preliminary  2004 Microchip Technology Inc. ...

Page 47

... Indirect Post-Modification Indirect with Pre- or Indirect with Pre- or Post-Modification Post-Modification  2004 Microchip Technology Inc. 4.3.2 RAW DEPENDENCY DETECTION During the instruction pre-decode, the core determines if any address register dependency is imminent across an instruction boundary. The stall detection logic com- pares the W register (if any) used for the destination EA ...

Page 48

... MODCON. Therefore, the instruction immediately following such a POP cannot be any instruction performing an indirect read operation should be noted that some instructions bytes, then the perform an indirect read operation implic- itly. These are: POP, RETURN, RETFIE, RETLW and ULNK. Preliminary  2004 Microchip Technology Inc. ...

Page 49

... Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words  2004 Microchip Technology Inc. The X Address Space Pointer W register (XWM) to which modulo addressing applied, is stored in MODCON<3:0> (see Table 3-3). Modulo addressing is enabled for X data space when XWM is set to any value other than 15 and the XMODEN bit is set at MODCON< ...

Page 50

... Section 4.4.1). For a decrementing buffer, the circular buffer end address is arbitrary, but must ‘ones’ boundary. There are no restrictions regarding how much an EA calculation can exceed the address boundary being checked and still be successfully corrected. Preliminary  2004 Microchip Technology Inc. ...

Page 51

... FIGURE 4-3: BIT-REVERSED ADDRESS EXAMPLE b15 b14 b13 b12 b11 b10 b9 b8 b15 b14 b13 b12 b11 b10 b9 b8  2004 Microchip Technology Inc. of successive 2. the BREN bit is set in the XBREV register and 3. the Addressing mode used is Register Indirect with Pre-Increment or Post-Increment. ...

Page 52

... Buffer Size (Words) 32768 16384 8192 4096 2048 1024 512 256 128 DS70082G-page 50 Decimal XB<14:0> Bit-Reversed Address Modifier Value Preliminary Bit-Reversed Address A0 Decimal 0x4000 0x2000 0x1000 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001  2004 Microchip Technology Inc. ...

Page 53

... The INTCON2 register controls the external inter- rupt request signal behavior and the use of the alternate vector table.  2004 Microchip Technology Inc. Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit ...

Page 54

... PWM - PWM Period Match 40 48 QEI - QEI Interrupt 41 49 Reserved 42 50 LVD - Low Voltage Detect 43 51 FLTA - PWM Fault FLTB - PWM Fault B 45-53 53-61 Reserved Lowest Natural Order Priority Preliminary  2004 Microchip Technology Inc. Interrupt Source 2 C Slave Interrupt 2 C Master Interrupt ...

Page 55

... Microchip Technology Inc. Note that many of these trap conditions can only be detected when they occur. Consequently, the question- able instruction is allowed to complete prior to trap exception processing ...

Page 56

... The proces- sor then loads the priority level for this interrupt into the status register. This action will disable all lower priority interrupts until the completion of the Interrupt Service Routine. Preliminary  2004 Microchip Technology Inc. ...

Page 57

... Interrupt 1 Vector — — — Interrupt 52 Vector Interrupt 53 Vector  2004 Microchip Technology Inc. 5.5 Alternate Vector Table In Program Memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Figure 5-2. Access to the Alternate Vector Table is provided by the ALTIVT bit in the INTCON2 register ...

Page 58

... DS70082G-page 56 Preliminary  2004 Microchip Technology Inc. ...

Page 59

... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select  2004 Microchip Technology Inc. 6.2 Run Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase and program 32 instructions (96 bytes time. ...

Page 60

... Write address of row to be erased into NVMADRU/NVMDR. c) Write ‘55’ to NVMKEY. d) Write ‘AA’ to NVMKEY. e) Set the WR bit. This will begin erase cycle. f) CPU will stall for the duration of the erase cycle. g) The WR bit is cleared when erase cycle ends. Preliminary  2004 Microchip Technology Inc. ...

Page 61

... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP  2004 Microchip Technology Inc. e) CPU will stall for duration of the program cycle. f) The WR bit is cleared by the hardware when program cycle ends. 6. Repeat steps 1 through 5 as needed to program desired amount of program Flash memory. ...

Page 62

... Write PM low word into program latch ; Write PM high byte into program latch ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ; Write PM low word into program latch ; Write PM high byte into program latch Preliminary  2004 Microchip Technology Inc. ...

Page 63

... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP  2004 Microchip Technology Inc. ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted ...

Page 64

... DS70082G-page 62 Preliminary  2004 Microchip Technology Inc. ...

Page 65

... Attempting to read the data EEPROM while a programming or erase operation is in progress results in unspecified data.  2004 Microchip Technology Inc. Control bit WR initiates write operations, similar to pro- gram Flash writes. This bit cannot be cleared, only set, in software. This bit is cleared in hardware at the com- pletion of the write operation ...

Page 66

... Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence Preliminary  2004 Microchip Technology Inc. ...

Page 67

... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete  2004 Microchip Technology Inc. The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...

Page 68

... EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together, help prevent an accidental write during brown-out, power glitch or software malfunction. Preliminary  2004 Microchip Technology Inc. ...

Page 69

... WR LAT + WR Port Read LAT Read Port  2004 Microchip Technology Inc. All port pins have three registers directly associated with the operation of the port pin. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input ...

Page 70

... NOP OL ) will be btss PORTB, #13 1 Output Enable 0 1 Output Data TRIS Latch Data Latch Preliminary PORT WRITE/READ EXAMPLE ; Configure PORTB<15:8> inputs ; and PORTB<7:0> as outputs ; Delay 1 cycle ; Next Instruction Output Multiplexers I/O Cell I/O Pad Input Data  2004 Microchip Technology Inc. ...

Page 71

... Microchip Technology Inc. Preliminary dsPIC30F DS70082G-page 69 ...

Page 72

... DS70082G-page 70 Preliminary  2004 Microchip Technology Inc. ...

Page 73

... CNPU1 00C4 CN7PUE CN6PUE CNPU2 00C6 — — Legend uninitialized bit Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.  2004 Microchip Technology Inc. Bit 13 Bit 12 Bit 11 Bit 10 CN13IE CN12IE CN11IE CN10IE — — — — ...

Page 74

... NOTES: DS70082G-page 72 Preliminary  2004 Microchip Technology Inc. ...

Page 75

... TGATE SOSCO/ T1CK LPOSCEN SOSCI  2004 Microchip Technology Inc. These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...

Page 76

... Low power • Real-Time Clock Interrupts These Operating modes are determined by setting the appropriate bit(s) in the T1CON Control register. FIGURE 9- pF 100K Preliminary RECOMMENDED COMPONENTS FOR TIMER1 LP OSCILLATOR RTC SOSCI 32.768 kHz dsPIC30FXXXX XTAL SOSCO R  2004 Microchip Technology Inc. ...

Page 77

... The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode.  2004 Microchip Technology Inc. 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective inter- rupt flag, T1IF, is asserted and an interrupt will be gen- erated, if enabled ...

Page 78

... DS70082G-page 76 Preliminary  2004 Microchip Technology Inc. ...

Page 79

... Timer3 interrupt flag (T3IF) and the interrupt is enabled with the Timer3 interrupt enable bit (T3IE).  2004 Microchip Technology Inc. 16-bit Mode: In the 16-bit mode, Timer2 and Timer3 can be configured as two independent 16-bit timers. Each timer can be set up in either 16-bit Timer mode or 16-bit Synchronous Counter mode ...

Page 80

... Timer configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70082G-page 78 16 TMR2 Sync LSB PR2 Q D TGATE(T2CON<6> TON 1 X Gate 0 1 Sync Preliminary TCKPS<1:0> 2 Prescaler 1, 8, 64, 256  2004 Microchip Technology Inc. ...

Page 81

... Equal Comparator x 16 Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK  2004 Microchip Technology Inc. PR2 TMR2 Q D TGATE Gate Sync PR3 Comparator x 16 TMR3 Q D TGATE ...

Page 82

... T3IE (IEC0<7>).. Note: In some devices, one or more of the TxCK pins may be absent. For these timers without the external clock input pin, the following modes should not be used: 1. TCS = 1 (16-bit counter) 2. TCS = 0, TGATE = 1 (gated time accumulation. Preliminary  2004 Microchip Technology Inc. ...

Page 83

... Microchip Technology Inc. Preliminary dsPIC30F DS70082G-page 81 ...

Page 84

... NOTES: DS70082G-page 82 Preliminary  2004 Microchip Technology Inc. ...

Page 85

... Note: Timer configuration bit T32, T4CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T4CON register.  2004 Microchip Technology Inc. The Timer4/5 module is similar in operation to the Timer 2/3 module. However, there are some differences, which are listed below: • ...

Page 86

... ADC Event Trigger Reset 0 T5IF Event Flag 1 TGATE T5CK DS70082G-page 84 PR4 TMR4 Q D TGATE Q CK TON 1 X Gate Sync PR5 Comparator x 16 TMR5 Q D TGATE Q CK Sync Preliminary Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256  2004 Microchip Technology Inc. ...

Page 87

... Microchip Technology Inc. Preliminary dsPIC30F DS70082G-page 85 ...

Page 88

... NOTES: DS70082G-page 86 Preliminary  2004 Microchip Technology Inc. ...

Page 89

... Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N.  2004 Microchip Technology Inc. The key operational features of the Input Capture module are: • Simple Capture Event mode • Timer2 and Timer3 mode selection • ...

Page 90

... The input capture interrupt flag is set on every edge, rising and falling. • The interrupt on Capture mode setting bits, ICI<1:0>, is ignored, since every capture generates an interrupt. • A capture overflow condition is not generated in this mode. Preliminary  2004 Microchip Technology Inc. ...

Page 91

... Sleep mode. The prescale settings of 4:1 or 16:1 are not applicable in this mode.  2004 Microchip Technology Inc. 12.2.2 INPUT CAPTURE IN CPU IDLE MODE CPU Idle mode allows input capture module operation with full functionality ...

Page 92

... DS70082G-page 90 Preliminary  2004 Microchip Technology Inc. ...

Page 93

... TMR3<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N.  2004 Microchip Technology Inc. The key operational features of the Output Compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...

Page 94

... FAULT condition has occurred. This state will be maintained until both of the following events have occurred: • The external FAULT condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits. Preliminary  2004 Microchip Technology Inc. ...

Page 95

... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic 0.  2004 Microchip Technology Inc. When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...

Page 96

... DS70082G-page 94 Preliminary  2004 Microchip Technology Inc. ...

Page 97

... Existing Pin Logic 0 UPDN Up/Down 1  2004 Microchip Technology Inc. The Quadrature Encoder Interface (QEI key fea- ture requirement for several motor control applications, such as Switched Reluctance (SR) and AC Induction Motor (ACIM). The operational features of the QEI are, but not limited to: • ...

Page 98

... Position counter reset by detection of index pulse, QEIM<2:0> = 110. 2. Position counter reset by match with MAXCNT, QEIM<2:0> = 111. The x4 Measurement mode provides for finer resolu- tion data (more position counts) for determining motor position. Preliminary  2004 Microchip Technology Inc. ...

Page 99

... Timer reg- ister. When UPDN = 1, the timer will count up. When UPDN = 0, the timer will count down.  2004 Microchip Technology Inc. In addition, control bit UPDN_SRC (QEICON<0>) determines whether the timer count direction state is based on the logic state, written into the UPDN control/ status bit (QEICON< ...

Page 100

... The QEIIF bit must be cleared in software. QEIIF is located in the IFS2 Status register. Enabling an interrupt is accomplished via the respec- tive enable bit, QEIIE. The QEIIE bit is located in the IEC2 Control register. Preliminary  2004 Microchip Technology Inc. ...

Page 101

... Microchip Technology Inc. Preliminary dsPIC30F DS70082G-page 99 ...

Page 102

... NOTES: DS70082G-page 100 Preliminary  2004 Microchip Technology Inc. ...

Page 103

... FEATURE SUMMARY: 6-OUTPUT PWM VS. 8-OUTPUT PWM Feature I/O Pins PWM Generators FAULT Input Pins Dead-Time Generators  2004 Microchip Technology Inc. • Single Pulse Generation mode • Interrupt support for asymmetrical updates in Center Aligned mode • Output override control for Electrically Commutative Motor (ECM) operation • ...

Page 104

... Channel 1 Dead-Time #1 Generator and Override Logic Special Event Postscaler SEVTDIR PTDIR Preliminary PWM4H PWM4L PWM3H Output Generator and PWM3L Override Logic Driver Block PWM2H Generator and PWM2L Override Logic PWM1H PWM1L FLTA FLTB Special Event Trigger  2004 Microchip Technology Inc. ...

Page 105

... PTPER Buffer PTCON Comparator SEVTDIR SEVTCMP PWM time base Note: Details of PWM Generator #1 and #2 not shown for clarity.  2004 Microchip Technology Inc. PWM Enable and Mode SFRs Dead-Time Control SFR FAULT Pin Control SFR PWM Manual Control SFR PWM Generator #3 ...

Page 106

... Second, asymmetrical cen- ter-aligned PWM waveforms can be generated, which are useful for minimizing output waveform distortion in certain motor control applications. Note: Programming a value of 0x0001 in the period register could generate a continu- ous interrupt pulse, and hence, must be avoided. Preliminary  2004 Microchip Technology Inc. ...

Page 107

... If the PWM time base is configured for one of the Up/ Down Count modes, the PWM period will be twice the value provided by Equation 15-1.  2004 Microchip Technology Inc. The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined using Equation 15-2: ...

Page 108

... The two dead-times can be assigned to individual PWM I/O pin pairs. This Operating mode allows the PWM module to drive different transistor/load combinations with each complementary PWM I/O pin pair. Preliminary  2004 Microchip Technology Inc. ...

Page 109

... No dead-time control is implemented between adjacent PWM I/O pins when the module is operating in the Independent mode and both I/O pins are allowed to be active simultaneously.  2004 Microchip Technology Inc. 15.7.3 DEAD-TIME RANGES The amount of dead-time provided by each dead-time unit is selected by specifying the input clock prescaler value and a 6-bit unsigned value ...

Page 110

... A special case exists when a PWM module I/O pair is in the Complementary mode and both pins are pro- grammed to be active on a FAULT condition. The PWMxH pin always has priority in the Complementary mode, so that both I/O pins cannot be driven active simultaneously. Preliminary  2004 Microchip Technology Inc. ...

Page 111

... PTPER. No duty cycle changes or period value changes will have effect while UDIS = 1.  2004 Microchip Technology Inc. 15.14 PWM Special Event Trigger The PWM module has a special event trigger that allows A/D conversions to be synchronized to the PWM time base ...

Page 112

... DS70082G-page 110 Preliminary  2004 Microchip Technology Inc. ...

Page 113

... SCL transitions while SPIROV is 1, effectively disabling the module until SPIxBUF is read by user software.  2004 Microchip Technology Inc. Transmit writes are also double buffered. The user writes to SPIxBUF. When the master or slave transfer is completed, the contents of the shift register (SPIxSR) is moved to the receive buffer ...

Page 114

... Clock Edge Control Select Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Preliminary Secondary Primary F CY Prescaler Prescaler 1,2,4,6 16, 64 SPI Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2  2004 Microchip Technology Inc. ...

Page 115

... Therefore, when the SSx pin is asserted low again, transmission/reception will begin at the MS bit, even if SSx had been de-asserted in the middle of a transmit/receive.  2004 Microchip Technology Inc. 16.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut-down. If ...

Page 116

... DS70082G-page 114 Preliminary  2004 Microchip Technology Inc. ...

Page 117

... I2CRCV is the receive buffer, as shown in Figure 16-1. I2CTRN is the transmit register to which bytes are writ- ten during a transmit operation, as shown in Figure 16-2.  2004 Microchip Technology Inc. 17.1 Operating Function Description The hardware fully implements all the master and slave functions of the I tions, as well as 7 and 10-bit addressing ...

Page 118

... Match Detect I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F OSC Preliminary Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read  2004 Microchip Technology Inc. ...

Page 119

... SCL high (see timing diagram). The inter- rupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master.  2004 Microchip Technology Inc. 17.3.2 SLAVE RECEPTION If the R_W bit received is a '0' during an address match, then Receive mode is initiated ...

Page 120

... This ensures that a write to the SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. Preliminary  2004 Microchip Technology Inc. ...

Page 121

... Generate a Stop condition on SDA and SCL. 2 • Configure the I C port to receive data. • Generate an ACK condition at the end of a received byte of data.  2004 Microchip Technology Inc. 2 17. Master Operation The master device generates all of the serial clock 2 C Slave Inter- pulses and the Start and Stop conditions ...

Page 122

... C OPERATION DURING CPU IDLE MODE 2 For the I C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle. Preliminary 2 C bus is free  2004 Microchip Technology Inc. ...

Page 123

... Microchip Technology Inc. Preliminary dsPIC30F DS70082G-page 121 ...

Page 124

... NOTES: DS70082G-page 122 Preliminary  2004 Microchip Technology Inc. ...

Page 125

... Internal Data Bus UTXBRK Data UxTX Parity Note  2004 Microchip Technology Inc. • One or two Stop bits • Fully integrated Baud Rate Generator with 16-bit prescaler • Baud rates range from 38 bps to 1.875 Mbps MHz instruction rate • 4-word deep transmit data buffer • ...

Page 126

... Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16X Baud Clock from Baud Rate Generator Preliminary Read Read Write UxMODE UxSTA Control Signals UxRXIF  2004 Microchip Technology Inc. ...

Page 127

... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (Power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented 1).  2004 Microchip Technology Inc. 18.3 Transmitting Data 18.3.1 TRANSMITTING IN 8-BIT DATA ...

Page 128

... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. Preliminary  2004 Microchip Technology Inc. RXB) X ...

Page 129

... No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not been received yet.  2004 Microchip Technology Inc. 18.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables this spe- cial mode, in which a 9th bit (URX8) value of ‘ ...

Page 130

... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode, or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. Preliminary  2004 Microchip Technology Inc. ...

Page 131

... Microchip Technology Inc. Preliminary dsPIC30F DS70082G-page 129 ...

Page 132

... NOTES: DS70082G-page 130 Preliminary  2004 Microchip Technology Inc. ...

Page 133

... Programmable link to Input Capture #2 (IC2) module for time-stamping and network synchronization • Low power Sleep and Idle mode  2004 Microchip Technology Inc. The CAN bus module consists of a protocol engine, and message buffering/control. The CAN protocol engine handles all functions for receiving and transmit- ting messages on the CAN bus ...

Page 134

... RXF2 A Acceptance Filter c RXF3 c Acceptance Filter e RXF4 p t Acceptance Filter RXF5 R M Identifier Data Field Receive RERRCNT Error Counter TERRCNT Transmit ErrPas Error BusOff Counter Protocol Finite State Machine Bit Timing Bit Timing Logic Generator (1) CiRX  2004 Microchip Technology Inc. ...

Page 135

... The I/O pins will revert to normal I/O function when the module is in the module disable mode.  2004 Microchip Technology Inc. The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...

Page 136

... These receive errors do not generate an interrupt. However, the receive error counter is incremented by one in case one of these errors occur. The RXWAR bit (CiINTF<9>) indicates that the Receive Error Counter has reached the CPU warning limit of 96 and an interrupt is generated. Preliminary  2004 Microchip Technology Inc. ...

Page 137

... If TXPRI<1:0> for a particular message buffer is set to ‘10’ or ‘01’, that buffer has an intermediate priority. If TXPRI<1:0> for a particular message buffer is ‘00’, that buffer has the lowest priority.  2004 Microchip Technology Inc. 19.5.3 TRANSMISSION SEQUENCE To initiate transmission of the message, the TXREQ bit (CiTXnCON< ...

Page 138

... definition, the Nominal Bit Time has a minimum and a maximum the minimum nominal bit time is 1 µsec, corresponding to a maximum bit rate of 1 MHz. Phase Phase Segment 1 Segment 2 Sample Point Preliminary Q . Also, by definition, Sync  2004 Microchip Technology Inc. ...

Page 139

... The following requirement must be fulfilled while setting the lengths of the Phase Segments: • Propagation Segment + Phase1 Seg > = Phase2 Seg  2004 Microchip Technology Inc. 19.6.5 SAMPLE POINT The Sample Point is the point of time at which the bus level is read and interpreted as the value of that respec- ...

Page 140

... DS70082G-page 138 Preliminary  2004 Microchip Technology Inc. ...

Page 141

... Microchip Technology Inc. Preliminary dsPIC30F DS70082G-page 139 ...

Page 142

... DS70082G-page 140 Preliminary  2004 Microchip Technology Inc. ...

Page 143

... Microchip Technology Inc. Preliminary dsPIC30F DS70082G-page 141 ...

Page 144

... NOTES: DS70082G-page 142 Preliminary  2004 Microchip Technology Inc. ...

Page 145

... The A/D converter has a unique feature of being able to operate while the device is in Sleep mode.  2004 Microchip Technology Inc. The A/D module has six 16-bit registers: • A/D Control Register1 (ADCON1) • A/D Control Register2 (ADCON2) • A/D Control Register3 (ADCON3) • ...

Page 146

... Note: Input multiplexer circuit will vary depending on the device selected. DS70082G-page 144 CH1 ADC S/H - 10-bit Result + CH2 S/H - 16-word, 10-bit + CH3 S/H CH1,CH2, - CH3,CH0 Sample/Sequence sample input switches + CH0 S/H - Preliminary  2004 Microchip Technology Inc. Conversion Logic Dual Port Buffer Control Input Mux Control ...

Page 147

... The channels are then converted sequentially. Obvi- ously, if there is only 1 channel selected, the SIMSAM bit is not applicable.  2004 Microchip Technology Inc. The CHPS bits selects how many channels are sam- pled. This can vary from channels. If CHPS selects 1 channel, the CH0 channel will be sampled at the sample clock and converted ...

Page 148

... The internal RC oscillator is selected by setting the ADRC bit. For correct A/D conversions, the A/D conversion clock must be selected to ensure a minimum T of 154 nsec (for V Preliminary AD wait The source of the AD . A/D CONVERSION CLOCK = T * (0.5*(ADCS<5:0> +1 time DD = 5V).  2004 Microchip Technology Inc. ...

Page 149

... Integer 0  2004 Microchip Technology Inc. If the A/D interrupt is enabled, the device will wake-up from Sleep. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set ...

Page 150

... Any external components connected (via high impedance analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. Preliminary DD SS and V as ESD the input voltage exceeds this  2004 Microchip Technology Inc. ...

Page 151

... Microchip Technology Inc. Preliminary dsPIC30F DS70082G-page 149 ...

Page 152

... NOTES: DS70082G-page 150 Preliminary  2004 Microchip Technology Inc. ...

Page 153

... In the Idle mode, the clock sources are still active, but the CPU is shut-off. The RC oscillator option saves system cost, while the LP crystal option saves power.  2004 Microchip Technology Inc. 21.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...

Page 154

... LP oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. 4: Some dsPIC30F devices do not have these oscillator options. Please refer to the specific device data sheet for details. DS70082G-page 152 Description (1) (2) (3) OSC /4 output (3) (4) (4) (4) Preliminary  2004 Microchip Technology Inc. (1) (1) (1) ...

Page 155

... OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI . Note: Paths indicated by dotted lines are not available on all devices. Please refer to the specific device data sheet for details.  2004 Microchip Technology Inc. PLL F PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator ...

Page 156

... PLL multiplier (respectively) is applied. Note: When a 16x PLL is used, the FRC frequency must not be tuned to a frequency greater than 7.5 MHz. Preliminary PLL FREQUENCY RANGE PLL Fout Multiplier x4 16 MHz-40 MHz x8 32 MHz-80 MHz x16 64 MHz-160 MHz  2004 Microchip Technology Inc. ...

Page 157

... Note that OSC1 pin cannot be used as an I/O pin, even if the secondary oscillator or an internal clock source is selected at all times.  2004 Microchip Technology Inc. 21.2.7 FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure ...

Page 158

... Byte Write “0x78” to OSCCON high • Byte Write “0x9A” to OSCCON high Byte Write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. Preliminary  2004 Microchip Technology Inc. ...

Page 159

... Reset state. The POR also selects the device clock source identified by the oscil- lator configuration fuses.  2004 Microchip Technology Inc. Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected by a WDT wake-up, since this is viewed as the resump- tion of normal operation ...

Page 160

... INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70082G-page 158 T OST T PWRT T OST PWRT T OST T PWRT T Preliminary ) DD ): CASE CASE 2 DD  2004 Microchip Technology Inc. ...

Page 161

... The BOR voltage trip points indicated here are nominal values provided for design guidance only.  2004 Microchip Technology Inc. A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source, based on the device configuration bit values (FOS<1:0> and FPR< ...

Page 162

... When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70082G-page 160 TRAPR IOPUWR EXTR SWR WDTO ( TRAPR IOPUWR EXTR SWR WDTO ( Preliminary Idle Sleep POR BOR Idle Sleep POR BOR  2004 Microchip Technology Inc. ...

Page 163

... In some devices, the LVD threshold voltage may be applied externally on the LVDIN pin. The LVD module is enabled by setting the LVDEN bit (RCON<12>).  2004 Microchip Technology Inc. 21.6 Power Saving Modes There are two power saving states that can be entered through the execution of a special instruction, PWRSAV. ...

Page 164

... For additional information, please refer specifications of the device. Note: If the code protection configuration fuse bits (FGS<GCP> and FGS<GWRP>) have been programmed, an erase of the entire code-protected device is only possible at voltages V Preliminary to the programming ≥ 4.5V. DD  2004 Microchip Technology Inc. ...

Page 165

... To use the In-Circuit Debugger function of the device, the design must implement ICSP connections to MCLR, V PGC, PGD, and the selected EMUDx/EMUCx pin pair.  2004 Microchip Technology Inc. This gives rise to two possibilities EMUD/EMUC is selected as the Debug I/O pin ...

Page 166

... DS70082G-page 164 Preliminary  2004 Microchip Technology Inc. ...

Page 167

... The file register specified by the value ’f’ • The destination, which could either be the file register ’f’ or the W0 register, which is denoted as ’WREG’  2004 Microchip Technology Inc. Most bit oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ’ ...

Page 168

... Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the Programmer’s Reference Manual. Description Preliminary  2004 Microchip Technology Inc. ...

Page 169

... Y data space pre-fetch address register for DSP instructions Wy ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space pre-fetch destination register for DSP instructions ∈ {W4..W7} Wyd  2004 Microchip Technology Inc. Description Preliminary dsPIC30F DS70082G-page 167 ...

Page 170

... Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Preliminary  2004 Microchip Technology Inc Status Flags words cycles Affected 1 1 OA,OB,SA, ...

Page 171

... Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd  2004 Microchip Technology Inc. Description Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws<Wb> Bit Test then Set f Bit Test then Set Bit Test then Set ...

Page 172

... Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd+1, Wnd} = unsigned(Wb) * unsigned(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(lit5) {Wnd+1, Wnd} = unsigned(Wb) * unsigned(lit5) W3: WREG Preliminary  2004 Microchip Technology Inc Status Flags words cycles Affected 1 1 OA,OB,OAB, SA,SB,SAB ...

Page 173

... SFTAC Acc,#Slit6 f,WREG SL Ws,Wd SL Wb,Wns,Wnd SL Wb,#lit5,Wnd  2004 Microchip Technology Inc. Description Negate Accumulator WREG = Operation No Operation Pop f from top-of-stack (TOS) Pop from top-of-stack (TOS) to Wdo Pop from top-of-stack (TOS) to W(nd):W(nd+1) Pop Shadow Registers Push f to top-of-stack (TOS) ...

Page 174

... Wn = byte swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink frame pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-Extend Ws Preliminary  2004 Microchip Technology Inc Status Flags words cycles Affected 1 1 OA,OB,OAB, SA,SB,SAB 1 1 ...

Page 175

... PICDEM MSC ® - microID - CAN ® - PowerSmart - Analog  2004 Microchip Technology Inc. 23.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...

Page 176

... MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high speed simulator is designed to debug, analyze and optimize time intensive DSP routines. Preliminary  2004 Microchip Technology Inc. economical software ...

Page 177

... The PC platform and Microsoft Windows 32-bit operating system were cho- sen to best make these features available in a simple, unified application.  2004 Microchip Technology Inc. 23.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low cost, run-time development tool, connecting to the host PC via an RS-232 or high speed USB interface ...

Page 178

... PICSTART Plus development pro- grammer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board FLASH memory. A generous prototype area is available for user hardware expansion. Preliminary  2004 Microchip Technology Inc. ...

Page 179

... Microcontrollers" Handbook and a USB Interface Cable. Supports all current 8/14-pin FLASH PIC microcontrollers, as well as many future planned devices.  2004 Microchip Technology Inc. 23.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...

Page 180

... NOTES: DS70082G-page 178 Preliminary  2004 Microchip Technology Inc. ...

Page 181

... Exposure to maximum rating conditions for extended periods may affect device reliability. Note: All peripheral electrical characteristics are specified. For exact peripherals available on specific devices, please refer the the Family Cross Reference Table.  2004 Microchip Technology Inc. DD (except V and MCLR) ................................................... -0. (Note 1) ...

Page 182

... RAM data. Preliminary dsPIC30FXXX-20E 20 — — — — 15 — -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Units Conditions V Industrial temperature V Extended temperature V V V/ms 0-5V in 0.1 sec 0-  2004 Microchip Technology Inc. ...

Page 183

... WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating. 3: Data is provided for the dsPIC30F6010 device. Other devices will have different I specific device data sheet for details.  2004 Microchip Technology Inc Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...

Page 184

... DD measurements are as follows: OSC1 Preliminary 20 MIPS EC mode, 8X PLL 16 MIPS EC mode, 16X PLL 30 MIPS EC mode, 16X PLL FRC (~ 2 MIPS values. Refer to the  2004 Microchip Technology Inc. ...

Page 185

... WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating. 3: Data is provided for the dsPIC30F6010 device. Other devices will have different I specific device data sheet for details.  2004 Microchip Technology Inc. ) (CONTINUED) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...

Page 186

... Preliminary 1 MIPS EC mode 4 MIPS EC mode, 4X PLL 10 MIPS EC mode, 4X PLL 8 MIPS EC mode, 8X PLL DD values. Refer to the  2004 Microchip Technology Inc. ...

Page 187

... Core off, Clock on and all modules turned off. 3: Data is provided for the dsPIC30F6010 device. Other devices will have different I specific device data sheet for details.  2004 Microchip Technology Inc. ) (CONTINUED) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...

Page 188

... Preliminary ) PD (3) Base Power Down Current (3) Watchdog Timer Current: ∆I WDT (3) Timer 1 w/32 kHz Crystal: ∆ BOR (3) BOR On: ∆I  2004 Microchip Technology Inc. ...

Page 189

... LVD, BOR, WDT, etc. are all switched off. The ∆ current is the additional current consumed when the module is enabled. This current should added to the base I current.  2004 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial A Operating temperature -40° ...

Page 190

... SM bus enabled bus disabled V SM bus enabled µA DD PIN 5V µA DD PIN 3V µA ≤ V ≤ PIN Pin at hi-impedance µA ≤ V ≤ PIN DD , Pin at hi-impedance µA ≤ V ≤ PIN DD V µA ≤ V ≤ PIN XT, HS and LP Osc mode  2004 Microchip Technology Inc. ...

Page 191

... These parameters are characterized but not tested in manufacturing. FIGURE 24-1: LOW-VOLTAGE DETECT CHARACTERISTICS DD V LV10 LVDIF (LVDIF set by hardware)  2004 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) Min Typ ...

Page 192

... V — — V — — V — 2.65 V — 2.86 V — 2.97 V — 3.18 V — 3.50 V — 3.71 V — 3.82 V — 4.03 V — 4.24 V — 4.45 V — 4.77 V — — V (Device not in Brown-out Reset) Power Up Time-out  2004 Microchip Technology Inc. ...

Page 193

... DD During Programming Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing.  2004 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...

Page 194

... DC Spec Section 24.0. Load Condition 2 – for OSC2 Pin 464 Ω for all pins except OSC2 for OSC2 output OS20 OS30 OS30 OS25 OS40 Preliminary ≤ +85°C for Industrial A ≤ +125°C for Extended OS31 OS31 OS41  2004 Microchip Technology Inc. ...

Page 195

... Measurements are taken ERC modes. The CLKOUT signal is measured on the OSC2 pin. CLKOUT is low for the Q1-Q2 period (1/2 T  2004 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...

Page 196

... Industrial A ≤ +125°C for Extended A Conditions DD -40°C to +85° 3.3V DD -40°C to +85° -40°C to +85° -40°C to +85°  2004 Microchip Technology Inc. ...

Page 197

... Measurements are taken in RC mode and EC mode where CLKOUT output These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated.  2004 Microchip Technology Inc. DI35 DI40 New Value DO31 DO32 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...

Page 198

... TIMER TIMING CHARACTERISTICS DD V SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins SY35 FSCM Delay Note: Refer to Figure 24-3 for load conditions. DS70082G-page 196 SY10 SY20 SY13 Preliminary  2004 Microchip Technology Inc. SY13 ...

Page 199

... BGAP Band Gap Start-up Time Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.  2004 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) Min ...

Page 200

... Extended A Max Units Conditions — ns Must also meet parameter TA15 — ns — ns — ns Must also meet parameter TA15 — ns — ns — ns — — prescale value (1, 8, 64, 256) — kHz OSC 6 T —  2004 Microchip Technology Inc. ...

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