DSPIC30F3013-30I/SO Microchip Technology, DSPIC30F3013-30I/SO Datasheet - Page 134

IC DSPIC MCU/DSP 24K 28SOIC

DSPIC30F3013-30I/SO

Manufacturer Part Number
DSPIC30F3013-30I/SO
Description
IC DSPIC MCU/DSP 24K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3013-30I/SO

Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
30
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F301330ISO

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F3013-30I/SO
Manufacturer:
NSC
Quantity:
340
Part Number:
DSPIC30F3013-30I/SO
Manufacturer:
PIC
Quantity:
20 000
dsPIC30F2011/2012/3012/3013
Any interrupt that is individually enabled (using the
corresponding IE bit) and meets the prevailing priority
level will be able to wake-up the processor. The
processor will process the interrupt and branch to the
ISR. The Sleep Status bit in the RCON register is set
upon wake-up.
All Resets will wake-up the processor from Sleep
mode. Any Reset, other than POR, will set the Sleep
Status bit. In a POR, the Sleep bit is cleared.
If the Watchdog Timer is enabled, then the processor
will wake-up from Sleep mode upon WDT time-out. The
Sleep and WDTO Status bits are both set.
17.6.2
In Idle mode, the clock to the CPU is shut down while
peripherals keep running. Unlike Sleep mode, the clock
source remains active.
Several peripherals have a control bit in each module
that allows them to operate during Idle.
LPRC Fail-Safe Clock remains active if clock failure
detect is enabled.
The processor wakes up from Idle if at least one of the
following conditions has occurred:
• any interrupt that is individually enabled (IE bit is
• any Reset (POR, BOR, MCLR)
• WDT time-out
Upon wake-up from Idle mode, the clock is re-applied
to the CPU and instruction execution begins
immediately, starting with the instruction following the
PWRSAV instruction.
DS70139G-page 134
Note:
‘1’) and meets the required priority level
In spite of various delays applied (T
T
(and PLL) may not be active at the end of
the time-out (e.g., for low-frequency
crystals). In such cases, if FSCM is
enabled, then the device will detect this as
a clock failure and process the clock failure
trap, the FRC oscillator will be enabled and
the user will have to re-enable the crystal
oscillator. If FSCM is not enabled, then the
device will simply suspend execution of
code until the clock is stable and will remain
in Sleep until the oscillator clock has
started.
IDLE MODE
LOCK
and T
PWRT
), the crystal oscillator
POR
,
Any interrupt that is individually enabled (using IE bit)
and meets the prevailing priority level will be able to
wake-up the processor. The processor will process the
interrupt and branch to the ISR. The Idle Status bit in
the RCON register is set upon wake-up.
Any Reset other than POR will set the Idle Status bit.
On a POR, the Idle bit is cleared.
If Watchdog Timer is enabled, then the processor will
wake-up from Idle mode upon WDT time-out. The Idle
and WDTO Status bits are both set.
Unlike wake-up from Sleep, there are no time delays
involved in wake-up from Idle.
17.7
The Configuration bits in each device Configuration
register specify some of the device modes and are
programmed by a device programmer, or by using the
In-Circuit Serial Programming™ (ICSP™) feature of
the device. Each device Configuration register is a
24-bit register, but only the lower 16 bits of each
register are used to hold configuration data. There are
five device Configuration registers available to the
user:
1.
2.
3.
4.
5.
The
automatically handled when you select the device in
your device programmer. The desired state of the
Configuration bits may be specified in the source code
(dependent on the language tool used), or through the
programming interface. After the device has been
programmed, the application software may read the
Configuration bit values through the table read
instructions. For additional information, please refer to
the Programming Specifications of the device.
Note:
FOSC (0xF80000): Oscillator Configuration
Register
FWDT (0xF80002): Watchdog Timer
Configuration Register
FBORPOR (0xF80004): BOR and POR
Configuration Register
FGS (0xF8000A): General Code Segment
Configuration Register
FICD (0xF8000C): Debug Configuration
Register
placement
Device Configuration Registers
If the code protection Configuration fuse
bits (FGS<GCP> and FGS<GWRP>)
have been programmed, an erase of the
entire code-protected device is only
possible at voltages V
of
© 2010 Microchip Technology Inc.
the
Configuration
DD
≥ 4.5V.
bits
is

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