DSPIC30F3013-30I/SO Microchip Technology, DSPIC30F3013-30I/SO Datasheet - Page 67

• Manufacturer Part Number: DSPIC30F3013-30I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3013-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301330ISO

8.2
A Reset is not a true exception because the interrupt
controller is not involved in the Reset process. The
processor initializes its registers in response to a Reset
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory
location immediately followed by the address target for
the GOTO instruction. The processor executes the GOTO
to the specified address and then begins operation at
the specified target (start) address.
8.2.1
In addition to external Reset and Power-on Reset
(POR), there are six sources of error conditions which
‘trap’ to the Reset vector.
• Watchdog Time-out:
• Uninitialized W Register Trap:
• Illegal Instruction Trap:
• Brown-out Reset (BOR):
• Trap Lockout:
© 2010 Microchip Technology Inc.
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
An attempt to use an uninitialized W register as
an Address Pointer causes a Reset.
Attempted execution of any unused opcodes
results in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
A momentary dip in the power supply to the
device has been detected which may result in
malfunction.
Occurrence of multiple trap conditions
simultaneously causes a Reset.
Reset Sequence
RESET SOURCES
dsPIC30F2011/2012/3012/3013
8.3
Traps can be considered as non-maskable interrupts
indicating a software or hardware error, which adhere
to a predefined priority as shown in
are intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.
Note that many of these trap conditions can only be
detected
questionable instruction is allowed to complete prior to
trap exception processing. If the user chooses to
recover from the error, the result of the erroneous
action that caused the trap may have to be corrected.
There are eight fixed priority levels for traps: Level 8
through Level 15, which implies that the IPL3 is always
set during processing of a trap.
If the user is not currently executing a trap, and he sets
the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
8.3.1
The following traps are provided with increasing
priority. However, since all traps can be nested, priority
has little effect.
Math Error Trap:
The math error trap executes under the following four
circumstances:
1.
2.
3.
4.
Note:
If an attempt is made to divide by zero, the
divide operation is aborted on a cycle boundary
and the trap is taken.
If enabled, a math error trap is taken when an
arithmetic operation on either accumulator A or
B causes an overflow from bit 31 and the
accumulator guard bits are not utilized.
If enabled, a math error trap is taken when an
arithmetic operation on either accumulator A or
B causes a catastrophic overflow from bit 39 and
all saturation is disabled.
If the shift amount specified in a shift instruction
is greater than the maximum allowed shift
amount, a trap occurs.
Traps
when
If the user does not intend to take
corrective action in the event of a trap
error condition, these vectors must be
loaded with the address of a default
handler that contains the RESET instruc-
tion. If, on the other hand, one of the vec-
tors containing an invalid address is
called, an address error trap is generated.
TRAP SOURCES
they
occur.
Consequently,
DS70139G-page 67
Figure
8-1. They
the