DSPIC30F3013-30I/SO Microchip Technology, DSPIC30F3013-30I/SO Datasheet - Page 97

IC DSPIC MCU/DSP 24K 28SOIC

DSPIC30F3013-30I/SO

Manufacturer Part Number
DSPIC30F3013-30I/SO
Description
IC DSPIC MCU/DSP 24K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3013-30I/SO

Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
30
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F301330ISO

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F3013-30I/SO
Manufacturer:
NSC
Quantity:
340
Part Number:
DSPIC30F3013-30I/SO
Manufacturer:
PIC
Quantity:
20 000
14.0
The Inter-Integrated Circuit (I
complete hardware support for both Slave and
Multi-Master modes of the I
standard, with a 16-bit interface.
This module offers the following key features:
• I
• I
• I
• I
• Serial clock synchronization for I
• I
14.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7 and 10-bit addressing.
Thus, the I
a master on an I
FIGURE 14-1:
© 2010 Microchip Technology Inc.
Note:
operation.
addressing.
addressing.
master and slaves.
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
collision and will arbitrate accordingly.
2
2
2
2
2
C interface supporting both master and slave
C Slave mode supports 7-bit and 10-bit
C Master mode supports 7-bit and 10-bit
C port allows bidirectional transfers between
C supports multi-master operation; detects bus
I
Operating Function Description
2
2
C™ MODULE
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
C module can operate either as a slave or
2
C bus.
2
C Standard and Fast mode
PROGRAMMER’S MODEL
Bit 15
Bit 15
2
C serial communication
2
C
TM
2
) module provides
C port can be
dsPIC30F2011/2012/3012/3013
Bit 9
Bit 8
Bit 7
Bit 7
14.1.1
The following types of I
• I
• I
• I
See the I
14.1.2
I
SDA pin is data.
14.1.3
I2CCON and I2CSTAT are control and status registers,
respectively. The I2CCON register is readable and
writable. The lower 6 bits of I2CSTAT are read-only.
The remaining bits of the I2CSTAT are read/write.
I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CRCV is the receive buffer as shown in
I2CTRN is the transmit register to which bytes are
written during a transmit operation, as shown in
Figure
The I2CADD register holds the slave address. A Status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the Baud Rate Generator reload
value.
In receive operations, I2CRSR and I2CRCV together
form a double-buffered receiver. When I2CRSR
receives a complete byte, it is transferred to I2CRCV
and
transmission, the I2CTRN is not double-buffered.
2
C has a 2-pin interface; the SCL pin is clock and the
Note:
2
2
2
C slave operation with 7-bit addressing
C slave operation with 10-bit addressing
C master operation with 7-bit or 10-bit addressing
an
14-2.
2
C programmer’s model
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
interrupt
VARIOUS I
PIN CONFIGURATION IN I
I
Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
2
C REGISTERS
I2CRCV (8 bits)
I2CTRN (8 bits)
I2CBRG (9 bits)
I2CCON (16 bits)
I2CSTAT (16 bits)
I2CADD (10 bits)
pulse
2
C operation are supported:
2
C MODES
is
(Figure
generated.
DS70139G-page 97
14-1).
2
Figure
C MODE
During
14-1.

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