IC DSPIC MCU/DSP 6K 28SOIC

DSPIC30F1010-30I/SO

Manufacturer Part NumberDSPIC30F1010-30I/SO
DescriptionIC DSPIC MCU/DSP 6K 28SOIC
ManufacturerMicrochip Technology
SeriesdsPIC™ 30F
DSPIC30F1010-30I/SO datasheets
 

Specifications of DSPIC30F1010-30I/SO

Core ProcessordsPICCore Size16-Bit
Speed30 MIPsConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o21
Program Memory Size6KB (2K x 24)Program Memory TypeFLASH
Ram Size256 x 8Voltage - Supply (vcc/vdd)3 V ~ 5.5 V
Data ConvertersA/D 6x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case28-SOIC (7.5mm Width)
Data Bus Width16 bitProcessor SeriesDSPIC30F
CoredsPIC3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By SupplierPG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011Package28SOIC W
Device CoredsPICFamily NamedsPIC30
Maximum Speed30 MHzOperating Supply Voltage3.3|5 V
Number Of Programmable I/os21Interface TypeI2C/SPI/UART
On-chip Adc6-chx10-bitNumber Of Timers2
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithDM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size-  
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dsPIC30F1010/202X
Data Sheet
28/44-Pin High-Performance
Switch Mode Power Supply
Digital Signal Controllers
Preliminary
© 2006 Microchip Technology Inc.
DS70178C

DSPIC30F1010-30I/SO Summary of contents

  • Page 1

    ... Microchip Technology Inc. dsPIC30F1010/202X Data Sheet 28/44-Pin High-Performance Switch Mode Power Supply Digital Signal Controllers Preliminary DS70178C ...

  • Page 2

    ... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

  • Page 3

    ... Enhanced Flash SMPS 16-Bit Digital Signal Controller Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” ...

  • Page 4

    ... PWM module interface - PWM Duty Cycle Control - PWM Period Control - PWM Fault Detect • Special Event Trigger • PWM-generated ADC Trigger dsPIC30F SWITCH MODE POWER SUPPLY FAMILY Product dsPIC30F1010 28 SDIP 6K dsPIC30F1010 28 SOIC 6K dsPIC30F1010 28 QFN-S 6K dsPIC30F2020 28 SDIP 12K dsPIC30F2020 28 SOIC 12K dsPIC30F2020 28 QFN-S 12K ...

  • Page 5

    ... QFN-S AN2/CMP1C/CMP2A/CN4/RB2 AN3/CMP1D/CMP2B/CN5/RB3 AN4/CMP2C/CN6/RB4 AN5/CMP2D/CN7/RB5 OSC1/CLKI/RB6 OSC2/CLKO/RB7 © 2006 Microchip Technology Inc. dsPIC30F1010/202X 1 28 MCLR PWM1L/RE0 4 25 PWM1H/RE1 5 24 PWM2L/RE2 PWM2H/RE3 6 23 RE4 RE5 PGC/EMUC/SDI1/SDA/U1RX/RF7 12 17 PGD/EMUD/SDO1/SCL/U1TX/RF8 13 16 SFLT2/INT0/OCFLTA/RA9 PGC2/EMUC2/OC1/SFLT1/INT1/RD0 PWM2L/RE2 2 20 PWM2H/RE3 3 19 RE4 dsPIC30F1010 4 RE5 PGC/EMUC/SDI1/SDA/U1RX/RF7 Preliminary DS70178C-page 3 ...

  • Page 6

    ... Pin Diagrams 28-Pin SDIP and SOIC AN0/CMP1A/CN2/RB0 AN1/CMP1B/CN3/RB1 AN2/CMP1C/CMP2A/CN4/RB2 AN3/CMP1D/CMP2B/CN5/RB3 AN4/CMP2C/CMP3A/CN6/RB4 AN5/CMP2D/CMP3B/CN7/RB5 AN6/CMP3C/CMP4A/OSC1/CLKI/RB6 AN7/CMP3D/CMP4B/OSC2/CLKO/RB7 PGD1/EMUD1/PWM4H/T2CK/U1ATX/CN1/RE7 PGC1/EMUC1/EXTREF/PWM4L/T1CK/U1ARX/CN0/RE6 PGD2/EMUD2/SCK1/SFLT3/OC2/INT2/RF6 28-Pin QFN-S AN2/CMP1C/CMP2A/CN4/RB2 AN3/CMP1D/CMP2B/CN5/RB3 AN4/CMP2C/CMP3A/CN6/RB4 AN5/CMP2D/CMP3B/CN7/RB5 AN6/CMP3C/CMP4A/OSC1/CLKI/RB6 AN7/CMP3D/CMP4B/OSC2/CLKO/RB7 DS70178C-page MCLR PWM1L/RE0 4 25 PWM1H/RE1 5 24 PWM2L/RE2 PWM2H/RE3 6 23 PWM3L/RE4 PWM3H/RE5 PGC/EMUC/SDI1/SDA/U1RX/RF7 12 17 PGD/EMUD/SDO1/SCL/U1TX/RF8 V 13 ...

  • Page 7

    ... Pin Diagrams 44-PIN QFN PGC/EMUC/SDI1/RF7 SYNCO/SS1/RF15 SFLT3/RA10 SFLT4/RA11 SDA/RG3 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 © 2006 Microchip Technology Inc. dsPIC30F1010/202X AN7/CMP3D/CMP4B/OSC2/CLKO/RB7 2 32 AN6/CMP3C/CMP4A/OSC1/CLKI/RB6 3 31 AN8/CMP4C/RB8 dsPIC30F2023 6 28 AN10/IFLT4/RB10 7 27 AN11/IFLT2/RB11 8 26 AN5/CMP2D/CMP3B/CN7/RB5 9 25 AN4/CMP2C/CMP3A/CN6/RB4 AN3/CMP1D/CMP2B/CN5/RB3 10 24 AN2/CMP1C/CMP2A/CN4/RB2 Preliminary DS70178C-page 5 ...

  • Page 8

    ... Pin Diagrams 44-Pin TQFP PGC/EMUC/SDI1/RF7 SYNCO/SS1/RF15 SFLT3/RA10 SFLT4/RA11 SDA/RG3 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 DS70178C-page dsPIC30F2023 Preliminary AN7/CMP3D/CMP4B/OSC2/CLKO/RB7 AN6/CMP3C/CMP4A/OSC1/CLKI/RB6 AN8/CMP4C/RB8 AN10/IFLT4/RB10 AN11/IFLT2/RB11 AN5/CMP2D/CMP3B/CN7/RB5 AN4/CMP2C/CMP3A/CN6/RB4 AN3/CMP1D/CMP2B/CN5/RB3 AN2/CMP1C/CMP2A/CN4/RB2 © 2006 Microchip Technology Inc. ...

  • Page 9

    ... Msps Analog-to-Digital Converter (ADC) Module........................................................................................................ 169 17.0 SMPS Comparator Module ...................................................................................................................................................... 191 18.0 System Integration ................................................................................................................................................................... 197 19.0 Instruction Set Summary .......................................................................................................................................................... 219 20.0 Development Support............................................................................................................................................................... 227 21.0 Electrical Characteristics .......................................................................................................................................................... 231 22.0 Package Marking Information................................................................................................................................................... 267 © 2006 Microchip Technology Inc. dsPIC30F1010/202X Preliminary DS70178C-page 7 ...

  • Page 10

    ... TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...

  • Page 11

    ... Figure 1-1 and Table 1-1 describe the dsPIC30F1010 SMPS device, Figure 1-2 and Table 1-2 describe the dsPIC30F2020 device and Figure 1-3 and Table 1-3 describe the dsPIC30F2023 SMPS device. ...

  • Page 12

    ... FIGURE 1-1: dsPIC30F1010 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH Program Counter Stack Address Latch Control Control Logic Logic Program Memory (12 Kbytes) 16 Data Latch ROM Latch Instruction Decode & Control ...

  • Page 13

    ... Table 1-1 provides a brief description of device I/O pinouts for the dsPIC30F1010 and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. ...

  • Page 14

    ... TABLE 1-1: PINOUT I/O DESCRIPTIONS FOR dsPIC30F1010 (CONTINUED) Pin Buffer Pin Name Type Type RE0-RE7 I/O ST RF6, RF7, RF8 I/O ST SCK1 I/O ST SDI1 I ST SDO1 O — SCL I/O ST SDA I/O ST T1CK I ST T2CK I ST U1RX I ST U1TX O — U1ARX I ST ...

  • Page 15

    ... Start-up Timer POR Reset Watchdog MCLR Timer Input Comparator Capture 10-bit ADC Module Module Input Change SPI1 Timers Notification © 2006 Microchip Technology Inc. dsPIC30F1010/202X X Data Bus Data Latch Data Latch Y Data X Data 16 RAM RAM (256 bytes) (256 bytes) Address Address ...

  • Page 16

    ... Table 1-2 provides a brief description of device I/O pinouts for the dsPIC30F2020 and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. ...

  • Page 17

    ... ST = Schmitt Trigger input with CMOS levels I = Input © 2006 Microchip Technology Inc. dsPIC30F1010/202X Description PORTB is a bidirectional I/O port. PORTA is a bidirectional I/O port. PORTD is a bidirectional I/O port. PORTE is a bidirectional I/O port. PORTF is a bidirectional I/O port. Synchronous serial clock input/output for SPI #1. ...

  • Page 18

    ... FIGURE 1-3: dsPIC30F2023 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH Program Counter Stack Address Latch Control Control Logic Logic Program Memory (12 Kbytes) 16 Data Latch ROM Latch Instruction Decode & Control ...

  • Page 19

    ... Schmitt Trigger input with CMOS levels I = Input © 2006 Microchip Technology Inc. dsPIC30F1010/202X Description Analog input channels. Positive supply for analog module. Ground reference for analog module. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...

  • Page 20

    ... TABLE 1-3: PINOUT I/O DESCRIPTIONS FOR dsPIC30F2023 (CONTINUED) Pin Buffer Pin Name Type Type PGD I/O ST PGC I ST PGD1 I/O ST PGC1 I ST PGD2 I/O ST PGC2 I ST RA8-RA11 I/O ST RB0-RB11 I/O ST RD0,RD1 I/O ST RE0-RE7 I/O ST RF2, RF3, I/O ST RF6-RF8, RF14, RF15 ...

  • Page 21

    ... Moreover, only the lower 16 bits of each instruction word can be accessed using this method. © 2006 Microchip Technology Inc. dsPIC30F1010/202X • Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions. ...

  • Page 22

    ... Programmer’s Model The programmer’s model is shown in Figure 2-1 and consists of 16x16-bit working registers (W0 through W15), 2x40-bit accumulators (ACCA and ACCB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT), and Program Counter (PC) ...

  • Page 23

    ... DSP ACCA Accumulators ACCB PC22 7 0 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2006 Microchip Technology Inc. dsPIC30F1010/202X D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 0 ...

  • Page 24

    ... Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/ 16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. DIVF – 16/16 signed fractional divide 2. DIV.sd – ...

  • Page 25

    ... EDAC MAC MAC MOVSAC MPY MPY.N MSC © 2006 Microchip Technology Inc. dsPIC30F1010/202X The DSP engine has various options selected through various bits in the CPU Core Configuration Register (CORCON), as listed below: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...

  • Page 26

    ... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70178C-page 24 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill © 2006 Microchip Technology Inc. ...

  • Page 27

    ... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 2.4.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true or complement data into the other input ...

  • Page 28

    ... The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit sat- uration, or bit 39 for 40-bit saturation) and will be satu- rated (if saturation is enabled) ...

  • Page 29

    ... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 15-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...

  • Page 30

    ... NOTES: DS70178C-page 28 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 31

    ... Microchip Technology Inc. dsPIC30F1010/202X FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F1010/ 202X GOTO Reset – Reset – Target Address Reserved Ext. Osc. Fail Trap ...

  • Page 32

    ... TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User User TBLRD/TBLWT (TBLPAG<7> Configuration TBLRD/TBLWT (TBLPAG<7> Program Space Visibility User FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Using Program 0 Counter Using 0 PSVPAG Reg Program Space ...

  • Page 33

    ... Program Memory ‘Phantom’ Byte (Read as ‘0’). © 2006 Microchip Technology Inc. dsPIC30F1010/202X A set of Table Instructions is provided to move byte or word sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the lsw of the program address; P<15:0> maps to D<15:0>. ...

  • Page 34

    ... FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE) PC Address 0x000000 00000000 0x000002 00000000 00000000 0x000004 0x000006 00000000 Program Memory ‘Phantom’ Byte (Read as ‘0’) 3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page ...

  • Page 35

    ... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. © 2006 Microchip Technology Inc. dsPIC30F1010/202X Program Space 0x0000 (1) PSVPAG 0x00 8 ...

  • Page 36

    ... FIGURE 3-6: DATA SPACE MEMORY MAP MSB Address 0x0001 SFR Space (Note) 0x07FF 0x0801 512 bytes 0x08FF 0x0901 SRAM Space 0x09FF 0x8001 Optionally Mapped into Program Memory 0xFFFF Note: Unimplemented SFR or SRAM locations read as ‘0’. DS70178C-page 34 16 bits Address ...

  • Page 37

    ... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2006 Microchip Technology Inc. dsPIC30F1010/202X SFR SPACE UNUSED Y SPACE UNUSED MAC Class Ops Read-Only Indirect EA using W10, W11 ...

  • Page 38

    ... DATA SPACES The X data space is used by all instructions and sup- ports all Addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...

  • Page 39

    ... Word> 3.2.7 DATA RAM PROTECTION The dsPIC30F1010/202X devices support data RAM protection features which enable segments of RAM to be protected when used in conjunction with Boot Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled ...

  • Page 40

    TABLE 3-3: CORE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 0016 ...

  • Page 41

    TABLE 3-3: CORE REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 MODCON 0046 XMODEN YMODEN — — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — BSRAM 0750 ...

  • Page 42

    ... NOTES: DS70178C-page 40 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 43

    ... Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2006 Microchip Technology Inc. dsPIC30F1010/202X 4.1 Instruction Addressing Modes The Addressing modes in Table 4-1 form the basis of the Addressing modes optimized to support the specific features of individual instructions ...

  • Page 44

    ... MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 <function> Operand 2 where Operand 1 is always a working register (i.e., the Addressing mode can only be register direct), which is referred to as Wb. Operand 2 can register, fetched from data memory 5-bit literal. The result location can be either a W register or an address location ...

  • Page 45

    ... Bidirectional mode, (i.e., address bound- ary checks will be performed on both the lower and upper address boundaries). © 2006 Microchip Technology Inc. dsPIC30F1010/202X 4.2.1 START AND END ADDRESS The modulo addressing scheme requires that a starting and an end address be specified and loaded ...

  • Page 46

    ... FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words DS70178C-page 44 MOV #0x1100,W0 MOV W0, XMODSRT ;set modulo start address MOV #0x1163,W0 MOV W0,MODEND ;set modulo end address MOV #0x8001,W0 MOV W0,MODCON ...

  • Page 47

    ... Microchip Technology Inc. dsPIC30F1010/202X If the length of a bit-reversed buffer then the last ‘N’ bits of the data buffer start address must be zeros. XB<14:0> is the bit-reversed address modifier or ‘pivot point’ ...

  • Page 48

    ... TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 32768 16384 8192 4096 2048 1024 512 256 128 Note 1: Modifier values greater than 256 words exceed the data memory available on the dsPIC30F1010/202X device DS70178C-page 46 Decimal XB<14:0> Bit-Reversed Address Modifier Value ...

  • Page 49

    ... Manual” (DS70046). For more information on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157). The dsPIC30F1010/202X device has interrupt sources and 4 processor exceptions (traps), which must be arbitrated based on a priority scheme. The CPU is responsible for reading the Interrupt Vec- tor Table (IVT) and transferring the address contained in the interrupt vector to the Program Counter (PC) ...

  • Page 50

    ... The INT0 (external interrupt 0) may be assigned to priority level 1, thus giving it a very low effective priority. DS70178C-page 48 TABLE 5-1: dsPIC30F1010/202X INTERRUPT VECTOR TABLE INT Vector Number Number Highest Natural Order Priority ...

  • Page 51

    ... Trap Lockout: Occurrence of multiple Trap conditions simultaneously will cause a Reset. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 5.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 5-1. They ...

  • Page 52

    ... Address Error Trap: This trap is initiated when any of the following circumstances occurs misaligned data word access is attempted data fetch from our unimplemented data memory location is attempted data access of an unimplemented program memory location is attempted instruction fetch from vector space is attempted. ...

  • Page 53

    ... The RETFIE (Return from Interrupt) instruction will unstack the Program Counter and status registers to return the processor to its state prior to the interrupt sequence. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 5.5 Alternate Vector Table In Program Memory, the IVT is followed by the AIVT, as shown in Figure 5-1. Access to the Alternate Vector Table is provided by the ALTIVT bit in the INTCON2 register ...

  • Page 54

    ... REGISTER 5-1: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR bit 15 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...

  • Page 55

    ... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. dsPIC30F1010/202X Preliminary DS70178C-page 53 ...

  • Page 56

    ... REGISTER 5-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 ALTIVT DISI — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector table ...

  • Page 57

    ... Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 Unimplemented: Read as ‘0’ bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 NVMIF ADIF U1TXIF U-0 R/W-0 R/W-0 — ...

  • Page 58

    ... REGISTER 5-3: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ...

  • Page 59

    ... INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 R/W-0 U-0 — CNIF — R/W-0 ...

  • Page 60

    ... REGISTER 5-5: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 ADCP2IF ADCP1IF ADCP0IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10 ADCP5IF: ADC Pair 5 Conversion Done Interrupt Flag Status bit ...

  • Page 61

    ... OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 Unimplemented: Read as ‘0’ bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 NVMIE ADIE U1TXIE U-0 R/W-0 R/W-0 — ...

  • Page 62

    ... REGISTER 5-6: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit ...

  • Page 63

    ... INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 R/W-0 U-0 — CNIE — R/W-0 R/W-0 R/W-0 ...

  • Page 64

    ... REGISTER 5-8: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 ADCP2IE ADCP1IE ADCP0IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10 ADCP5IE: ADC Pair 5 Conversion done Interrupt Enable bit ...

  • Page 65

    ... INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

  • Page 66

    ... REGISTER 5-10: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 — T3IP<2:0> bit 15 U-0 R/W-1 R/W-0 — OC2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...

  • Page 67

    ... SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

  • Page 68

    ... REGISTER 5-12: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — SI2CIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ 2 bit 10-8 MI2CIP<2:0>: I ...

  • Page 69

    ... INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

  • Page 70

    ... REGISTER 5-14: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — PWM3IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 PWM4IP<2:0>: PWM Generator #4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...

  • Page 71

    ... CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11-0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 U-0 U-0 — — U-0 U-0 U-0 — ...

  • Page 72

    ... REGISTER 5-16: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 — AC3IP<2:0> bit 15 U-0 R/W-1 R/W-0 — AC1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 AC3IP<2:0>: Analog Comparator 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...

  • Page 73

    ... Unimplemented: Read as ‘0’ bit 2-0 AC4IP<2:0>: Analog Comparator 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...

  • Page 74

    ... REGISTER 5-18: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 — ADCP2IP<2:0> bit 15 U-0 R/W-1 R/W-0 — ADCP0IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADCP2IP<2:0>: ADC Pair 2 Conversion Done Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...

  • Page 75

    ... ADCP3IP<2:0>: ADC Pair 3 Conversion Done Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...

  • Page 76

    ... REGISTER 5-20: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R-0 R-0 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • ...

  • Page 77

    TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Name INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 ALTIVT DISI — — 0082 IFS0 0084 — MI2CIF SI2CIF NVMIF IFS1 0086 AC3IF AC2IF ...

  • Page 78

    ... NOTES: DS70178C-page 76 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 79

    ... I/O cell (pad) to which they are connected. Table 6-1 and Table 6-2 show the register formats for the shared ports, PORTA through PORTF, for the dsPIC30F1010/2020 and PORTA through PORTG for the dsPIC30F2023 device, respectively. ...

  • Page 80

    ... Delay 1 cycle BTSS PORTB, #13; Next Instruction DS70178C-page 78 6.3 Input Change Notification The input change notification function of the I/O ports allows the dsPIC30F1010/202X devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature will be capable of detecting input change-of-states even in OL Sleep mode, when the clocks are disabled ...

  • Page 81

    ... TABLE 6-1: dsPIC30F1010/2020 PORT REGISTER MAP Bit SFR Name Addr. Bit 15 Bit 14 Bit 13 12 TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — TRISB 02C6 — — — — PORTB 02C8 — ...

  • Page 82

    ... LATG 02E8 — — — — Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 6-3: dsPIC30F1010/202X INPUT CHANGE NOTIFICATION REGISTER MAP SFR Bit Addr. Bit 15 Bit 14 Bit 13 Bit 11 Name 12 CNEN1 0060 — ...

  • Page 83

    ... Addressing Using Table Instruction User/Configuration Space Select © 2006 Microchip Technology Inc. dsPIC30F1010/202X 7.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory 32 instructions (96 bytes time and can write program memory data 32 instructions (96 bytes time ...

  • Page 84

    ... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instruc- tions bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program 32 instructions at one time. RTSP may be used to program multiple program memory panels, but the table pointer must be changed at each panel boundary ...

  • Page 85

    ... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2006 Microchip Technology Inc. dsPIC30F1010/202X 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program and set WREN bit. ...

  • Page 86

    ... LOADING WRITE LATCHES Example 7-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer. EXAMPLE 7-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...

  • Page 87

    TABLE 7-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — Legend uninitialized bit Note: Refer ...

  • Page 88

    ... NOTES: DS70178C-page 86 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 89

    ... SFR, T1CON. Figure 8-1 presents a block diagram of the 16-bit timer module. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 16-bit Timer Mode: In the 16-bit Timer mode, the timer increments on every instruction cycle match value, preloaded into the period register PR1, then resets to 0 and continues to count ...

  • Page 90

    ... FIGURE 8-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER) Equal Reset 0 T1IF Event Flag 1 TGATE T1CK 8.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T1CK pin) is asserted high. Control bit TGATE (T1CON< ...

  • Page 91

    ... Enabling an interrupt is accomplished via the respec- tive timer interrupt enable bit, T1IE. The timer interrupt enable bit is located in the IEC0 control register in the Interrupt Controller. © 2006 Microchip Technology Inc. dsPIC30F1010/202X Preliminary DS70178C-page 89 ...

  • Page 92

    TABLE 8-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) ...

  • Page 93

    ... Timer2/3 module. Figure 9-2 and Figure 9- 3 show Timer2/3 configured as two independent 16-bit timers: Timer2 and Timer3, respectively. Note: The dsPIC30F1010 device does not fea- ture Timer3. Timer2 is a ‘Type B’ timer and Timer3 is a ‘Type C’ timer. Please refer to the appropriate timer type in Section 21.0 “ ...

  • Page 94

    ... FIGURE 9-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 Write TMR2 Read TMR2 16 Reset TMR3 MSB ADC Event Trigger Comparator x 32 Equal PR3 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer Configuration bit T32, (T2CON<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register ...

  • Page 95

    ... T3IF Event Flag 1 TGATE Note: The dsPIC30F202X does not have an external pin input to TIMER3. The following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) © 2006 Microchip Technology Inc. dsPIC30F1010/202X PR2 Comparator x 16 TMR2 Q D TGATE Q CK ...

  • Page 96

    ... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...

  • Page 97

    TABLE 9-1: TIMER2/3 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...

  • Page 98

    ... NOTES: DS70178C-page 96 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 99

    ... ICxCON register (where x = 1,2,...,N). The dsPIC DSC devices contain capture channels, (i.e., the maximum value 8). Note: The dsPIC30F1010 devices does not fea- ture a Input Capture module. The dsPIC30F202X devices have one capture input – IC1. The naming of this capture ...

  • Page 100

    ... Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • Capture every falling edge • Capture every rising edge • Capture every 4th rising edge • Capture every 16th rising edge • Capture every rising and falling edge These simple Input Capture modes are configured by setting the appropriate bits ICM< ...

  • Page 101

    ... Sleep mode. The prescale settings of 4:1 or 16:1 are not applicable in this mode. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 10.2.2 INPUT CAPTURE IN CPU IDLE MODE CPU Idle mode allows input capture module operation with full functionality. In the CPU Idle mode, the Inter- rupt mode selected by the ICI< ...

  • Page 102

    TABLE 10-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — Legend uninitialized bit Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for ...

  • Page 103

    ... Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 and 2. © 2006 Microchip Technology Inc. dsPIC30F1010/202X The key operational features of the Output Compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...

  • Page 104

    ... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers: Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the Output Compare module. 11.2 Simple Output Compare Match Mode When control bits OCM< ...

  • Page 105

    ... PWM mode is reenabled by writing the appropriate mode bits, OCM<2:0> in the OCxCON register. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 11.5 Output Compare Operation During CPU Sleep Mode When the CPU enters the Sleep mode, all internal clocks are stopped ...

  • Page 106

    ... FIGURE 11-1: PWM OUTPUT TIMING Duty Cycle TMR3 = PR3 T3IF = 1 (Interrupt Flag) OCxR = OCxRS TMR3 = Duty Cycle (OCxR) 11.7 Output Compare Interrupts The output compare channels have the ability to gener- ate an interrupt on a compare match, for whichever Match mode has been selected. ...

  • Page 107

    TABLE 11-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — Note: Refer to ...

  • Page 108

    ... NOTES: DS70178C-page 106 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 109

    ... POWER SUPPLY PWM The Power Supply PWM (PS PWM) module on the dsPIC30F1010/202X device supports a wide variety of PWM modes and output formats. This PWM module is ideal for power conversion applications such as: • DC/DC converters • AC/DC power supplies • Uninterruptable Power Supply (UPS) 12 ...

  • Page 110

    ... FIGURE 12-1: SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF POWER SUPPLY PWM PWMCONx Pin and mode control Control for blanking external input signals LEBCONx TRGCONx ADC Trigger Control Dead-time Control ALTDTRx, DTRx PWM enable and mode control PTCON PDC1 MUX PWM GEN #1 Latch ...

  • Page 111

    ... TRGCONx: PWM TRIGGER Control Register • IOCONx: PWM I/O Control Register • FCLCONx: PWM Fault Current-Limit Control Register • TRIGx: PWM Trigger Compare Value Register • LEBCONx: Leading Edge Blanking Control Register © 2006 Microchip Technology Inc. dsPIC30F1010/202X TMR < PDC Dead PWM Override Time Logic ...

  • Page 112

    ... REGISTER 12-1: PTCON: PWM TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 PTEN — PTSIDL bit 15 R/W-0 R/W-0 R/W-0 SYNCEN SYNCSRC<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PTEN: PWM Module Enable bit 1 = PWM module is enabled ...

  • Page 113

    ... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-3 Special Event Compare Count Value bits bit 2-0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 PTPER <15:8> R/W-0 R/W-0 U-0 — Unimplemented bit, read as ‘0’ ...

  • Page 114

    ... REGISTER 12-4: MDC: PWM MASTER DUTY CYCLE REGISTER R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 Master PWM Duty Cycle Value bits Note 1: The minimum value for this register is 0x0008 and the maximum value is 0xFFEF. ...

  • Page 115

    ... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PWM Generator #x Duty Cycle Value bits Note 1: The minimum value for this register is 0x0008 and the maximum value is 0xFFEF. © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 PDCx<15:8> R/W-0 R/W-0 R/W-0 PDCx< ...

  • Page 116

    ... REGISTER 12-7: PHASEx: PWM PHASE-SHIFT REGISTER R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 PHASEx<7:2> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-2 PHASEx<15:2>: PWM Phase-Shift Value or Independent Time Base Period for this PWM Generator bits Note: If used as an independent time base, bits < ...

  • Page 117

    ... TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits This value specifies the ROLL counter value needed for a match that will then enable the trigger postscaler logic to begin counting trigger events. © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 ALTDTRx<13:8> ...

  • Page 118

    ... REGISTER 12-11: IOCONx: PWM I/O CONTROL REGISTER R/W-0 R/W-0 R/W-0 PENH PENL POLH bit 15 R/W-0 R/W-0 R/W-0 OVRDAT<1:0> FLTDAT<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PENH: PWMH Output Pin Ownership bit 1 = PWM module controls PWMxH pin ...

  • Page 119

    ... CLPOL: Current-Limit Polarity for PWM Generator #X bit 1 = The selected current-limit source is low active 0 = The selected current-limit source is high active bit 7 CLMODE: Current-Limit Mode Enable for PWM Generator #X bit 1 = Current-limit function is enabled 0 = Current-limit function is disabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 CLSRC<3:0> R/W-0 R/W-0 R/W-0 FLTPOL U = Unimplemented bit, read as ‘ ...

  • Page 120

    ... REGISTER 12-12: FCLCONx: PWM FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED) bit 6-3 FLTSRC<3:0>: Fault Control Signal Source Select for PWM Generator #X bits 0000 = Analog Comparator #1 0001 = Analog Comparator #2 0010 = Analog Comparator #3 0011 = Analog Comparator #4 0100 = Reserved 0101 = Reserved 0110 = Reserved 0111 = Reserved ...

  • Page 121

    ... The minimum usable value for this register is 0x0008 A value of 0x0000 does not produce a trigger. If the TRIGx value is being calculated based on duty cycle value, you must ensure that a minimum TRIGx value is written into the register at all times. © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 TRGCMP<15:8> ...

  • Page 122

    ... REGISTER 12-14: LEBCONx: LEADING EDGE BLANKING CONTROL REGISTER R/W-0 R/W-0 R/W-0 PHR PHF PLR bit 15 R/W-0 R/W-0 R/W-0 LEB<7:3> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PHR: PWMH Rising Edge Trigger Enable bit 1 = Rising edge of PWMH will trigger LEB counter ...

  • Page 123

    ... Value 0 PWMH Duty Cycle Period © 2006 Microchip Technology Inc. dsPIC30F1010/202X 12.4.2 COMPLEMENTARY PWM MODE Complementary PWM is generated in a manner similar to standard Edge-Aligned PWM. Complementary mode provides a second PWM output signal on the PWML pin that is the complement of the primary PWM signal (PWMH) ...

  • Page 124

    ... MULTI-PHASE PWM MODE Multi-Phase PWM, as shown in Figure 12-6, uses phase-shift values in the Phase registers to shift the PWM outputs relative to the primary time base. Because the phase-shift values are added to the pri- mary time base, the phase-shifted outputs occur earlier than a PWM channel that specifies zero phase shift ...

  • Page 125

    ... Duty Cycle Actual Period Programmed Period © 2006 Microchip Technology Inc. dsPIC30F1010/202X Typically, in the converter application, an energy stor- age inductor is charged with current while the PWM signal is asserted, and the inductor current is dis- charged by the load when the PWM signal is deas- serted ...

  • Page 126

    ... Primary PWM Time Base There is a Primary Time Base (PTMR) counter for the entire PWM module, In addition, each PWM generator has an individual time base counter. The PTMR determines when the individual time base counters are to update their duty cycle and phase-shift registers ...

  • Page 127

    ... The PWM period can be determined from the following formula: Period Duration = (PTPER + 1)/120 MHz @ 30 MIPS © 2006 Microchip Technology Inc. dsPIC30F1010/202X 12.9 PWM Frequency and Duty Cycle Resolution 3 The PWM Duty cycle resolution is 1.05 nsec per LSB @ 30 MIPS ...

  • Page 128

    ... PWM Duty Cycle Comparison Units The PWM module has two to four PWM duty cycle generators. Three to five 16-bit special function regis- ters are used to specify duty cycle values for the PWM module: • MDC (Master Duty Cycle) • PDC1, ..., PDC4 (Duty Cycle) ...

  • Page 129

    ... DTC<1:0> bit in the PWMCON register FIGURE 12-15: DEAD-TIME INSERTION FOR COMPLEMENTARY PWM t da PWM Generator #1 Output PWM1H PWM1L © 2006 Microchip Technology Inc. dsPIC30F1010/202X FIGURE 12-16: DTR1 ALTDR1 PWM1 in DTR2 ALTDTR2 PWM2 in DTR3 ALTDTR3 PWM3 in DTR4 ALTDTR4 PWM4 in 12 ...

  • Page 130

    ... FIGURE 12-17: DUAL DEAD-TIME WAVEFORMS No dead time PWMH PWML Positive dead time PWMH PWML Negative dead time PWMH PWML DTRx ALTDTRx FIGURE 12-18: DEAD-TIME INSERTION (PWM OUTPUT SIGNAL TIMING MAY BE DELAYED DS70178C-page 128 12.14.3 DEAD-TIME RANGES The amount of dead time provided by each dead-time unit is selected by specifying a 12-bit unsigned value in the DTRx registers ...

  • Page 131

    ... Example 12 code example for configuring PWM channel 1 to operate in complementary mode at 400 kHz, with a dead-time value of approximately 64 nsec assumed that the dsPIC30F1010/202X is operating on the internal fast RC oscillator with PLL in the high- frequency range (14.55 MHz input to the PLL, assuming industrial temperature rated part). ...

  • Page 132

    ... EXAMPLE 12-1: CODE EXAMPLE FOR CONFIGURING PWM CHANNEL 1 . Note: This code example does not illustrate configuration of various fault modes for the PWM module intended as a quick start guide for setting up the PWM Module. mov #0x0400, w0 mov w0, PTCON ; Set the PWM Period ...

  • Page 133

    ... The primary time base special event interrupt is enabled via the SEIEN bit in the PTCON register. The individual time base interrupts generated by the trigger logic in each PWM generator are controlled by the TRGIEN bit in the PWMCONx registers. © 2006 Microchip Technology Inc. dsPIC30F1010/202X PDI 15 3 PTMRx Compare Logic ...

  • Page 134

    ... The FLTLEBEN and CLLEBEN bits enable the applica- tion of the blanking period to the selected Fault and current-limit inputs. The LEB duration @ 30 (LEB<9:3> + 1)/120 MHz. There is a blanking period offset of 8.4 nsec. Therefore a LEB<9:3> value of zero yields an effective blanking period of 8.4 ns. ...

  • Page 135

    ... The operating mode for each Fault input pin is selected using the FLTMOD<1:0> control bits in the FCLCONx register. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 12.23.4 FAULT ENTRY The response of the PWM pins to the Fault input pins is always asynchronous with respect to the device clock signals ...

  • Page 136

    ... PWM Current-Limit Pins Each PWM generator can select its own current-limit input source from up to12 current-limit/Fault pins. In the FCLCONx registers, each PWM generator has control bits (CLSRC<3:0>) that specify the source for its cur- rent-limit input signal. Additionally, each PWM genera- ...

  • Page 137

    ... Microchip Technology Inc. dsPIC30F1010/202X 12.29 Asserting Outputs via Current Limit It is possible to use the CLDAT bits to assert the PWMxH,L outputs in response to a current-limit event. ...

  • Page 138

    ... OVERRIDE SYNCHRONIZATION If the OSYNC bit in the IOCONx register is set, the out- put overrides performed via the OVRENH,L and the OVDDAT<1:0> bits are synchronized to the PWM time base. Synchronous output overrides occur when the time base is zero. If PTEN = 0, meaning the timer is not running, writes to IOCON take effect on the next T boundary ...

  • Page 139

    ... Boost Converter PWM1H © 2006 Microchip Technology Inc. dsPIC30F1010/202X 12.34.2 APPLICATION OF COMPLEMENTARY PWM MODE Complementary mode PWM is often used in circuits that use two transistors in a bridge configuration where transformers are not used, as shown in Figure 12-23. If transformers are used, then some means must be provided to ensure that no net DC currents flow through the transformer to prevent core saturation ...

  • Page 140

    ... APPLICATION OF PUSH-PULL PWM MODE Push-Pull PWM mode is typically used in transformer coupled circuits to ensure that no net DC currents flow through the transformer. Push-Pull mode ensures that the same duty cycle PWM pulse is applied to the transformer windings in alternate directions, as shown in Figure 12-24. ...

  • Page 141

    ... T1 PWM1H PWM1H PWM1H © 2006 Microchip Technology Inc. dsPIC30F1010/202X 12.34.6 APPLICATION OF CURRENT RESET PWM MODE In Current Reset PWM mode, the PWM frequency var- ies with the load current. This mode is different than most PWM modes because the user sets the maxi- mum PWM period, but an external circuit measures the inductor current ...

  • Page 142

    ... METHODS TO REDUCE EMI The goal is to move the PWM edges around in time to spread the EMI energy over a range of frequencies to reduce the peak energy at any given frequency during the EMI measurement process, which measures long term averages. The EMI measurement process integrates the EMI energy into 9 kHz wide frequency bins ...

  • Page 143

    ... Microchip Technology Inc. dsPIC30F1010/202X The TRGDIV<2:0> bits in each TRGCONx register will be set to ‘111’, which selects that every 8th trigger comparison match will generate a trigger signal to the ADC to capture data and begin a conversion process ...

  • Page 144

    TABLE 12-4: POWER SUPPLY PWM REGISTER MAP File Name ADR Bit 15 Bit 14 Bit 13 Bit 12 PTCON 0400 PTEN — PTSIDL SESTAT PTPER 0402 MDC 0404 SEVTCMP 0406 PWMCON1 0408 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON1 040A PENH PENL ...

  • Page 145

    TABLE 12-4: POWER SUPPLY PWM REGISTER MAP (CONTINUED) File Name ADR Bit 15 Bit 14 Bit 13 Bit 12 FCLCON4 0448 — — — PDC4 044A PHASE4 044C DTR4 044E — — ALTDTR4 0450 — — TRIG4 0452 TRGCON4 0454 ...

  • Page 146

    ... NOTES: DS70178C-page 144 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 147

    ... SERIAL PERIPHERAL INTERFACE (SPI) Note: This data sheet summarizes the features of this group of dsPIC30F1010/202X devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). The Serial Peripheral Interface (SPI) module is a syn- chronous serial interface useful for communicating with other peripheral or microcontroller devices ...

  • Page 148

    ... SDIx SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF Note: The dsPIC30F1010/2020 devices do not contain the SS1 pin. Therefore, the Slave Select and Frame Sync features cannot be used on these devices. These features are available on the dsPIC30F2023. DS70178C-page 146 1:1 to 1:8 Secondary Prescaler Select ...

  • Page 149

    ... SPI MASTER, FRAME MASTER CONNECTION DIAGRAM dsPIC33F (SPI Slave, Frame Slave) FIGURE 13-4: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM dsPIC33F (SPI Master, Frame Slave) © 2006 Microchip Technology Inc. dsPIC30F1010/202X PROCESSOR 2 (SPI Slave) SDOx SDIx Serial Receive Buffer SDIx SDOx LSb ...

  • Page 150

    ... FIGURE 13-5: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM dsPIC33F (SPI Slave, Frame Slave) FIGURE 13-6: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM dsPIC33F (SPI Master, Frame Slave) EQUATION 13-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED F SCK TABLE 13-1: SAMPLE SCKx FREQUENCIES ...

  • Page 151

    ... SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 U-0 U-0 — — ...

  • Page 152

    ... REGISTER 13-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12 ...

  • Page 153

    ... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application. © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 U-0 U-0 — — ...

  • Page 154

    TABLE 13-2: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name SPI1STAT 0240 SPIEN — SPISIDL — SPI1CON 0242 — — — DISSCK DISSDO MODE16 SPI1CON2 0244 FRMEN SPIFSD FRMPOL — SPI1BUF 0246 Legend: u ...

  • Page 155

    ... I2CRCV is the receive buffer, as shown in Figure 16-1. I2CTRN is the transmit register to which bytes are writ- ten during a transmit operation, as shown in Figure 16-2. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 14.1 Operating Function Description The hardware fully implements all the master and slave functions of the I specifications, as well as 7 and 10-bit addressing ...

  • Page 156

    ... FIGURE 14-2: I C™ BLOCK DIAGRAM Shift SCL Clock SDA Match Detect Stop bit Detect Stop bit Generate Shift Clock DS70178C-page 154 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload ...

  • Page 157

    ... I2CRCV is not full or I2COV is not set, I2CRSR is transferred to I2CRCV. ACK is sent on the ninth clock. © 2006 Microchip Technology Inc. dsPIC30F1010/202X If the RBF flag is set, indicating that I2CRCV is still holding data from a previous operation (RBF = 1), then ACK is not sent; however, the interrupt pulse is gener- ated ...

  • Page 158

    ... Automatic Clock Stretch In the Slave modes, the module can synchronize buffer reads and write to the master device by clock stretching. 14.5.1 TRANSMIT CLOCK STRETCHING Both 10-bit and 7-bit Transmit modes implement clock stretching by asserting the SCLREL bit after the falling edge of the ninth clock if the TBF bit is cleared, indicating the buffer is empty ...

  • Page 159

    ... Configure the I C port to receive data. • Generate an ACK condition at the end of a received byte of data. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 2 14. Master Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition ...

  • Page 160

    ... BAUD RATE GENERATOR Master mode, the reload value for the BRG is located in the I2CBRG register. When the BRG is loaded with this value, the BRG counts down to ‘0’ and stops until another reload has taken place. If clock arbitration is taking place, for instance, the BRG is reloaded when the SCL pin is sampled high ...

  • Page 161

    TABLE 14-1: I C™ REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name — — — — I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — I2CCON 0206 I2CEN ...

  • Page 162

    ... NOTES: DS70178C-page 160 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 163

    ... Family Reference Manual” (DS70046). The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the dsPIC30F1010/202X device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 inter- faces ...

  • Page 164

    ... UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator. The U1BRG register controls the period of a free-running 16-bit timer. Equation 15-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 15-1: UART BAUD RATE WITH ...

  • Page 165

    ... A transmit interrupt will be generated as per the setting of control bit, UTXISELx. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 15.4 Break and Sync Transmit Sequence The following sequence will send a message frame header made Break, followed by an auto-baud Sync byte ...

  • Page 166

    ... REGISTER 15-1: U1MODE: UART1 MODE REGISTER R/W-0 U-0 R/W-0 UARTEN — USIDL bit 15 R/W-0 HC R/W-0 R/W-0 HC WAKE LPBACK ABAUD bit 7 Legend Unimplemented bit, read as ‘0’ Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UART1 Enable bit 1 = UART1 enabled ...

  • Page 167

    ... PDSEL1:PDSEL0: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit © 2006 Microchip Technology Inc. dsPIC30F1010/202X Preliminary DS70178C-page 165 ...

  • Page 168

    ... REGISTER 15-2: U1STA: UART1 STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 (1) UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL1 URXISEL0 ADDEN bit 7 Legend Unimplemented bit, read as ‘0’ Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15, 13 UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits 11 =Reserved ...

  • Page 169

    ... RSR to the empty state) bit 0 URXDA: Receive Buffer Data Available bit (Read-Only Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty © 2006 Microchip Technology Inc. dsPIC30F1010/202X Preliminary 0 transition) will reset DS70178C-page 167 ...

  • Page 170

    TABLE 15-1: UART1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — ...

  • Page 171

    ... MSPS ANALOG-TO- DIGITAL CONVERTER (ADC) MODULE The dsPIC30F1010/202X devices provide high-speed successive approximation analog to digital conversions to support applications such as AC/DC and DC/DC power converters. 16.1 Features • 10-bit resolution • Uni-polar Inputs • input channels • ±1 LSB accuracy • ...

  • Page 172

    ... FIGURE 16-1: ADC BLOCK DIAGRAM AN0 AN2 AN4 AN6 AN8 AN10 AN1 AN3 AN11 DS70178C-page 170 Dedicated Sample & Holds 10-Bit SAR DAC AV DD Even numbered inputs without dedicated Sample and Hold Common Sample and Hold Preliminary 12-word, 16-bit Registers ...

  • Page 173

    ... If the shared S&H is busy at the time the dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion cycle bit 4-3 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 U-0 — — U-0 U-0 — ...

  • Page 174

    ... REGISTER 16-1: A/D CONTROL REGISTER (ADCON) (CONTINUED) bit 2-0 ADCS<2:0>: A/D Conversion Clock Divider Select bits If PLL is enabled (assume 15 MHz external clock as clock source): 111 = F /18 = 13.3 MHz @ 30 MIPS ADC 110 = F /16 = 15.0 MHz @ 30 MIPS ADC 101 = F /14 = 17.1 MHz @ 30 MIPS ...

  • Page 175

    ... Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 0 P0RDY: Conversion Data for Pair #0 Ready bit Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit. © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 U-0 U-0 — ...

  • Page 176

    ... REGISTER 16-3: A/D BASE REGISTER (ADBASE) R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-1 ADC Base Register: This register contains the base address of the user’s ADC Interrupt Service Rou- tine jump table ...

  • Page 177

    ... Start conversion of AN1 and AN0 (if selected by TRGSRC bits). If other conversions are in progress, then conversion will be performed when the conversion resources are available. This bit will be reset when the PEND bit is set © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 TRGSRC1<4:0> ...

  • Page 178

    ... REGISTER 16-5: A/D CONVERT PAIR CONTROL REGISTER #0 (ADCPC0) (CONTINUED) bit 4-0 TRGSRC0<4:0>: Trigger 0 Source Selection bits Selects trigger source for conversion of analog channels AN1 and AN0. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected ...

  • Page 179

    ... Start conversion of AN5 and AN4 (if selected by TRGSRC bits). If other conversions are in progress, then conversion will be performed when the conversion resources are available. This bit will be reset when the PEND bit is set © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 TRGSRC3<4:0> ...

  • Page 180

    ... REGISTER 16-6: A/D CONVERT PAIR CONTROL REGISTER #1 (ADCPC1) (CONTINUED) bit 4-0 TRGSRC2<4:0>: Trigger 2 Source Selection bits Selects trigger source for conversion of analog channels: AN5 and AN4 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected ...

  • Page 181

    ... Start conversion of AN9 and AN8 (if selected by TRGSRC bits). If other conversions are in progress, then conversion will be performed when the conversion resources are available. This bit will be reset when the PEND bit is set. © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 TRGSRC5<4:0> ...

  • Page 182

    ... REGISTER 16-7: A/D CONVERT PAIR CONTROL REGISTER #2 (ADCPC2) (CONTINUED) bit 4-0 TRGSRC4<4:0>: Trigger Source Selection 4 bits Selects trigger source for conversion of analog channels: AN9 and AN8 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected ...

  • Page 183

    ... R X Late sample yields zero data Measuring peak inductor current is very important © 2006 Microchip Technology Inc. dsPIC30F1010/202X 16.5 Application Information The ADC module implements a concept based on “Conversion Pairs”. In power conversion applications, there is a need to measure voltages and currents for each PWM control loop ...

  • Page 184

    ... Reverse Conversion Order The ORDER control bit in the ADCON register, when set, reverses the order of the input pair conversion pro- cess. Normally (ORDER = 0), the even numbered input of an input pair is converted first and then the odd numbered input is converted. If ORDER = 1, the odd numbered input pin of an input pair is converted first, followed by the even numbered pin ...

  • Page 185

    ... ADSTAT register at the completion of the first conversion, and remains set until it is cleared by the user. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 16.11 Conflict Resolution If more than one conversion pair request is active at the same time, the ADC control logic processes the ...

  • Page 186

    ... Example 16-1 shows a code sequence for using the ADBASE register to implement ADC Input Pair Inter- rupt Handling. When the ADBASE register is read, it contains the sum of the base address of the jump table and the encoded ADC channel pair number left shifted by 2 bits ...

  • Page 187

    ... When operating at the maximum conversion rate of 2 Msps per channel, the sampling period is 41.6 nsec = 83.3 nsec. © 2006 Microchip Technology Inc. dsPIC30F1010/202X ; The ADC pair 0 conversion complete handler ; Restore W0-W3 and SR registers ; Return from Interrupt ; The ADC pair 1 conversion complete handler ...

  • Page 188

    ... A/D Sample and Convert Timing The sample and hold circuits assigned to the input pins have their own timing logic that is triggered when an external sample and convert request (from PWM or TMR) is made. The sample and hold circuits have a fixed two clock data sample period. When the sample ...

  • Page 189

    ... For all analog input pairs that have dedicated sample and hold circuits, the common sample and hold circuit samples the input at the start of the first conversion so that both samples (odd and even) are near simultaneous. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 5th 4th ...

  • Page 190

    ... Module Power-Down Modes The module has two internal power modes. When the ADON bit is ‘1’, the module is in Active mode and is fully powered and functional. When ADON is ‘0’, the module is in Off mode. The state machine for the module is reset, as are all of the pending conversion requests ...

  • Page 191

    ... Read to Bus: Fractional d09 d08 d07 Integer © 2006 Microchip Technology Inc. dsPIC30F1010/202X d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 d06 d05 d04 d03 d02 d01 d00 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Preliminary ...

  • Page 192

    TABLE 16-1: ADC REGISTER MAP File Name ADR Bit 15 Bit 14 Bit 13 Bit 12 ADCON 0300 ADON — ADSIDL — ADPCFG 0302 — — — — Reserved 0304 — — — — ADSTAT 0306 — — — — ...

  • Page 193

    ... Trigger an ADC sample and convert process • Truncate the PWM signal (current limit) • Truncate the PWM period (current minimum) © 2006 Microchip Technology Inc. dsPIC30F1010/202X • Programmable output polarity • Interrupt generation capability • Selectable Input sources • DAC has three ranges of operation: ...

  • Page 194

    ... Module Description The Comparator module uses a 20 nsec comparator. The comparator offset is ±5 mV typical. The negative input of the comparator is always connected to the DAC circuit. The positive input of the comparator is connected to an analog multiplexer that selects the desired source pin. ...

  • Page 195

    ... CMPPOL: Comparator Output Polarity Control bit 1 = Output is inverted 0 = Output is non inverted bit 0 RANGE: Selects DAC Output Voltage Range bit 1 = High Range: Max DAC value = Low Range: Max DAC value = INTREF, 1.2V ±1% © 2006 Microchip Technology Inc. dsPIC30F1010/202X (CMPCONx) X U-0 U-0 U-0 — — ...

  • Page 196

    ... REGISTER 17-2: COMPARATOR DAC CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Reserved: Read as ‘0’ These bits are reserved for possible future expansion of the DAC from 10 bits to more bits. ...

  • Page 197

    TABLE 17-1: ANALOG COMPARATOR CONTROL REGISTER MAP File Name ADR Bit 15 Bit 14 Bit 13 CMPON CMPSIDL CMPCON1 04C0 — CMPDAC1 04C2 — — — CMPON CMPSIDL CMPCON2 04C4 — CMPDAC2 04C6 — — — CMPON CMPSIDL CMPCON3 04C8 ...

  • Page 198

    ... NOTES: DS70178C-page 196 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 199

    ... Power-on Reset (POR). Thereafter, the clock source can be changed between permissible clock sources. The OSCCON register controls the clock switching and reflects system clock related status bits. Note: 32 kHz crystal operation is not enabled on dsPIC30F1010/202X devices. A simplified diagram of the oscillator system is shown in Figure 18-1. 18.2 Oscillator Control Registers The oscillators are controlled with these registers: • ...

  • Page 200

    ... FIGURE 18-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 TUN<3:0> 4 Internal Fast RC Oscillator (FRC) POR Done Clock Dither Circuit DS70178C-page 198 F PWM F PLL x32 x16 PLL P Lock LL Primary Osc Primary Oscillator Clock Stability Detector Switching and Control Block Oscillator ...