DSPIC30F1010-30I/SO Microchip Technology, DSPIC30F1010-30I/SO Datasheet - Page 134

• Manufacturer Part Number: DSPIC30F1010-30I/SO
• Description: IC DSPIC MCU/DSP 6K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC30F1010/202X
The FLTLEBEN and CLLEBEN bits enable the applica-
tion of the blanking period to the selected Fault and
current-limit inputs.
The
(LEB<9:3> + 1)/120 MHz.
There is a blanking period offset of 8.4 nsec. Therefore
a LEB<9:3> value of zero yields an effective blanking
period of 8.4 ns.
If a current-limit or Fault inputs are active at the end of
the previous PWM cycle, and they are still active at the
start of the new PWM cycle and the dead time is non-
zero, the Fault or current limit will be detected
regardless of the LEB counter configuration.
12.23 PWM Fault Pins
Each PWM generator can select its own Fault input
source from a selection of up to 12 Fault/current-limit
pins. In the FCLCONx registers, each PWM generator
has control bits that specify the source for its Fault input
signal. These are the FLTSRC<3:0> bits. Additionally,
each PWM generator has a FLTIEN bit in the PWM-
CONx register that enables the generation of Fault
interrupt requests. Each PWM generator has an asso-
ciated Fault Polarity bit (FLTPOL) in the FCLCONx reg-
ister that selects the active level of the selected Fault
input.
FIGURE 12-20:
DS70178C-page 132
CMP1x
CMP2x
CMP3x
CMP4x
SFLT1
SFLT2
SFLT3
SFLT4
IFLT2
IFLT4
LEB
Analog Comparator
Module
duration
PWM FAULT CONTROL LOGIC DIAGRAM
Analog Comparator 1
Analog Comparator 3
Analog Comparator 2
Analog Comparator 4
Shared Fault # 1
Shared Fault # 2
Shared Fault # 3
Shared Fault # 4
Independent Fault # 2
Independent Fault # 4
@
Generator
PWMx
30
MIPS
‘0000’
‘0001’
‘0010’
‘0011’
‘1000’
‘1001’
‘1101’
‘1111’
‘1010’
‘1011’
FLTSRC<3:0>
Preliminary
MUX
=
FLTMOD<1:0> = 00 – FLTSTAT signal is latched until Reset in software
FLTMOD<1:0> = 01 – FLTSTAT signal is Reset by PTMR every PWM cycle
FLTMOD<1:0> = 11 – FLTSTAT signal is disabled
The Fault pins actually serve two different purposes.
First is generation of Fault overrides for the PWM out-
puts. The action of overriding the PWM outputs and
generating an interrupt is performed asynchronously in
hardware so that Fault events can be managed quickly.
Second, the Fault pin inputs can be used to implement
either Current-Limit PWM mode or Current Force
mode.
PWM Fault condition states are available on the FLT-
STAT bit in the PWMCONx registers. The FLTSTAT bits
displays the Fault IRQ latch if the FIE bit is set. If Fault
interrupts are not enabled, then the FSTATx bits display
the status of the selected FLTx input in positive logic
format. When the Fault input pins are not used in asso-
ciation with a PWM generator, these pins become
general purpose I/O or interrupt input pins.
The FLTx pins are normally active high. The FLTPOL
bit in FCLCONx registers, if set to one, invert the
selected Fault input signal so that it is an active low.
The Fault pins are also readable through the PORT I/O
logic when the PWM module is enabled. This allows
the user to poll the state of the Fault pins in software.
Figure 12-20 is a diagram of the PWM Fault control
logic.
Selection
Mode
Logic
Fault
FLTMOD<1:0>
Signals
PWMxH,L
PTMR
FLTDAT<1:0>
2
2
© 2006 Microchip Technology Inc.
0
1
MUX
FLTSTAT
2
PWMxH,L