DSPIC30F1010-30I/SO Microchip Technology, DSPIC30F1010-30I/SO Datasheet - Page 174

• Manufacturer Part Number: DSPIC30F1010-30I/SO
• Description: IC DSPIC MCU/DSP 6K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC30F1010/202X
REGISTER 16-1:
DS70178C-page 172
bit 2-0
ADCS<2:0>: A/D Conversion Clock Divider Select bits
If PLL is enabled (assume 15 MHz external clock as clock source):
111 = F
110 = F
101 = F
100 = F
011 = F
010 = F
001 = F
000 = F
If PLL is disabled (assume 15 MHz external clock as clock source):
111 = F
110 = F
101 = F
100 = F
011 = F
010 = F
001 = F
000 = F
Note:
A/D CONTROL REGISTER (ADCON) (CONTINUED)
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
/18 = 13.3 MHz @ 30 MIPS
/16 = 15.0 MHz @ 30 MIPS
/14 = 17.1 MHz @ 30 MIPS
/12 = 20.0 MHz @ 30 MIPS
/10 = 24.0 MHz @ 30 MIPS
/8 = 30.0 MHz @ 30 MIPS
/6 = Reserved, defaults to 30 MHz @ 30 MIPS
/4 = Reserved, defaults to 30 MHz @ 30 MIPS
/18 = 0.83 MHz @ 7.5 MIPS
/16 = 0.93 MHz @ 7.5 MIPS
/14 = 1.07 MHz @ 7.5 MIPS
/12 = 1.25 MHz @ 7.5 MIPS
/10 = 1.5 MHz @ 7.5 MIPS
/8 = 1.87 MHz @ 7.5 MIPS
/6 = 2.5 MHz @ 7.5 MIPS
/4 = 3.75 MHz @ 7.5 MIPS
See Figure 18-2 for ADC clock derivation.
Preliminary
© 2006 Microchip Technology Inc.