T89C5121-ICUIL Atmel, T89C5121-ICUIL Datasheet

IC 8051 MCU W/SMART CARD 24SSOP

T89C5121-ICUIL

Manufacturer Part Number
T89C5121-ICUIL
Description
IC 8051 MCU W/SMART CARD 24SSOP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of T89C5121-ICUIL

Core Processor
8051
Core Size
8-Bit
Speed
16MHz
Connectivity
SmartCard, UART/USART
Peripherals
LED, POR, WDT
Number Of I /o
14
Program Memory Size
16KB (16K x 8)
Program Memory Type
Flash RAM
Eeprom Size
16K x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 5.4 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
24-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Other names
Q1468934
T89C5121-ICSIL
T89C5121-ICSIL
Features
80C51 Core
T83C5121 with 16 Kbytes Mask ROM
T85C5121 with 16 Kbytes Code RAM
T89C5121 with 16 Kbytes Code RAM and 16 Kbytes EEPROM
On-chip Expanded RAM (XRAM): 256 Bytes
Versatile Host Serial Interface
Multi-protocol Smart Card Interface
Alternate Card Support with CLK, I/O and RST According to GSM 11.12V Standard
2x I/O Ports: 6 I/O Port1 and 8 I/O Port3
2x LED Outputs with Programmable Current Sources: 2, 4, or 10 mA
Hardware Watchdog
Reset Output Includes
4-level Priority Interrupt System with 7 Sources
7.36 to 16 MHz On-chip Oscillator with Clock Prescaler
Absolute CPU Maximal Frequency: 16 MHz in X1 mode, 8MHz in X2 mode
Idle and Power-down Modes
Voltage Operation: 2.85V to 5.4V
Low Power Consumption
Temperature Range
Packages
– 12 or 6 Clocks per Instruction (X1 and X2 Modes)
– 256 Bytes Scratchpad RAM
– Dual Data Pointer
– Two 16-bit Timer/Counters: T0 and T1
– Full-duplex Enhanced UART (EUART) with Dedicated Baud Rate Generator (BRG):
– Output Enable Input
– Multiple Logic Level Shifters Options (1.8V to V
– Automatic Level Shifter Option
– Certified with Dedicated Firmware According to ISO 7816, EMV2000, GIE-CB, GSM
– Asynchronous Protocols T = 0 and T = 1 with Direct and Inverse Modes
– Baud Rate Generator Supporting All ISO7816 Speeds up to D = 32/F = 372
– Parity Error Detection and Indication
– Automatic Character Repetition on Parity Errors
– Programmable Timeout Detection
– Card Clock Stop High or Low for Card Power-down Mode
– Support Synchronous Card with C4 and C8 Programmable Outputs
– Card Detection and Automatic De-activation Sequence
– Step-up/down Converter with Programmable Voltage Output: 5V, 3V (± 8% at
– Direct Connection to Smart Card Terminals:
– Hardware Watchdog Reset
– Power-on Reset (POR)
– Power-fail Detector (PFD)
– 8 mA Operating Current (at 5.4V and 3.68 MHz)
– 150 mA Maximum Current with Smart Card Power-on (at 16 MHz X1 Mode)
– 30 A Maximum Power-down Current at 3.0V (without Smart Card)
– 100 A Maximum Power-down Current at 5.4V (without Smart Card)
– Commercial: 0 to +70 C Operating Temperature
– Industrial: -40 to +85 C Operating Temperature
– SSOP24
– QFN32
– PLCC52
Most Standard Speeds up to 230K bits/s at 7.36 MHz
11.12V and WHQL Standards
60 mA) and 1.8V (±8% at 20 mA)
Short Circuit Current Limitation
Logic Level Shifters
4 kV ESD Protection (MIL/STD 833 Class 3)
CC
)
8-bit
Microcontroller
with Multi-
protocol Smart
Card Interface
T83C5121
T85C5121
T89C5121
AT83C5121
AT85C5121
AT89C5121
Rev. 4164G–SCR–07/06

Related parts for T89C5121-ICUIL

T89C5121-ICUIL Summary of contents

Page 1

... T83C5121 with 16 Kbytes Mask ROM • T85C5121 with 16 Kbytes Code RAM • T89C5121 with 16 Kbytes Code RAM and 16 Kbytes EEPROM • On-chip Expanded RAM (XRAM): 256 Bytes • Versatile Host Serial Interface – Full-duplex Enhanced UART (EUART) with Dedicated Baud Rate Generator (BRG): Most Standard Speeds up to 230K bits/s at 7.36 MHz – ...

Page 2

... In addition, the T8xC5121 have, a Multi protocol Smart Card Interface, a dual data pointer, 2 programmable LED current sources (2-4-10 mA) and a hardware Watchdog. T89C5121 Flash RAM version and T85C5121 Code RAM version can be loaded by In- System Programming (ISP) software residing in the on-chip ROM from a low-cost exter- nal serial EEPROM or from R232 interface ...

Page 3

Pin Description 4164G–SCR–07/06 Figure 2. 24-pin SSOP Pinout CVSS P1.5/CRST 4 P1.4/CCLK P1.3/CC4 P1.2/CPRES P1.1/CC8 P1.0/CIO RST 10 XTAL2 XTAL1 12 Figure 3. QFN32 Pinout 32 1 CVcc P1.5/CRST 2 P1.4/CCLK 3 P1.3/CC4 4 P1.2/CPRES 5 ...

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A/T8xC5121 4 Figure 4. PLCC52 Pinout P1.4/CCLK 9 P1.3/CC4 PSEN ALE 12 13 P2.7/A15 14 P2.6/A14 15 P2.5/A13 16 P1.2/CPRES 17 P1.1/CC8 P1.0/CIO 18 P2.4/A12 19 RST 20 21 ...

Page 5

Signals Table 1. Ports Description Signal Port Name Alternate P1.0 CIO P1.1 CC8 P1.2 CPRES P1.3 CC4 P1.4 CCLK P1.5 CRST 4164G–SCR–07/06 All the T8xC5121 signals are detailed in Table 1. The port structure is described in Section “Port Structure ...

Page 6

Table 1. Ports Description (Continued) Signal Port Name Alternate P3.0 RxD P3.1 TxD P3.2 INT0 P3.3 INT1 OE P3.4 T0 A/T8xC5121 6 Internal Power Supply ESD Type Description UART function Receive data input Input/Output function I/O P3.0 ...

Page 7

Table 1. Ports Description (Continued) Signal Port Name Alternate P3.5 CIO1 P3.6 CCLK1 LED0 P3.7 CRST1 P3.7 CRST1 LED1 4164G–SCR–07/06 Internal Power Supply ESD Type Description Input/Output function I/O P3 bi-directional I/O port with internal pull-ups. Timer 0 ...

Page 8

Table 1. Ports Description (Continued) Signal Port Name Alternate RST XTAL1 XTAL2 CVSS VSS A/T8xC5121 8 Internal Power Supply ESD Type Description V I/O Reset input CC Holding this pin low ...

Page 9

Table 1. Ports Description (Continued) Signal Port Name Alternate ONLY FOR PLCC52 version P0[7:0] AD[7:0] P2[7:0] A[15:8] P3.6 WR P3.7 RD ALE PSEN PSEN EA EA 4164G–SCR–07/06 Internal Power Supply ESD Type Description V I/O Input/Output function Port 0 CC ...

Page 10

Port Structure Description Quasi Bi-directional Output Configuration Figure 5. Quasi Bi-directional Output Configuration Port latch Data Push-pull Output Configuration A/T8xC5121 10 The different ports structures are described as follows. The default port output configuration for standard I/O ports is the ...

Page 11

Figure 6. Push-pull Output Configuration Port latch Data LED Output Configuration Figure 7. LED Source Current Configuration 2 CPU CLOCK DELAY LEDx.0 Port Latch Data LEDx.1 Note: The port can be configured in quasi bi-directional mode and the level of ...

Page 12

SFR Mapping A/T8xC5121 12 The Special Function Registers (SFR) of the T8xC5121 belongs to the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3 • Timer 0 registers: TCON, ...

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Table 2. SFR Addresses and Reset Values 0/8 1/9 F8h F0h B LEDCON 0000 0000 XXXX 0000 E8h E0h ACC 0000 0000 D8h D0h PSW RCON 0000 0000 XXXX OXXX C8h C0h B8h IPL0 SADEN XXX0 0000 0000 0000 B0h ...

Page 14

PowerMonitor Description Figure 8. PowerMonitor Block Diagram External V DD Power Supply PowerMonitor Diagram A/T8xC5121 14 The PowerMonitor function supervises the evolution of the voltages feeding the micro- controller, and if needed, suspends its activity when the detected value is ...

Page 15

Figure 9. Power-Up and Steady-state Conditions Monitored DV CC VPFDP VPFDM t G Power-up t rise Reset V CC 4164G–SCR–07/06 Steady-state Condition Such device when it is integrated in a microcontroller, forces the CPU in reset mode when V reaches ...

Page 16

Power Monitoring and Clock Management Idle Mode Power-down Mode Entering Power-down Mode Exit from Power-down Mode A/T8xC5121 16 For applications where power consumption is a critical factor, three power modes are provided: • Idle mode • Power-down mode • Clock ...

Page 17

Figure 10. Power-down Exit Waveform INT0 INT1 XTAL1 Active phase SCI Control LED Control Low Power Mode 4164G–SCR–07/06 The ports status under Power-down is the status which was valid before entering this mode. The INT1 interrupt is a multiplexed input ...

Page 18

Reduced EMI Mode Power Modes Control Registers A/T8xC5121 18 The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still ...

Page 19

Table 4. AUXR Register AUXR (S:8Eh) Auxiliary Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Low Power mode selection ...

Page 20

A/T8xC5121 20 Table 5. IE0 Register IE0 Interrupt Enable Register (A8h Bit Bit Number Mnemonic Description Enable All interrupt bit Clear to disable all interrupts Set to enable all interrupts ...

Page 21

Table 6. ISEL Register ISEL (S:BAh) Interrupt Enable Register CPLEV - RXIT Bit Bit Number Mnemonic Description Card presence detection level This bit indicates which CPRES level will bring about an interrupt Set this bit to ...

Page 22

Clock Management Functional Block Diagram A/T8xC5121 22 In order to optimize the power consumption and the execution time needed for a specific task, an internal prescaler feature and a X2 feature have been implemented between the oscillator and the CPU. ...

Page 23

X2 Feature Description Figure 12. Mode Switching Waveforms XTAL1 XTAL1:2 X2 bit CPU clock STD Mode 4164G–SCR–07/06 The T8xC5121 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages: • Divides frequency crystals ...

Page 24

Clock Prescaler Clock Control Registers Clock Prescaler Register A/T8xC5121 24 Before supplying the CPU and the peripherals, the main clock is divided by a factor reduce the CPU power consumption. This factor is controlled with the ...

Page 25

Table 9. CKCON0 Register CKCON0 - Clock Control Register (8Fh WDX2 - Bit Bit Number Mnemonic Description 7 - Reserved Watchdog clock (This control bit is validated when the CPU clock X2 is set; when ...

Page 26

A/T8xC5121 26 Table 10. CKCON1 Register CKCON1 - Clock Control Register (AFh Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved SCIB clock Clear to select ...

Page 27

DC/DC Clock Clock Control Register Clock Prescaler 4164G–SCR–07/06 The DC/DC block needs a clock with a 50% duty cycle. The frequency must also respect a value between 3.68 MHz and 4 MHz. The first requirement imposes a divider in the ...

Page 28

A/T8xC5121 28 4164G–SCR–07/06 ...

Page 29

Smart Card Interface Block (SCIB) Introduction Main Features 4164G–SCR–07/06 The SCIB provides all signals to directly interface a smart card. Compliance with the ISO7816, EMV’2000, GSM and WHQL standards has been certified. Both synchronous (e.g. memory card) and asynchronous smart ...

Page 30

Block Diagram Functional Description Barrel Shifter SCART FSM A/T8xC5121 30 The Smart Card Interface Block diagram is shown in Figure 14. Figure 14. SCIB Block Diagram Barrel shifter Clk_iso Clk_cpu Etu counter Guard time counter Waiting time counter SCI Registers ...

Page 31

ETU Counter Guard Time Counter 4164G–SCR–07/06 the different counters. One of the most important counters is the guard time counter that gives time slots corresponding to the character frame enabled only in UART mode. The transition from the ...

Page 32

Waiting Time Counter (WT) Figure 16. Waiting Time Counter ETU Counter WTEN Write_SCWT2 UART Start bit A/T8xC5121 32 The WT counter bits down counter which can be loaded with the value contained in the SCWT2, SCWT1, SCWT0 ...

Page 33

Power-on and Power-off FSM 4164G–SCR–07/06 Figure 17 Mode > GT CHAR 1 Figure 18 Mode Transmission BLOC 1 CHAR n CHAR 1 CHAR 2 < CWT In this state, the machine applies the signals ...

Page 34

Interrupt Generator Registers A/T8xC5121 34 There are several sources of interruption but the SCIB macro-cell issues only one inter- rupt signal: SCIB IT. Figure 20. SCIB Interrupt Sources Transmit buffer copied to shift register ESCTBI Output current out of range ...

Page 35

Other Features Clock Alternate Card 4164G–SCR–07/06 The Ck-ISO input must be in the range MHz according to ISO7816. The ISO Clock diagram and the configuration examples are shown in Figure 20. Figure 21. Clock Diagram of the ...

Page 36

Card Presence Input SCIB Reset A/T8xC5121 36 Figure 22. Alternate Card F CK_IDLE CK_IDLE PR3 P3.6 ALTKPS0,1 SCSR Reg. SCSR Reg. The internal pull-up on Card Presence input can be disconnected in order to ...

Page 37

DC/DC Converter 4164G–SCR–07/06 The Smart Card supply voltage ( controlled by several registers: • The register described in Section “SCICR Register” controls the CVCC voltage with bits CVcc0, CVcc1 • The register described in Section “SCCON Register”, switches ...

Page 38

Registers Description A/T8xC5121 38 Table 15. SCICR Register SCICR (S:B6h, SCRS = 1) Smart Card Interface Control Register RESET CARDDET CVcc1 Bit Number Bit Mnemonic Description Reset 7 RESET Set this bit to reset the SCIB and ...

Page 39

Table 16. SCCON Register SCCON (S:ACh, SCRS = 0) Smart Card Contacts Register CLK - CARDC8 Bit Number Bit Mnemonic Description Card Clock Selection Clear this bit to use the CardClk bit (CARDCLK) to drive Card ...

Page 40

A/T8xC5121 40 Table 17. SCISR Register SCISR (S:ADh, SCRS = 0) Smart Card UART Interface Status Register SCTBE CARDIN CIccOVF Bit Bit Number Mnemonic Description SCIB transmit buffer empty This bit is set by hardware when the ...

Page 41

Table 18. SCIIR Register SCIIR (S:AEh, SCRS = 0) Smart Card UART Interrupt Identification Register (read only SCTBI - CIccERR CVccERR Bit Number Bit Mnemonic Description SCIB transmit buffer interrupt This bit is set by hardware ...

Page 42

A/T8xC5121 42 Table 19. SCIER Register SCIER (S:AEh, SCRS = 1) Smart Card UART Interrupt Enable Register ESCTBI - CIccER Bit Bit Number Mnemonic Description Smart Card UART Transmit Buffer Empty Interrupt Enable 7 ESCTBI Clear this ...

Page 43

Table 20. SCSR Register SCSR (S:ABh) Smart Card Selection Register Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved Character repetition selection 4 CREPSEL Clear this bit to ...

Page 44

A/T8xC5121 44 Table 22. SCRBUF Register SCRBUF (S:AA read-only, SCRS = 1) Smart Card Receive Buffer Register – – – Bit Bit Number Mnemonic Description Provides the byte received from the I/O pin when SCRI is set. ...

Page 45

Table 24. SCETU0 Register SCETU0 (S:ACh, SCRS = 1) Smart Card ETU Register ETU7 ETU6 ETU5 Bit Bit Number Mnemonic Description ETU LSB The Elementary Time Unit is (ETU[10:0] - 0.5*COMP)/f, where f is the ...

Page 46

A/T8xC5121 46 Table 27. SCWT2 Register SCWT2 (S:B6h, SCRS = 0) Smart Card Character/Block Wait Time Register WT23 WT22 WT21 Bit Bit Number Mnemonic Description Wait Time Byte 2 7-0 WT[23:16] Used together with WT[15:0] (see ...

Page 47

Interrupt System Figure 23. Interrupt Control System INT0 TF0 RXEN Rxd OEEN 1 INT1/OE 0 OELEV PRESEN 0 CPRES 1 CPLEV TF1 RI TI SCI 4164G–SCR–07/06 The T8xC5121 has a total of 6 interrupt vectors: four external interrupts (INT0, INT1/OE, ...

Page 48

INT1 Interrupt Vector INT1/OE Input Rxd Input CPRES Input A/T8xC5121 48 A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If ...

Page 49

Table 32. IE0 Register Bit Bit Number Mnemonic Description Enable All interrupt bit Clear to disable all interrupts Set to enable all interrupts each interrupt source is ...

Page 50

A/T8xC5121 50 Table 33. IE1 Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from ...

Page 51

Table 34. TCON Register TCON (S:88h) Timer 0/Counter Control Register TF1 TR1 TF0 Bit Bit Number Mnemonic Description Timer 1 Overflow flag Cleared by the hardware when processor vectors to interrupt routine. 7 TF1 Set by ...

Page 52

A/T8xC5121 52 Table 35. ISEL Register CPLEV OEIT PRESIT Bit Bit Number Mnemonic Description Card presence detection level This bit indicates which CPRES level will bring about an interrupt Set this bit to indicate that Card Presence ...

Page 53

Table 36. IPL0 Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this ...

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A/T8xC5121 54 Table 37. IPL1 Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from ...

Page 55

Table 38. IPH0 Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this ...

Page 56

A/T8xC5121 56 Table 39. IPH1 Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from ...

Page 57

LED Ports Configuration Registers Definition 4164G–SCR–07/06 The current source of the LED Ports can be adjusted to 3 different values mA. The LED output is an alternate function of P3.6 an P3.7 and cannot be used ...

Page 58

Dual Data Pointer A/T8xC5121 58 T8xC5121 contains a Dual Data Pointer accelerating data memory block moves. The Standard 80C52 Data Pointer is a 16-bit value that is used to address off-chip data RAM or peripherals. In T8xC5121, the standard 16-bit ...

Page 59

Table 43. AUXR1 Register AUXR1 - Dual Pointer Selection Register (A2h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...

Page 60

Memory Management Program Memory ROM Configuration Byte Program ROM Lock Bits A/T8xC5121 60 All the T8xC5121 versions implement 16 Kbytes of ROM memory, 256 Bytes RAM and 256 Bytes XRAM. The hardware configuration byte and the split of internal memory ...

Page 61

... Memory Mapping T89C5121 Flash ROM Version 4164G–SCR–07/06 In the products versions, the following internal spaces are defined: • RAM • XRAM • CRAM: 16 KBytes Program RAM Memory • ROM The specific accesses from/to these memories are: • XRAM: if the bit RPS in RCON (described below) is reset, MOVX instructions address the XRAM space. • ...

Page 62

T85C121 Code RAM Version A/T8xC5121 serial communication device (as described above: TWI or RS232) is detected, the program download its content in the internal EEPROM and in CRAM. Else, the program is internally downloaded from the internal ...

Page 63

T83C5121 with Mask ROM Version In-System Programming Hardware Interface 4164G–SCR–07/06 Figure 25. CRAM and ROM Mappings FFFFh F800h entry point C000h Bootloader 3FFFh 0000h ROM In this version, the customer program is masked in 16 Kbytes ROM. • The customer ...

Page 64

Figure 26. Hardware in Relation with the Two Communication Protocols DV CC P3.2/INT0 P3.7/CRST1 V CC P2.1 P2.0 BOOTLOADER UART EEPROM Mapping A/T8xC5121 64 TWI SDA SCL TWI SDA SCL Internal EEPROM AT24C128 Address = 00h A0 ...

Page 65

... A serial code is sent on RD pin (P3.7) A/T8xC5121 ROM ROM program Execution 0000h Program is downloaded from External EEPROM into internal EEPROM and CRAM and executed. An ISP Software can be used from program the part. Atmel FLIP software is available Program is downloaded from internal EEPROM in CRAM and executed 65 ...

Page 66

In-System Programming Timings Protection Mechanisms Transfer Checks A/T8xC5121 66 The download from the internal EEPROM to CRAM is executed after 4 seconds when operating at 12 MHz frequency. In order to verify that the transfers are free of errors, a ...

Page 67

Read/Write Protection Lock Byte 4164G–SCR–07/ ...

Page 68

Configuration Bits A/T8xC5121 68 The only mean to remove the security level send a Full Chip Erase command. Data Bytes Table 48. Synthesis of Security Mechanisms Source Function Protection Internal The first protection level of the SSB ...

Page 69

UART Protocol Overview Physical Layer Datas and Limits Frame Description 4164G–SCR–07/06 Table 49. Valid Software Security Byte Values SSB Values FE FC BF,BE,BC 7F,7E,7C 3F,3E,3C The serial protocol used is described below. The UART is used to transmit information with ...

Page 70

Command Description A/T8xC5121 70 • Record Type: – Record Type specifies the command type. This field is used to interpret the remaining information within the frame. The encoding for all the current record types are described in Table 51. • ...

Page 71

Autobaud Table 52. Autobaud Performances Frequency (MHz) Baudrate (kHz) 6.176 9600 OK 19200 OK 38400 - 57600 - 115200 - Protection Mechanisms Transfer Checks Security 4164G–SCR–07/06 The ISP feature allows a wide range of baud rates in the user application. ...

Page 72

A/T8xC5121 72 Source Target UART ISP Intern. EEP UART ISP CRAM SSB in EEP and UART ISP CRAM SSB in EEP and UART ISP CRAM Case Protection SSB level 1 must be set (done, if Programming selected, at ISP Programming ...

Page 73

Timers/Counters Introduction Timer 0/Counter Operations 4164G–SCR–07/06 The T8xC5121 implements two general-purpose, 16-bit Timer 0s/Counters. Although they are identified as Timer 0, Timer 1, you can independently configure each to operate in a variety of modes as a Timer 0 or ...

Page 74

Timer 0 Mode 0 (13-bit Timer 0) Figure 28. Timer 0/Counter Mode 0 FCLK_Periph Tx C/Tx# TMOD reg INTx# GATEx TMOD reg Mode 1 (16-bit Timer 0) A/T8xC5121 74 Timer 0 functions as ...

Page 75

Figure 29. Timer 0/Counter Mode 1 FCLK_Periph Tx INTx# GATEx TMOD reg Mode 2 (8-bit Timer 0 with Auto-Reload) Figure 30. Timer 0/Counter Mode 2 FCLK_Periph ...

Page 76

Figure 31. Timer 0/Counter 0 in Mode 3: Two 8-bit Counters FCLK_Periph T0 C/T0# TMOD.2 INT0 GATE0 TMOD.3 FCLK_Periph A/T8xC5121 TR0 TCON.4 TR1 TCON.6 Overflow TL0 TF0 (8 bits) TCON.5 Overflow TH0 TF1 (8 bits) TCON.7 Timer ...

Page 77

Timer 1 Mode 0 (13-bit Timer 0) Mode 1 (16-bit Timer 0) Mode 2 (8-bit Timer 0 with Auto-Reload) Mode 3 (Halt) 4164G–SCR–07/06 Timer 1 is identical to Timer 0 except for Mode 3 which is a hold-count mode. The ...

Page 78

Registers A/T8xC5121 78 Table 55. TCON Register TCON (S:88h) - Timer 0/Counter Control Register TF1 TR1 TF0 Bit Bit Number Mnemonic Description Timer 1 Overflow flag Cleared by the hardware when processor vectors to interrupt routine. 7 ...

Page 79

Table 56. TMOD Register TMOD (S:89h) - Timer 0/Counter Mode Control Registers 7 6 GATE1 C/T1# Bit Number Bit Mnemonic Description Timer 1 Gating Control bit 7 GATE1 Clear to enable Timer 1 whenever TR1 bit is set. Set to ...

Page 80

A/T8xC5121 80 Table 57. TH0 Register TH0 (S:8Ch) - Timer 0 High Byte Register Bit Bit Number Mnemonic Description 7:0 High Byte of Timer 0 Reset Value = 0000 0000b Table 58. TL0 Register TL0 (S:8Ah) - ...

Page 81

Serial I/O Port Framing Error Detection 4164G–SCR–07/06 The serial I/O port is entirely compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) ...

Page 82

Automatic Address Recognition Given Address A/T8xC5121 82 Figure 34. UART Timings in Mode 1 RXD D0 D1 Start Bit RI SMOD0 = X FE SMOD0 = 1 Figure 35. UART Timings in Modes 2 and 3 RXD D0 D1 Start ...

Page 83

Broadcast Address 4164G–SCR–07/06 To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR0101 0110b SADEN1111 1100b Given0101 01XXb The following is an example of how to use given addresses to address ...

Page 84

Reset Addresses UART Output Configuration Voltage Level Output Enable Function A/T8xC5121 84 On reset, the SADDR, SADEN register are initialized to 00h, i.e. the given and broad- cast addresses are XXXX XXXXb (all don’t care bits). This ensures that the ...

Page 85

UART Control Registers 4164G–SCR–07/06 Table 61. SADEN Register SADEN Slave Address Mask Register (B9h Reset Value = 0000 0000b Table 62. SADDR Register SADDR Slave Address Register (A9h Reset Value = 0000 0000b Table ...

Page 86

UART Timings Mode Selection Baud Rate Generator Timer 1 Figure 36. Timer 1 Baud Rate Generator Block Diagram PER 6 0 CLOCK 1 T1 C/T1# TMOD.6 INT1 GATE1 TR1 TMOD.7 TCON.6 Internal Baud Rate Generator A/T8xC5121 86 The following description ...

Page 87

Figure 37. Internal Baud Rate Generator Block Diagram PER 6 0 CLOCK 1 SPD BDRCON.1 Synchronous Mode (Mode 0) Figure 38. Serial I/O Port Block Diagram (Mode 0) SCON.6 SM1 Mode Decoder Mode Controller TI SCON.1 ...

Page 88

Reception (Mode 0) Baud Rate Selection (Mode 0) A/T8xC5121 88 To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI bits and setting the REN bit. As shown in Figure 40, Clock is pulsed ...

Page 89

Asynchronous Modes (Modes 1, 2 and 3) Figure 43. Serial I/O Port Block Diagram (Modes 1, 2 and 3) T1 CLOCK IBRG CLOCK PER CLOCK SM2 SCON.4 Mode 1 Figure 44. Data Frame Format (Mode 1) Mode 1 Modes 2 ...

Page 90

Framing Error Detection (Modes 1, 2 and 3) Baud Rate Selection (Modes 1 and 3) Figure 47. Baud Rate Source Selection (Modes 1 and 3) T1 CLOCK 0 1 IBRG CLOCK RBCK BDRCON.2 A/T8xC5121 90 Framing error detection is provided ...

Page 91

Baud Rate Selection (Mode 2) 4164G–SCR–07/06 Table 65. Internal Baud Rate Generator Value MHz PER Baud Rate SPD SMOD1 115200 - - 57600 - - 38400 1 1 19200 1 1 9600 1 1 4800 1 1 ...

Page 92

A/T8xC5121 92 Table 66. BRL (S:91h) BRL Register Baud Rate Generator Reload Register BRL7 BRL6 BRL5 Bit Bit Number Mnemonic Description BRL7:0 Baud Rate Reload Value. Reset Value = 0000 0000b ...

Page 93

Table 67. SCON Register SCON (S:98h) Serial Control Registe 7 6 FE/SM0 SM1 Bit Bit Number Mnemonic Description Framing Error bit To select this function, set SMOD0 bit in PCON register. FE Set by hardware to indicate an invalid stop ...

Page 94

A/T8xC5121 94 Table 68. BDRCON Register BDRCON Baud Rate Control Register (9Bh Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit Reserved ...

Page 95

Table 69. SIOCON Register Serial Input Output Configuration Register Register (91h PMSOEN1 PMSOEN0 - Bit Bit Number Mnemonic Description Output Enable function on Txd/P3.1 and T0/P3.4: PMSOEN1 PMSOEN0 PMOSEN1 PMOSEN0 0 1 ...

Page 96

Hardware Watchdog Timer Using the WDT A/T8xC5121 96 The WDT is intended as a recovery method in situations where the CPU may be sub- jected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer ReSeT ...

Page 97

WDT during Power-down and Idle 4132C–SCR–07/06 Table 71. WDTPRG Register WDTPRG - Watchdog Timer Out Register (0A7h Bit Bit Number Mnemonic Description Reserved 5 - The value read from this ...

Page 98

Electrical Characteristics Absolute Maximum Ratings Ambiant Temperature Under Bias ......................- Storage Temperature ................................... - 150 C Voltage ........................................-0. 6. Voltage on Any Pin to V ...

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The operating conditions for I Tests are the following: CC Figure 51. I Test Condition, Active Mode RST EA XTAL2 (NC) XTAL1 CLOCK SIGNAL V SS Figure 52. I ...

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A/T8xC5121 100 Table 73. Serial Interface DC parameters (P3.0, P3.1, P3.3 and P3.4) Symbol Parameter Min -0.5 -0.5 V Input Low Voltage -0.5 IL 1.4 1.6 V Input High Voltage 2 Output Low V OL Voltage ...

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Table 75. Smart Card 5V Interface DC Parameters Symbol Parameter Min Card Supply Current Card Supply CV 4.6 CC Voltage CV Ripple on CVcc CC CV Spikes on CVcc 4 CVcc to 0 VHLl ...

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A/T8xC5121 102 Table 78. Smart Card Clock DC Parameters (Port P1.4) Symbol Parameter Min 0(1) Output Low V OL Voltage 0(1) Output Low I OL Current 0 Output High V 0 Voltage CV CC Output ...

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Table 80. Smart Card I/O DC Parameters (P1.0) Symbol Parameter Min 0(1) V Input Low Voltage IL 0(1) I Input Low Current IL V Input High Voltage 0 Input High Current IH Output Low V ...

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A/T8xC5121 104 Table 82. Smart Card RST, CC4, CC8, DC Parameters (Port P1.5, P1.3, P1.1) Symbol Parameter Min V Output Low Voltage OL I Output Low Current Output High Voltage OH 0 Output ...

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Typical Application Figure 54. Typical Application Diagram 4.7 µ ( Serial Interface RTS OE TxD RxD Notes and C5 must be placed near IC and have low ...

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A/T8xC5121 106 6. Distance between Device pads and Smart Card connector must be less than 4 centimeters. 7. C6,C7 should be as close as possible to the Smart Card connector to reduce noise and interferences. 4164G–SCR–07/06 ...

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... AT85C5121- 16K RAM ICRUL AT85C5121- 16K RAM S3SUL AT85C5121- 16K RAM S3RUL AT89C5121- 16K Flash RAM ICSUL AT89C5121- 16K Flash RAM ICRUL Note: 1. Contact Atmel for availability. 4164G–SCR–07/06 Temperature Supply Voltage Range Max Frequency 2.85 - 5.4V Industrial 2.85 - 5.4V Industrial 2 ...

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Package Drawings SSOP24 A/T8xC5121 108 4164G–SCR–07/06 ...

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PLCC52 4164G–SCR–07/06 A/T8xC5121 109 ...

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QFN32 A/T8xC5121 110 4164G–SCR–07/06 ...

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Document Revision History for T8xC5121 Changes from 4164B - 06/02 to 4164C - 07/03 Changes from 4164C - 07/03 to 4164D - 12/03 Changes from 4164D - 12/03 to 4164E - 01/04 Changes from 4164E - 01/04 to 4164F 11/05 ...

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Table of Features ................................................................................................. 1 Contents Description ............................................................................................ 2 Block Diagram ...................................................................................... 2 Pin Description ..................................................................................... 3 Signals ...................................................................................................................5 Port Structure Description....................................................................................10 SFR Mapping ....................................................................................... 12 PowerMonitor ...................................................................................... 14 Description.......................................................................................................... 14 PowerMonitor Diagram ....................................................................................... 14 Power Monitoring and Clock Management ...

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Memory Management ......................................................................... 60 Timers/Counters ................................................................................. 73 Serial I/O Port ...................................................................................... 81 UART Timings ..................................................................................... 86 Hardware Watchdog Timer ................................................................ 96 Electrical Characteristics ................................................................... 98 Typical Application ........................................................................... 105 Ordering Information........................................................................ 107 Package Drawings............................................................................ 108 Document Revision History for T8xC5121 ...

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Changes from 4164E - 01/04 to 4164F 11/05 .................................................. 111 Changes from 4164F 11/05 to 4164F 07/06..................................................... 111 Table of Contents .................................................................................. i A/T8xC5121 iii 4164G–SCR–07/06 ...

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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to anyintellectu- alproperty right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORYWAR- RANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICU- LARPURPOSE, OR NON-INFRINGEMENT ...

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