IC DSPIC MCU/DSP 16K 28-SOIC

DSPIC33FJ16GS502-I/SO

Manufacturer Part NumberDSPIC33FJ16GS502-I/SO
DescriptionIC DSPIC MCU/DSP 16K 28-SOIC
ManufacturerMicrochip Technology
SeriesdsPIC™ 33F
DSPIC33FJ16GS502-I/SO datasheets
 

Specifications of DSPIC33FJ16GS502-I/SO

Core ProcessordsPICCore Size16-Bit
Speed40 MIPsConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o21
Program Memory Size16KB (16K x 8)Program Memory TypeFLASH
Ram Size2K x 8Voltage - Supply (vcc/vdd)3 V ~ 3.6 V
Data ConvertersA/D 8x10b; D/A 1x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case28-SOIC (7.5mm Width)
Core Frequency40MHzCore Supply Voltage3.3V
Embedded Interface TypeI2C, SPI, UARTNo. Of I/o's21
Flash Memory Size16KBSupply Voltage Range3V To 3.6V
Package28SOIC WDevice CoredsPIC
Family NamedsPIC33Maximum Speed40 MHz
Operating Supply Voltage3.3 VData Bus Width16 Bit
Number Of Programmable I/os21Interface TypeI2C/SPI/UART
On-chip Adc8-chx10-bitNumber Of Timers3
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
Preliminary
© 2009 Microchip Technology Inc.
DS70318D

DSPIC33FJ16GS502-I/SO Summary of contents

  • Page 1

    ... Microchip Technology Inc. High-Performance, 16-bit Digital Signal Controllers Preliminary Data Sheet DS70318D ...

  • Page 2

    ... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

  • Page 3

    ... Source/Sink on All PWM pins On-Chip Flash and SRAM: • Flash Program Memory ( Kbytes) • Data SRAM ( Kbytes) • Boot and General Security for Program Flash © 2009 Microchip Technology Inc. dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Peripheral Features: • Timer/Counters Three 16-Bit Timers: - Can pair up to make one 32-bit timer • ...

  • Page 4

    ... Power-up Timer (PWRT) • Oscillator Start-up Timer (OST) • Watchdog Timer with its RC Oscillator • Fail-Safe Clock Monitor (FSCM) • Reset by Multiple Sources • In-Circuit Serial Programming™ (ICSP™) • Reference Oscillator Output Preliminary © 2009 Microchip Technology Inc. ...

  • Page 5

    ... Renewable Power/Pure Sine Wave Inverters • Uninterruptible Power Supply (UPS) Packaging: • 18-Pin SOIC • 28-Pin SPDIP/SOIC/QFN-S • 44-Pin TQFP/QFN See the dsPIC33FJ06GS101/X02 and Note: dsPIC33FJ16GSX02/X04 Families table for the exact peripheral features per device. © 2009 Microchip Technology Inc. Controller Preliminary DS70318D-page 3 ...

  • Page 6

    ... Controller Families Device dsPIC33FJ06GS101 18 6 256 dsPIC33FJ06GS102 28 6 256 16 dsPIC33FJ06GS202 dsPIC33FJ16GS402 dsPIC33FJ16GS404 dsPIC33FJ16GS502 dsPIC33FJ16GS504 The PWM4H:PWM4L pins are remappable. Note 1: The PWM Fault pins and PWM synchronization pins are remappable. 2: Only two out of three interrupts are remappable. 3: DS70318D-page 4 Remappable Peripherals ( 2x2 ...

  • Page 7

    ... AN2/CMP1C/CMP2A/RA2 AN3/CMP1D/CMP2B/RP0 AN4/CMP2C/RP9 AN5/CMP2D/RP10 OSC1/CLKIN/RP1 OSC2/CLKO/RP2 PGED2/DACOUT/INT0/RP3 PGEC2/EXTREF/RP4 PGED3/RP8 The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and Note 1: dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals © 2009 Microchip Technology Inc. MCLR AN0/RA0 AN1/RA1 PWM1L/RA3 ...

  • Page 8

    ... TCK/PWM3L/RP12 TMS/PWM3H/RP11 (1) /CN1/RB1 CAP DD (1) /CN2/RB2 PGEC1/SDA/RP7 (1) PGED1/TDI/SCL/RP6 /CN4/RB4 TDO/RP5 PGEC3/RP15 Preliminary = Pins are tolerant (1) /CN14/RB14 (1) /CN13/RB13 (1) /CN12/RB12 (1) /CN11/RB11 C ORE (1) /CN7/RB7 (1) /CN6/RB6 (1) /CN5/RB5 = Pins are tolerant (1) /CN14/RB14 (1) /CN13/RB13 (1) /CN12/RB12 (1) /CN11/RB11 C ORE (1) /CN7/RB7 (1) /CN6/RB6 (1) /CN6/RB5 (1) /CN15/RB15 © 2009 Microchip Technology Inc. ...

  • Page 9

    ... The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and Note 1: dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected externally. SS © 2009 Microchip Technology Inc ...

  • Page 10

    ... TMS/PWM3H/RP11 dsPIC33FJ16GS402 CAP (1) /CN1/RB1 (1) /CN2/RB2 7 15 PGEC1/SDA/RP7 PWM2L/RP14 (1) /CN0/RB0 2 20 PWM2H/RP13 (1) /CN9/RB9 3 19 TCK/PWM3L/RP12 /CN10/RB10 4 18 TMS/PWM3H/RP11 dsPIC33FJ16GS502 CAP (1) /CN1/RB1 (1) /CN2/RB2 PGEC1/SDA/RP7 Preliminary = Pins are tolerant (1) /CN14/RB14 (1) /CN13/RB13 (1) /CN12/RB12 (1) /CN11/RB11 / ORE (1) /CN7/RB7 = Pins are tolerant (1) /CN14/RB14 (1) /CN13/RB13 (1) /CN12/RB12 (1) /CN11/RB11 / ...

  • Page 11

    ... The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and Note 1: dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected externally. SS © 2009 Microchip Technology Inc ...

  • Page 12

    ... The metal plane at the bottom of the device is not connected to any pins and is recommended to connect externally. DS70318D-page dsPIC33FJ16GS504 Preliminary = Pins are tolerant (1) OSC2/CLKO/AN7/CMP3D/CMP4B/RP2 /CN2/RB2 (1) OSC1/CLKI/AN6/CMP3C/CMP4A/RP1 /CN1/RB1 (1) AN8/CMP4C/RP17 /CN17/RC1 (1) AN10/RP26 /CN26/RC10 (1) AN11/RP25 /CN25/RC9 (1) AN5/CMP2D/CMP3B/RP10 /CN10/RB10 AN4/CMP2C/CMP3A/RP9 (1) /CN9/RB9 (1) AN3/CMP1D/CMP2B/RP0 /CN0/RB0 AN2/CMP1C/CMP2A/RA2 SS © 2009 Microchip Technology Inc. ...

  • Page 13

    ... CAP DD ORE (1) TMS/PWM3H/RP11 /CN11/RB11 (1) TCK/PWM3L/RP12 /CN12/RB12 (1) PWM2H/RP13 /CN13/RB13 PWM2L/RP14 (1) /CN14/RB14 The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and Note 1: dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals © 2009 Microchip Technology Inc dsPIC33FJ16GS404 Preliminary ...

  • Page 14

    ... The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and Note 1: dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals DS70318D-page 12 OSC2/CLKO/AN7/CMP3D/CMP4B/RP2 33 OSC1/CLKI/AN6/CMP3C/CMP4A/RP1 32 AN8/CMP4C/RP17 dsPIC33FJ16GS504 AN10/RP26 28 AN11/RP25 27 AN5/CMP2D/CMP3B/RP10 26 AN4/CMP2C/CMP3A/RP9 25 AN3/CMP1D/CMP2B/RP0 24 23 AN2/CMP1C/CMP2A/RA2 Preliminary = Pins are tolerant (1) /CN2/RB2 (1) /CN1/RB1 (1) /CN17/RC1 (1) /CN26/RC10 (1) /CN25/RC9 (1) /CN10/RB10 (1) /CN9/RB9 (1) /CN0/RB0 © 2009 Microchip Technology Inc. ...

  • Page 15

    ... Electrical Characteristics .......................................................................................................................................................... 283 25.0 Packaging Information.............................................................................................................................................................. 317 Appendix A: Revision History............................................................................................................................................................. 329 Index ................................................................................................................................................................................................. 337 The Microchip Web Site ..................................................................................................................................................................... 341 Customer Change Notification Service .............................................................................................................................................. 341 Customer Support .............................................................................................................................................................................. 341 Reader Response .............................................................................................................................................................................. 342 Product Identification System ............................................................................................................................................................ 343 © 2009 Microchip Technology Inc. Preliminary DS70318D-page 13 ...

  • Page 16

    ... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70318D-page 14 Preliminary © 2009 Microchip Technology Inc. ...

  • Page 17

    ... X04 devices contain extensive Digital Signal Processor (DSP) functionality with a high-performance, 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices ...

  • Page 18

    ... Latch Control Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support MCLR OC1 ADC1 UART1 OC2 IC1,2 CNx I2C1 Preliminary PORTA PORTB 16 PORTC Remappable Pins 16-Bit ALU 16 PWM SPI1 © 2009 Microchip Technology Inc. ...

  • Page 19

    ... TDI I TTL TDO O — Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-Transistor Logic © 2009 Microchip Technology Inc. PPS Capable No Analog input channels No External clock source input. Always associated with OSC1 pin function. No Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...

  • Page 20

    ... Ground reference for analog modules No Positive supply for peripheral logic and I/O pins No CPU logic filter capacitor connection No Ground reference for logic and I/O pins Analog = Analog input P = Power PPS = Peripheral Pin Select Preliminary Description I = Input O = Output © 2009 Microchip Technology Inc. ...

  • Page 21

    ... Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 “External Oscillator Pins”) © 2009 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required ...

  • Page 22

    ... Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V IH for Preliminary and V ) and fast signal shown in Figure 2-2, it EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR dsPIC33F JP C and V specifications are met and V specifications are met. IL © 2009 Microchip Technology Inc. is ...

  • Page 23

    ... REAL ICE™ In-Circuit Debugger User's Guide” DS51616 ® • “Using MPLAB REAL ICE™” (poster) DS51749 © 2009 Microchip Technology Inc. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “ ...

  • Page 24

    ... Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect 10k resistor to V unused pins and drive the output to logic low. 2.10 Typical Application Connection Examples Examples of typical application connections are shown in Figure 2-4 through Figure 2-11. Preliminary © 2009 Microchip Technology Inc ...

  • Page 25

    ... FIGURE 2-4: DIGITAL PFC ADC Channel FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION k 1 ADC Channel © 2009 Microchip Technology Inc. I PFC | FET k 2 Driver ADC Channel PWM Output dsPIC33FJ06GS101 I PFC V INPUT FET k 2 Driver ADC PWM Channel Output dsPIC33FJ06GS101 ...

  • Page 26

    ... Input FET k 7 Driver ADC Channel dsPIC33FJ06GS502 DS70318D-page 24 5V Output I 5V FET k Driver 1 Analog ADC Comp. Channel dsPIC33FJ06GS202 FET Driver PWM FET Driver PWM Analog Comparator Analog Comparator Analog Comparator ADC Channel Preliminary k 2 3.3V Output © 2009 Microchip Technology Inc. ...

  • Page 27

    ... OFF-LINE UPS Push-Pull Converter V BAT GND FET FET k Driver Driver 2 PWM PWM ADC or Analog Comp ADC ADC k 6 Battery Charger © 2009 Microchip Technology Inc GND FET FET FET FET k Driver Driver Driver Driver 1 ADC PWM PWM PWM PWM ADC dsPIC33FJ16GS504 ADC ...

  • Page 28

    ... FIGURE 2-9: INTERLEAVED PFC | ADC Channel ADC Channel DS70318D-page FET FET Driver Driver ADC ADC ADC PWM PWM Channel Channel Channel dsPIC33FJ06GS202 Preliminary V + OUT OUT © 2009 Microchip Technology Inc. ...

  • Page 29

    ... FIGURE 2-10: PHASE-SHIFTED FULL-BRIDGE CONVERTER Gate 3 Gate 1 S1 Gate Gate 1 FET Driver S1 Gate 2 © 2009 Microchip Technology Inc. S3 Gate 4 Gate 5 Analog Ground Gate 3 FET Driver S3 Gate 4 Preliminary Gate OUT V - OUT Gate 5 FET k 2 Driver k 1 PWM ADC PWM ...

  • Page 30

    ... DS70318D-page 28 PWM PWM PWM PWM PWM PWM PWM PWM PWM PWM Preliminary © 2009 Microchip Technology Inc. ...

  • Page 31

    ... X04 is shown in Figure 3-2. © 2009 Microchip Technology Inc. 3.1 Data Addressing Overview The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred and and Y data memory. Each memory block has its own ...

  • Page 32

    ... Data Latch Data Latch PCH PCL X RAM Y RAM Address Address Loop Control Latch Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support Preliminary 16-Bit ALU 16 To Peripheral Modules © 2009 Microchip Technology Inc. ...

  • Page 33

    ... Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG OAB SAB DA SRH © 2009 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 PC0 0 Program Space Visibility Page Address ...

  • Page 34

    ... The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). 4: Clearing this bit will clear SA and SB. DS70318D-page 32 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) (1,4) Preliminary R/C R/W-0 (1,4) SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2009 Microchip Technology Inc. ...

  • Page 35

    ... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). 4: Clearing this bit will clear SA and SB. © 2009 Microchip Technology Inc. (2) Preliminary DS70318D-page 33 ...

  • Page 36

    ... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. DS70318D-page 34 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) Preliminary R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2009 Microchip Technology Inc. ...

  • Page 37

    ... Microchip Technology Inc. 3.5.2 DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: • ...

  • Page 38

    ... DS70318D-page 36 Algebraic Operation – y – y change – – 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-Bit Multiplier/Scaler 16 16 To/From W Array Preliminary ACC Write Back Yes No No Yes No Yes Yes Round u Logic Zero Backfill © 2009 Microchip Technology Inc. ...

  • Page 39

    ... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. © 2009 Microchip Technology Inc. 3.6.2.1 The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input. • ...

  • Page 40

    ... MAC class of instructions, the accumulator write- back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. Preliminary subject to data saturation (see © 2009 Microchip Technology Inc. ...

  • Page 41

    ... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2009 Microchip Technology Inc. 3.6.4 BARREL SHIFTER The barrel shifter can perform up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...

  • Page 42

    ... NOTES: DS70318D-page 40 Preliminary © 2009 Microchip Technology Inc. ...

  • Page 43

    ... Flash Memory (1792 instructions) Unimplemented (Read ‘0’s) Reserved Device Configuration Registers Reserved DEVID (2) Reserved © 2009 Microchip Technology Inc. 4.1 Program Address Space The program dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ and X04 devices is 4M instructions. The space is families of addressable by a 24-bit value derived either from the ...

  • Page 44

    ... These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector Table”. least significant word Instruction Width Preliminary PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2009 Microchip Technology Inc. ...

  • Page 45

    ... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2009 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so and care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...

  • Page 46

    ... Optionally Mapped into Program Memory 0xFFFF DS70318D-page 44 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x087E 0x0880 Y Data RAM (Y) 0x08FE 0x0900 0x1FFE 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8-Kbyte Near Data Space © 2009 Microchip Technology Inc. ...

  • Page 47

    ... SRAM Space 0x0BFF 0x0C01 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2009 Microchip Technology Inc. LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x09FE 0x0A00 Y Data RAM (Y) 0x0BFE 0x0C00 ...

  • Page 48

    ... Optionally Mapped into Program Memory 0xFFFF DS70318D-page 46 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0BFE 0x0C00 Y Data RAM (Y) 0x0FFE 0x1000 0x1FFE 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8-Kbyte Near Data Space © 2009 Microchip Technology Inc. ...

  • Page 49

    ... X and Y address space also the X data prefetch path for the dual operand DSP instructions (MAC class). © 2009 Microchip Technology Inc. The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths ...

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    ... DS70318D-page 48 Preliminary © 2009 Microchip Technology Inc. ...

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    ... PC<22:16> 000000000 <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2009 Microchip Technology Inc. 4.3 Instruction Addressing Modes The addressing modes shown in Table 4-48 form the and basis of the addressing modes optimized to support the specific features of individual instructions. The ...

  • Page 74

    ... ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. Preliminary MAC INSTRUCTIONS Register Indirect with Register Offset Addressing mode is available only for W9 (in X space) and W11 (in Y space). OTHER INSTRUCTIONS © 2009 Microchip Technology Inc. ...

  • Page 75

    ... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2009 Microchip Technology Inc. Y Note: calculations assume word-sized data (LSb of every EA is always clear). The length of a circular buffer is not directly specified determined by the difference corresponding start and end addresses ...

  • Page 76

    ... If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV<15>) bit, a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the Bit-Reversed Pointer. Preliminary © 2009 Microchip Technology Inc. N bytes, should not be ...

  • Page 77

    ... TABLE 4-49: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address © 2009 Microchip Technology Inc. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address Decimal Preliminary A0 Decimal ...

  • Page 78

    ... TBLPAG<7:0> 0xxx xxxx xxxx xxxx xxxx xxxx TBLPAG<7:0> 1xxx xxxx PSVPAG<7:0> xxxx xxxx Preliminary <15> <14:1> <0> 0 Data EA<15:0> Data EA<15:0> xxxx xxxx xxxx xxxx (1) Data EA<14:0> xxx xxxx xxxx xxxx © 2009 Microchip Technology Inc. ...

  • Page 79

    ... Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2009 Microchip Technology Inc. Program Counter 0 23 bits ...

  • Page 80

    ... TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 0x800000 Only read operations are shown; write operations are also valid in the user memory area. Preliminary © 2009 Microchip Technology Inc. ...

  • Page 81

    ... PSVPAG is mapped into the upper half of the data memory space... © 2009 Microchip Technology Inc. 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...

  • Page 82

    ... NOTES: DS70318D-page 80 Preliminary © 2009 Microchip Technology Inc. ...

  • Page 83

    ... Program Counter Using 1/0 Table Instruction User/Configuration Space Select © 2009 Microchip Technology Inc. signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. and RTSP is accomplished using TBLRD (table read) and ...

  • Page 84

    ... NVMKEY register. Refer to Section 5.3 “Programming Operations” for further details. Preliminary processor stalls (waits) until the PROGRAMMING TIME × FRC Accuracy FRC Tuning 11064 Cycles = × × 0.05 1 0.00375 – 11064 Cycles = × × 0.05 – 1 0.00375 – © 2009 Microchip Technology Inc. ...

  • Page 85

    ... No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be Reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2009 Microchip Technology Inc. (1) U-0 U-0 — — (1) ...

  • Page 86

    ... NVMKEY<7:0>: Key Register bits (write-only) DS70318D-page 84 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 87

    ... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2009 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...

  • Page 88

    ... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted Preliminary © 2009 Microchip Technology Inc. ...

  • Page 89

    ... DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2009 Microchip Technology Inc. Any active source of reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to and a known Reset state and some are unaffected. ...

  • Page 90

    ... SWDTEN bit setting. DS70318D-page 88 (1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 91

    ... Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2009 Microchip Technology Inc. (1) (CONTINUED) Preliminary ...

  • Page 92

    ... Total Delay OSCD (1) — LOCK OSCD LOCK (1,2) — OSCD OST (1,2) — OSCD OST — — ( LOCK OSCD OST (1,2,3) T LOCK LOCK ( OSCD OST LOCK (1,2,3) T LOCK (3) LOCK ( OSCD (1) — 102.4 μs for a OST © 2009 Microchip Technology Inc. , the , (1, ...

  • Page 93

    ... GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine the Fail-Safe Clock Monitor (FSCM) is enabled, it begins to monitor the system clock when the system clock is ready and the delay, T FSCM © 2009 Microchip Technology Inc. V BOR T BOR ...

  • Page 94

    ... DD ) for proper device operation. The BOR crosses the DD , has elapsed. The BOR , ensures the voltage regulator output ) is programmed by PWRT Reset Timer Value Select bits in the POR Configuration + initiated each time V BOR PWRT trip point BOR © 2009 Microchip Technology Inc. DD ...

  • Page 95

    ... Software RESET Instruction (SWR) Whenever the RESET instruction is executed, the device will assert SYSRST, placing the device in a special Reset state. This Reset state will not re-initialize the clock. The clock source in effect prior to © 2009 Microchip Technology Inc BOR PWRT ...

  • Page 96

    ... RCON register value after a device Reset will be meaningful. Table 6-3 provides a summary of the Reset flag bit operation. Set by: POR,BOR POR,BOR POR,BOR POR POR,BOR PWRSAV instruction, CLRWDT instruction, POR,BOR POR,BOR POR,BOR Preliminary Cleared by: © 2009 Microchip Technology Inc. ...

  • Page 97

    ... The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices implement unique interrupts and 4 non-maskable traps. These are summarized in Table 7-1. © 2009 Microchip Technology Inc. 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located and after the IVT, as shown in Figure 7-1 ...

  • Page 98

    ... Note 1: See Table 7-1 for the list of implemented interrupt vectors. DS70318D-page 96 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1) © 2009 Microchip Technology Inc. ...

  • Page 99

    ... Microchip Technology Inc. AIVT Address Highest Natural Order Priority 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Capture 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C ...

  • Page 100

    ... ADC Pair 1 Convert Done 0x0001F4 ADC Pair 2 Convert Done 0x0001F6 ADC Pair 3 Convert Done 0x0001F8 ADC Pair 4 Convert Done 0x0001FA ADC Pair 5 Convert Done 0x0001FC ADC Pair 6 Convert Done 0x0001FE Reserved Lowest Natural Order Priority Preliminary Interrupt Source © 2009 Microchip Technology Inc. ...

  • Page 101

    ... IPCx The IPCx registers are used to set the Interrupt Priority Level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. © 2009 Microchip Technology Inc. 7.3.5 INTTREG The INTTREG register contains the associated interrupt vector number and the new CPU Interrupt priority Level, which are latched into the Vector Number (VECNUM< ...

  • Page 102

    ... R/W-0 R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set © 2009 Microchip Technology Inc. ...

  • Page 103

    ... MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...

  • Page 104

    ... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70318D-page 102 Preliminary © 2009 Microchip Technology Inc. ...

  • Page 105

    ... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 ...

  • Page 106

    ... R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1,2) (1,2) (1,2) Preliminary R/W-0 R/W-0 (1,2) SPI1EIF T3IF bit 8 R/W-0 R/W-0 (1) IC1IF INT0IF bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 107

    ... Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: This bit is not implemented in dsPIC33FJ06GS101/102 devices. 2: These bits are not implemented in dsPIC33FJ06GS202 devices. © 2009 Microchip Technology Inc. (1) Preliminary DS70318D-page 105 ...

  • Page 108

    ... DS70318D-page 106 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) INT1IF CNIF AC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 109

    ... Unimplemented: Read as ‘0’ bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...

  • Page 110

    ... DS70318D-page 108 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown ...

  • Page 111

    ... Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: These bits are unimplemented in dsPIC33FJ06GS202 devices. 2: These bits are unimplemented in dsPIC33FJ06GS101 and dsPIC33FJ16GS502 devices. 3: These bits are unimplemented in dsPIC33FJ16GS402/404/502 devices. 4: These bits are unimplemented in dsPIC33FJ06101/102/202 devices. © 2009 Microchip Technology Inc. ...

  • Page 112

    ... U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) ADCP6IF ADCP5IF ADCP4IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (2) (3) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 (1) (2) (3) ADCP3IF ADCP2IF bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 113

    ... Unimplemented: Read as ‘0’ bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note 1: These bits are unimplemented in dsPIC33FJ06GS101/102 devices. 2: These bits are unimplemented in dsPIC33FJ06GS202 devices. © 2009 Microchip Technology Inc. R/W-0 R/W-0 U1TXIE U1RXIE U-0 R/W-0 (1,2) — ...

  • Page 114

    ... Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note 1: These bits are unimplemented in dsPIC33FJ06GS101/102 devices. 2: These bits are unimplemented in dsPIC33FJ06GS202 devices. DS70318D-page 112 (1) Preliminary © 2009 Microchip Technology Inc. ...

  • Page 115

    ... Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note 1: This bit is not implemented in dsPIC33FJ06GS101/102 and dsPIC33FJ16GS402/404 devices. © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — ...

  • Page 116

    ... U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/W-0 U-0 PSEMIE — bit 8 U-0 U-0 — — bit Bit is unknown U-0 U-0 — ...

  • Page 117

    ... Interrupt request is not enabled bit 14 PWM1IE: PWM1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13-0 Unimplemented: Read as ‘0’ Note 1: This bit is unimplemented in dsPIC33FJ06GS101/102 devices. © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 ...

  • Page 118

    ... PWM3IE: PWM3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: These bits are unimplemented in dsPIC33FJ06GS202 devices. 2: These bits are unimplemented in dsPIC33FJ06GS101 and dsPIC33FJ16GS502 devices. 3: These bits are unimplemented in dsPIC33FJ16GS402/404/502 devices. 4: These bits are unimplemented in dsPIC33FJ06101/102/202 devices. DS70318D-page 116 ...

  • Page 119

    ... ADCP2IE: ADC Pair 2 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: These bits are not implemented in dsPIC33FJ06GS101/102/202 and dsPIC33FJ16GS402/402/502 devices. 2: This bit is not implemented in dsPIC33FJ06GS102/202 devices. 3: This bit is not implemented in dsPIC33FJ06GS101 devices. © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — ...

  • Page 120

    ... Note 1: These bits are unimplemented in dsPIC33FJ06GS101/102 devices. DS70318D-page 118 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 (1) — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 121

    ... Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: These bits are not implemented in dsPIC33FJ06GS101/202 devices. 2: These bits are not implemented in dsPIC33FJ06GS102 devices. © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 (1,2) — ...

  • Page 122

    ... Note 1: These bits are not implemented in dsPIC33FJ06GS101/102/202 devices. DS70318D-page 120 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 (1) T3IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 123

    ... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — ...

  • Page 124

    ... Note 1: These bits are not implemented in dsPIC33FJ06GS101/102 and dsPIC33FJ16GS402/404 devices. DS70318D-page 122 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 (1) AC1IP<2:0> bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 125

    ... INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...

  • Page 126

    ... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 127

    ... Interrupt is priority 7 (highest priority) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ Note 1: These bits are not implemented in dsPIC33FJ06GS101/102 devices. © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 (1) — U-0 U-0 — ...

  • Page 128

    ... These bits are not implemented in dsPIC33FJ06101/102/202 devices. DS70318D-page 126 U-0 U-0 — — R/W-0 U-0 R/W-1 (1) — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 (2) PWM3IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 129

    ... Interrupt is priority 7 (highest priority) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11-01 Unimplemented: Read as ‘0’ Note 1: These bits are not implemented in dsPIC33FJ06GS101/102 and dsPIC33FJ16GS402/404 devices. © 2009 Microchip Technology Inc. R/W-0 U-0 U-0 (1) — U-0 U-0 U-0 — ...

  • Page 130

    ... These bits are not implemented in dsPIC33FJ06GS101/102 devices. DS70318D-page 128 U-0 U-0 U-0 — — R/W-0 U-0 R/W-1 (1) — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1,2) Preliminary U-0 U-0 — — — bit 8 R/W-0 R/W-0 (1,2) AC3IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 131

    ... ADCP0IP<2:0>: ADC Pair 0 Conversion Done Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 U-0 — ...

  • Page 132

    ... These bits are implemented in dsPIC33FJ16GS504 devices only. DS70318D-page 130 R/W-0 U-0 R/W-1 (4) — R/W-0 U-0 R/W-1 (2,3) — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 (4) ADCP4IP<2:0> bit 8 R/W-0 R/W-0 (1) ADCP2IP<2:0> bit Bit is unknown (4) (4) (2,3) (1) © 2009 Microchip Technology Inc. ...

  • Page 133

    ... ADCP6IP<2:0>: ADC Pair 6 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Note 1: These bits are not implemented in dsPIC33FJ06GS202 devices. © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 ...

  • Page 134

    ... Interrupt vector pending is number 9 0000000 = Interrupt vector pending is number 8 DS70318D-page 132 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...

  • Page 135

    ... ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2009 Microchip Technology Inc. 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...

  • Page 136

    ... NOTES: DS70318D-page 134 Preliminary © 2009 Microchip Technology Inc. ...

  • Page 137

    ... See Section 8.1.3 “PLL Configuration” and Section 8.2 “Auxiliary Clock Generation” for F Note 1: If the Oscillator is used with modes, an external parallel resistor with the value of 1 MΩ must be connected. 2: © 2009 Microchip Technology Inc. • An on-chip Phase-Locked Loop (PLL) to scale the internal operating frequency to the required system clock frequency • ...

  • Page 138

    ... Oscillator Source POSCMD<1:0> FNOSC<2:0> Internal xx Internal xx Internal xx Reserved xx Primary 10 Primary 01 Primary 00 Primary 10 Primary 01 Primary 00 Internal xx Internal xx Preliminary © 2009 Microchip Technology Inc. device operation. PLL Configuration bits divided by 2 OSC ) and the defines the OSC Note 1, 2 111 1 110 1 101 — 100 — ...

  • Page 139

    ... The primary oscillator and internal FRC oscillator sources can be used with an auxiliary PLL to obtain the auxiliary clock. The auxiliary PLL has a fixed 16x multiplication factor. © 2009 Microchip Technology Inc. For a primary oscillator or FRC oscillator, output ‘F the PLL output ‘F EQUATION 8-2: ...

  • Page 140

    ... PLL modes. DS70318D-page 138 (1) R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary © 2009 Microchip Technology Inc. R/W-y R/W-y (2) NOSC<2:0> bit 8 U-0 R/W-0 — OSWEN bit Bit is unknown ...

  • Page 141

    ... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2009 Microchip Technology Inc. (1) (CONTINUED) ...

  • Page 142

    ... Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. DS70318D-page 140 R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 143

    ... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ...

  • Page 144

    ... FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested DS70318D-page 142 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) TUN<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 145

    ... No clock input is selected bit 6 FRCSEL: Select Reference Clock Source for Auxiliary PLL bit 1 = Select FRC clock for auxiliary PLL 0 = Input clock source is determined by ASRCSEL bit setting bit 5-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. U-0 U-0 — — U-0 U-0 — ...

  • Page 146

    ... This pin is remappable. Refer to Section 10.4 “Peripheral Pin Select” for more information. DS70318D-page 144 R/W-0 R/W-0 R/W-0 ROSEL RODIV<3:0> U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) pin (1) Preliminary R/W-0 R/W-0 (1) bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 147

    ... NOSC control bits. If they are the same, the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. © 2009 Microchip Technology Inc valid clock switch has been initiated, the LOCK (OSCCON<3>) status bits are cleared. ...

  • Page 148

    ... NOTES: DS70318D-page 146 Preliminary © 2009 Microchip Technology Inc. ...

  • Page 149

    ... EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2009 Microchip Technology Inc. 9.2 Instruction-Based Power-Saving Modes The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ and X04 devices have two special power-saving modes that ...

  • Page 150

    ... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control regis- ters are already configured to enable module operation). Preliminary There are eight possible ® DSC © 2009 Microchip Technology Inc. ...

  • Page 151

    ... SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2-1 Unimplemented: Read as ‘0’ bit 0 ADCMD: ADC Module Disable bit 1 = ADC module is disabled 0 = ADC module is enabled © 2009 Microchip Technology Inc. R/W-0 R/W-0 U-0 T2MD T1MD — U-0 R/W-0 U-0 — ...

  • Page 152

    ... DS70318D-page 150 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 IC2MD IC1MD bit 8 R/W-0 R/W-0 OC2MD OC1MD bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 153

    ... Unimplemented: Read as ‘0’ bit 3 REFOMD: Reference Clock Generator Module Disable bit 1 = Reference clock generator module is disabled 0 = Reference clock generator module is enabled bit 2-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. U-0 U-0 R/W-0 — — CMPMD U-0 ...

  • Page 154

    ... DS70318D-page 152 U-0 R/W-0 R/W-0 — PWM4MD PWM3MD U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 PWM2MD PWM1MD bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 155

    ... Analog Comparator 2 module is disabled 0 = Analog Comparator 2 module is enabled bit 8 CMP1MD: Analog Comparator 1 Module Disable bit 1 = Analog Comparator 1 module is disabled 0 = Analog Comparator 1 module is enabled bit 7-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. U-0 R/W-0 R/W-0 — CMP4MD CMP3MD U-0 ...

  • Page 156

    ... NOTES: DS70318D-page 154 Preliminary © 2009 Microchip Technology Inc. ...

  • Page 157

    ... CK WR PORT Data Latch Read LAT Read PORT © 2009 Microchip Technology Inc. peripheral that shares the same pin. Figure 10-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. and When a peripheral is enabled and the peripheral is ...

  • Page 158

    ... CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Pull-ups on change notification pins Note: should always be disabled when the port pin is configured as a digital output. Preliminary dsPIC33FJ06GS101/X02 and in response to a © 2009 Microchip Technology Inc. ...

  • Page 159

    ... The association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. © 2009 Microchip Technology Inc. 10.4.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it will be mapped to ...

  • Page 160

    ... RPINR30 FLT3 RPINR30 FLT4 RPINR31 FLT5 RPINR31 FLT6 RPINR32 FLT7 RPINR32 FLT8 RPINR33 SYNCI1 RPINR33 SYNCI2 RPINR34 Preliminary © 2009 Microchip Technology Inc. Configuration Bits INT1R<5:0> INT2R<5:0> T1CKR<5:0> T2CKR<5:0> T3CKR<5:0> IC1R<5:0> IC2R<5:0> OCFAR<5:0> U1RXR<5:0> U1CTSR<5:0> SDI1R<5:0> SCK1R<5:0> SS1R<5:0> FLT1R<5:0> FLT2R<5:0> FLT3R<5:0> ...

  • Page 161

    ... RPn tied to Analog Comparator Output 4 101010 PWM4H RPn tied to PWM output pins associated with PWM Generator 4 101100 PWM4L RPn tied to PWM output pins associated with PWM Generator 4 101101 © 2009 Microchip Technology Inc. FIGURE 10-3: MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPn RPORn<5:0> Default U1TX Output Enable ...

  • Page 162

    ... Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the Peripheral Pin Select registers. Preliminary © 2009 Microchip Technology Inc. ...

  • Page 163

    ... Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. Not all output remappable peripheral registers are implemented on all devices. See the register and description of the specific register for further details. R/W-1 R/W-1 R/W-1 INT1R< ...

  • Page 164

    ... Input tied to RP0 DS70318D-page 162 U-0 U-0 — — R/W-1 R/W-1 R/W-1 INT2R<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 165

    ... Input tied to V 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 T3CKR<5:0> R/W-1 R/W-1 R/W-1 T2CKR<5:0> Unimplemented bit, read as ‘0’ ...

  • Page 166

    ... Input tied to RP0 DS70318D-page 164 R/W-1 R/W-1 R/W-1 IC2R<5:0> R/W-1 R/W-1 R/W-1 IC1R<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 167

    ... Input tied to V 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 R/W-1 OCFAR<5:0> Unimplemented bit, read as ‘0’ ...

  • Page 168

    ... Input tied to RP0 DS70318D-page 166 R/W-1 R/W-1 R/W-1 U1CTSR<5:0> R/W-1 R/W-1 R/W-1 U1RXR<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 169

    ... Input tied to V 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 SCK1R<5:0> R/W-1 R/W-1 R/W-1 SDI1R<5:0> Unimplemented bit, read as ‘0’ ...

  • Page 170

    ... Input tied to RP0 DS70318D-page 168 U-0 U-0 — — R/W-1 R/W-1 R/W-1 SS1R<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 171

    ... Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 FLT1R<5:0> U-0 U-0 — — Unimplemented bit, read as ‘0’ ...

  • Page 172

    ... Input tied to RP0 DS70318D-page 170 R/W-1 R/W-1 R/W-1 FLT3R<5:0> R/W-1 R/W-1 R/W-1 FLT2R<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 173

    ... Input tied to V 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 FLT5R<5:0> R/W-1 R/W-1 R/W-1 FLT4R<5:0> Unimplemented bit, read as ‘0’ ...

  • Page 174

    ... Input tied to RP0 DS70318D-page 172 R/W-1 R/W-1 R/W-1 FLT7R<5:0> R/W-1 R/W-1 R/W-1 FLT6R<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 175

    ... Input tied to V 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 SYNCI1R<5:0> R/W-1 R/W-1 R/W-1 FLT8R<5:0> Unimplemented bit, read as ‘0’ ...

  • Page 176

    ... R/W-0 RP1R<5:0> R/W-0 R/W-0 R/W-0 RP0R<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 177

    ... Table 10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP4R<5:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table 10-2 for peripheral function numbers) © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP3R<5:0> R/W-0 ...

  • Page 178

    ... R/W-0 R/W-0 R/W-0 RP9R<5:0> R/W-0 R/W-0 R/W-0 RP8R<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared dsPIC33FJ06GS101 device. Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 179

    ... Unimplemented: Read as ‘0’ bit 5-0 RP12R<5:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits (see Table 10-2 for peripheral function numbers) This register is not implemented in the Note 1: © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP11R<5:0> R/W-0 R/W-0 R/W-0 RP10R< ...

  • Page 180

    ... R/W-0 R/W-0 R/W-0 RP17R<5:0> R/W-0 R/W-0 R/W-0 RP16R<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 181

    ... Unimplemented: Read as ‘0’ bit 5-0 RP20R<5:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: This register is implemented in dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only. © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP19R<5:0> R/W-0 ...

  • Page 182

    ... Bit is cleared R/W-0 R/W-0 R/W-0 RP25R<5:0> R/W-0 R/W-0 R/W-0 RP24R<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 183

    ... Unimplemented: Read as ‘0’ bit 5-0 RP28R<5:0>: Peripheral Output Function is Assigned to RP28 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: This register is implemented in dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only. © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP27R<5:0> R/W-0 ...

  • Page 184

    ... Bit is cleared R/W-0 R/W-0 R/W-0 RP35R<5:0> R/W-0 R/W-0 R/W-0 RP34R<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 185

    ... FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM F CY TCKPS<1:0> T1CK Prescaler (/n) TCKPS<1:0> © 2009 Microchip Technology Inc. The Timer1 module can operate in one of the following modes: • Timer mode and • Gated Timer mode families of • Synchronous Counter mode • Asynchronous Counter mode source ...

  • Page 186

    ... DS70318D-page 184 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 187

    ... Prescaler F CY TCKPS<1:0> Prescaler Sync TxCK TCKPS<1:0> © 2009 Microchip Technology Inc. • External clock input (TxCK) is always synchronized to the internal device clock and the clock synchronization is performed after the prescaler. and Figure 12-1 shows a block diagram of the Type B timer. families of ...

  • Page 188

    ... Set the corresponding TON bit. The timer value at any point is stored in the register pair, TMR3:TMR2, which always contains the most significant word of the count, while TMR2 contains the least significant word. Preliminary 32-BIT TIMER Type C Timer (msw) Timer3 © 2009 Microchip Technology Inc. ...

  • Page 189

    ... TIMER BLOCK DIAGRAM Gate Sync Prescaler F CY (/n) TCKPS<1:0> Prescaler Sync (/n) TxCK TCKPS<1:0> Note 1: Timerx is a Type B Timer (x = 2). 2: Timery is a Type C Timer (y = 3). © 2009 Microchip Technology Inc. Falling Edge Detect PRy PRx Comparator 10 lsw (1) TMRx TMRy 00 x1 TMRyHLD TGATE ...

  • Page 190

    ... DS70318D-page 188 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 191

    ... Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, these bits have no effect. © 2009 Microchip Technology Inc. U-0 U-0 (1) — ...

  • Page 192

    ... NOTES: DS70318D-page 190 Preliminary © 2009 Microchip Technology Inc. ...

  • Page 193

    ... ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note 1: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2009 Microchip Technology Inc. • Simple Capture Event modes: - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of ...

  • Page 194

    ... Input capture module turned off DS70318D-page 192 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 195

    ... TMR3 TMR2 Note: An ‘x’ signal, register or bit name denotes the number of the output compare channels. © 2009 Microchip Technology Inc. The state of the output pin changes when the timer value matches the Compare register value. The output compare module generates either a single output ...

  • Page 196

    ... OCx rising and falling edge OCx falling edge 0 OCx falling edge 0 ‘0’, if OCxR is zero No interrupt ‘1’, if OCxR is non-zero ‘0’, if OCxR is zero OCFA falling edge for OC1 to OC4 ‘1’, if OCxR is non-zero Timer is Reset on Period Match Preliminary — © 2009 Microchip Technology Inc. ...

  • Page 197

    ... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2009 Microchip Technology Inc. U-0 U-0 U-0 — ...

  • Page 198

    ... NOTES: DS70318D-page 196 Preliminary © 2009 Microchip Technology Inc. ...

  • Page 199

    ... PWM outputs • Output override control • Special Event Trigger • PWM capture feature • Prescaler for input clock © 2009 Microchip Technology Inc. • Dual trigger from PWM to ADC • PWMxH, PWMxL output pin swapping • PWM4H, PWM4L pins remappable and • ...

  • Page 200

    ... Dead-Time Generator Channel 4 Dead-Time Generator External Time Base Synchronization Special Event Special Event Trigger Postscaler Fault Mode and Pin Control Preliminary PWM1H PWM1L PWM2H PWM2L PWM3H PWM3L PWM4H (1) (1) PWM4L Fault Control X (1) FLT Logic (1) SYNCO (1) SYNCI X © 2009 Microchip Technology Inc. ...