DSPIC33FJ16GS502-I/SO Microchip Technology, DSPIC33FJ16GS502-I/SO Datasheet - Page 139

IC DSPIC MCU/DSP 16K 28-SOIC

DSPIC33FJ16GS502-I/SO

Manufacturer Part Number
DSPIC33FJ16GS502-I/SO
Description
IC DSPIC MCU/DSP 16K 28-SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS502-I/SO

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Core Frequency
40MHz
Core Supply Voltage
3.3V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
16KB
Supply Voltage Range
3V To 3.6V
Package
28SOIC W
Device Core
dsPIC
Family Name
dsPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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8.1.3
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in Figure 8-2.
The output of the primary oscillator or FRC, denoted as
‘F
... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected in the range of 0.8 MHz to 8 MHz. The
prescale
PLLPRE<4:0> bits (CLKDIV<4:0>).
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor, ‘M’,
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
The VCO output is further divided by a postscale factor,
‘N2’. This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4, or 8, and
must be selected such that the PLL output frequency
(F
generates device operating speeds of 6.25-40 MIPS.
FIGURE 8-2:
8.2
The auxiliary clock generation is used for a peripherals
that need to operate at a frequency unrelated to the
system clock such as a PWM or ADC.
The primary oscillator and internal FRC oscillator
sources can be used with an auxiliary PLL to obtain the
auxiliary clock. The auxiliary PLL has a fixed 16x
multiplication factor.
© 2009 Microchip Technology Inc.
IN
OSC
Note:
Source (Crystal, External
Clock or Internal RC)
’, is divided down by a prescale factor (N1) of 2, 3,
) is in the range of 12.5 MHz to 80 MHz, which
Auxiliary Clock Generation
Note 1: This frequency range must be satisfied at all times.
factor
PLL CONFIGURATION
To achieve 1.04 ns PWM resolution, the
auxiliary clock must be set up for 120 MHz.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
‘N1’
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PLL BLOCK DIAGRAM
is
selected
Divide by
PLLPRE
2-33
N1
using
0.8-8.0 MHz
Here
(1)
Preliminary
the
X
For a primary oscillator or FRC oscillator, output ‘F
the PLL output ‘F
EQUATION 8-2:
For example, suppose a 10 MHz crystal is being used
with the selected oscillator mode of XT with PLL (see
Equation 8-3).
• If PLLPRE<4:0> = 0, then N1 = 2. This yields a
• If PLLDIV<8:0> = 0x1E, then M = 32. This yields a
• If PLLPOST<1:0> = 0, then N2 = 2. This provides
EQUATION 8-3:
8.3
The reference clock output logic provides the user with
the ability to output a clock signal based on the system
clock or the crystal oscillator on a device pin. The user
application can specify a wide range of clock scaling
prior to outputting the reference clock.
Divide by
PLLDIV
VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
VCO output of 5 x 32 = 160 MHz, which is within
the 100-200 MHz ranged needed.
a Fosc of 160/2 = 80 MHz. The resultant device
operating speed is 80/2 = 40 MIPS.
Note:
2-513
VCO
F
M
CY
=
100-200 MHz
Reference Clock Generation
F
OSC
If the primary PLL is used as a source for
the auxiliary clock, then the primary PLL
should be configured up to a maximum
operation of 30 MIPS or less.
Here
2
F
VCO
F
=
(1)
OSC
OSC
1
2
PLLPOST
’ is given by Equation 8-2.
= F
(
Divide by
F
XT WITH PLL MODE
EXAMPLE
10000000 * 32
2, 4, 8
OSC
IN
N2
*
2 * 2
(
CALCULATION
N1*N2
12.5-80 MHz
M
DS70318D-page 137
Here
)
)
=
(1)
40 MIPS
F
OSC
IN
’,

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