DSPIC33FJ16GS502-I/SO Microchip Technology, DSPIC33FJ16GS502-I/SO Datasheet - Page 202

• Manufacturer Part Number: DSPIC33FJ16GS502-I/SO
• Description: IC DSPIC MCU/DSP 16K 28-SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS502-I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 16KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 15-1:
DS70318D-page 200
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5-4
bit 3-0
SYNCEN
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
R/W-0
R/W-0
PTEN
(1)
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
PTEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
Unimplemented: Read as ‘0’
PTSIDL: PWM Time Base Stop in Idle Mode bit
1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
SESTAT: Special Event Interrupt Status bit
1 = Special event interrupt is pending
0 = Special event interrupt is not pending
SEIEN: Special Event Interrupt Enable bit
1 = Special event interrupt is enabled
0 = Special event interrupt is disabled
EIPU: Enable Immediate Period Updates bit
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWM cycle boundaries
SYNCPOL: Synchronization Input/Output Polarity bit
1 = SYNCIx and SYNCO polarity is inverted (active-low)
0 = SYNCIx and SYNCO are active-high
SYNCOEN: Primary Time Base Sync Enable bit
1 = SYNCO output is enabled
0 = SYNCO output is disabled
SYNCEN: External Time Base Synchronization Enable bit
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
Unimplemented: Read as ‘0’
SYNCSRC<1:0>: Synchronous Source Selection bits
00 = SYNCI1
01 = SYNCI2
10 = Reserved
11 = Reserved
SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits
0000 = 1:1 Postscaler generates a Special Event Trigger on every compare match event
0001 = 1:2 Postscaler generates a Special Event Trigger on every second compare match event
•
•
•
1111 = 1:16 Postscaler generates a Special Event Trigger trigger on every sixteenth compare match event
U-0
U-0
—
—
PTCON: PWM TIME BASE CONTROL REGISTER
HC = Hardware Clearable bit
W = Writable bit
‘1’ = Bit is set
PTSIDL
R/W-0
R/W-0
SYNCSRC<1:0>
HS/HC-0
SESTAT
Preliminary
R/W-0
(1)
(1)
U = Unimplemented bit, read as ‘0’
HS = Hardware Settable bit
‘0’ = Bit is cleared
(1)
SEIEN
R/W-0
R/W-0
(1)
(1)
(1)
EIPU
R/W-0
R/W-0
SEVTPS<3:0>
(1)
© 2009 Microchip Technology Inc.
SYNCPOL
x = Bit is unknown
(1)
R/W-0
R/W-0
(1)
(1)
SYNCOEN
R/W-0
R/W-0
bit 8
bit 0
(1)