DSPIC33FJ16GS502-I/SO Microchip Technology, DSPIC33FJ16GS502-I/SO Datasheet - Page 84

IC DSPIC MCU/DSP 16K 28-SOIC

DSPIC33FJ16GS502-I/SO

Manufacturer Part Number
DSPIC33FJ16GS502-I/SO
Description
IC DSPIC MCU/DSP 16K 28-SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS502-I/SO

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Core Frequency
40MHz
Core Supply Voltage
3.3V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
16KB
Supply Voltage Range
3V To 3.6V
Package
28SOIC W
Device Core
dsPIC
Family Name
dsPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ16GS502-I/SO
Manufacturer:
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DSPIC33FJ16GS502-I/SO
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
5.2
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 Flash program memory array is organized into rows
of 64 instructions or 192 bytes. RTSP allows the user
application to erase a page of memory, which consists of
eight rows (512 instructions) at a time, and to program
one row or one word at a time. Table 24-12 shows typical
erase and programming times. The 8-row erase pages
and single row write rows are edge-aligned from the
beginning of program memory, on boundaries of
1536 bytes and 192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written.
programming each row.
DS70318D-page 82
RTSP Operation
A
programming
cycle
is
required
Preliminary
for
5.3
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode.
programming operation is finished.
The programming time depends on the FRC accuracy
(see Table 24-20) and the value of the FRC Oscillator
Tuning register (see Register 8-4). Use the following
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time, and Word
Write Cycle Time parameters (see Table 24-12).
EQUATION 5-1:
For example, if the device is operating at +125°C,
the FRC accuracy will be ±5%. If the TUN<5:0> bits
(see Register 8-4) are set to ‘b111111, the
Minimum Row Write Time is:
and, the Maximum Row Write Time is:
Setting the WR bit (NVMCON<15>) starts the opera-
tion, and the WR bit is automatically cleared when the
operation is finished.
5.4
Two SFRs are used to read and write the program
Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user application must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 5.3
“Programming Operations” for further details.
T
T
RW
RW
------------------------------------------------------------------------------------------------------------------------- -
7.37 MHz
=
=
--------------------------------------------------------------------------------------------- - 1.586ms
7.37 MHz
---------------------------------------------------------------------------------------------- 1.435ms
7.37 MHz
The
Programming Operations
Control Registers
×
processor
(
FRC Accuracy
×
×
(
(
11064 Cycles
11064 Cycles
1 0.05
1
+
PROGRAMMING TIME
© 2009 Microchip Technology Inc.
0.05
T
stalls
)
)
×
×
)%
(
(
1 0.00375
1 0.00375
×
(
(waits)
FRC Tuning
)
)
=
=
until
)%
the

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