DSPIC33FJ16GS502-I/SO Microchip Technology, DSPIC33FJ16GS502-I/SO Datasheet - Page 96

IC DSPIC MCU/DSP 16K 28-SOIC

DSPIC33FJ16GS502-I/SO

Manufacturer Part Number
DSPIC33FJ16GS502-I/SO
Description
IC DSPIC MCU/DSP 16K 28-SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS502-I/SO

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Core Frequency
40MHz
Core Supply Voltage
3.3V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
16KB
Supply Voltage Range
3V To 3.6V
Package
28SOIC W
Device Core
dsPIC
Family Name
dsPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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DSPIC33FJ16GS502-I/SO
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
6.7
To maintain the integrity of the Peripheral Pin Select
Control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occur (such as cell
disturbances caused by ESD or other external events),
a Configuration Mismatch Reset occurs.
The Configuration Mismatch (CM) flag in the Reset
Control (RCON<9>) register is set to indicate the
Configuration Mismatch Reset. Refer to Section 10.0
“I/O
Configuration Mismatch Reset.
6.8
An illegal condition device Reset occurs due to the
following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
The Illegal Opcode or Uninitialized W Access Reset
(IOPUWR) flag in the Reset Control (RCON<14>)
register is set to indicate the illegal condition device
Reset.
6.8.1
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
The Illegal Opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the Illegal Opcode Reset, use only the lower 16 bits of
TABLE 6-3:
DS70318D-page 94
TRAPR (RCON<15>)
IOPWR (RCON<14>)
CM (RCON<9>)
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
Note:
Note:
Ports”
Flag Bit
Configuration Mismatch Reset
Illegal Condition Device Reset
All Reset flag bits can be set or cleared by user software.
The
feature and associated Reset flag are not
available on all devices.
ILLEGAL OPCODE RESET
for
RESET FLAG BIT OPERATION
Configuration
more
Trap conflict event
Illegal opcode or uninitialized W register
access or Security Reset
Configuration Mismatch
MCLR Reset
RESET instruction
WDT time-out
PWRSAV #SLEEP instruction
PWRSAV #IDLE instruction
POR, BOR
POR
information
Mismatch
Set by:
on
Reset
Preliminary
the
each program memory section to store the data values.
The upper 8 bits should be programmed with 3Fh,
which is an illegal opcode value.
6.8.2
Any attempt to use the uninitialized W register as an
Address Pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
Resets and is considered uninitialized until written to.
6.8.3
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (boot and secure segment), that
operation will cause a Security Reset.
The PFC occurs when the program counter is reloaded
as a result of a call, jump, computed jump, return,
return from subroutine or other form of branch
instruction.
The VFC occurs when the program counter is reloaded
with an interrupt or trap vector.
Refer to Section 21.8 “Code Protection and
CodeGuard™ Security” for more information on
Security Reset.
6.9
The user application can read the Reset Control
(RCON) register after any device Reset to determine
the cause of the Reset.
Table 6-3 provides a summary of the Reset flag bit
operation.
Note:
Using the RCON Status Bits
POR,BOR
POR,BOR
POR,BOR
POR
POR,BOR
PWRSAV instruction, CLRWDT instruction,
POR,BOR
POR,BOR
POR,BOR
UNINITIALIZED W REGISTER
RESET
SECURITY RESET
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
© 2009 Microchip Technology Inc.
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