ATMEGA32A-PU Atmel, ATMEGA32A-PU Datasheet
ATMEGA32A-PU
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ATMEGA32A-PU Summary of contents
Page 1
... Speed Grades – 16MHz • Power Consumption at 1MHz, 3V, 25°C – Active: 0.6mA – Idle Mode: 0.2mA – Power-down Mode: < 1µA ® ® AVR 8-bit Microcontroller (1) 8-bit Microcontroller with 32KBytes In-System Programmable Flash ATmega32A 8155C–AVR–02/11 ...
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... Pin Configurations Figure 1-1. 8155C–AVR–02/11 Pinout ATmega32A (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP1) PD6 ...
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... Overview The Atmel enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega32A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. 8155C–AVR–02/11 ® ® ...
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... Atmel ATmega32A is a powerful microcontroller that provides a highly-flexible and cost- effective solution to many embedded control applications. The Atmel AVR ATmega32A is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula- tors, and evaluation kits. ...
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... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega32A as listed on 59. 2.2.5 Port C (PC7:PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...
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... Be aware that not all C Compiler vendors include bit definitions in the header files and interrupt handling compiler dependent. Please confirm with the C Compiler documen- tation for more details. 8155C–AVR–02/11 , even if the ADC is not used. If the ADC is used, it should be connected ATmega32A CC 6 ...
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... AVR core architecture in general. The main function of the Block Diagram of the AVR MCU Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega32A Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog Timer ...
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... Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 8155C–AVR–02/11 ATmega32A 8 ...
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... Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 8155C–AVR–02/ R/W R/W R/W R/W R ⊕ V ATmega32A SREG R/W R/W R ...
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... General R14 Purpose R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 6-2, each register is also assigned a data memory address, mapping them ATmega32A 0 Addr. $00 $01 $02 $0D $0E $0F $10 $11 $1A X-register Low Byte $1B X-register High Byte $1C Y-register Low Byte ...
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... Data is pushed onto the stack Return address is pushed onto the stack with a subroutine call or Decremented by 2 interrupt Incremented by 1 Data is popped from the stack Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt ATmega32A Figure 6- R26 ($1A ...
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... Har- The Parallel Instruction Fetches and Instruction Executions T1 clk CPU 1st Instruction Fetch 2nd Instruction Fetch 3rd Instruction Fetch 4th Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU ATmega32A SP12 SP11 SP10 SP9 SP4 ...
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... Total Execution Time Result Write Back ® ® AVR provides several different interrupt sources. These interrupts and the separate for details. “Boot Loader Support – Read-While-Write Self- 253. ATmega32A “Memory Pro- “Interrupts” on page 45. The list also “Interrupts” on page 45 for more ...
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... AVR exits from an interrupt, it will always return to the main program and exe- ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ; set global interrupt enable ATmega32A 14 ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 8155C–AVR–02/11 ATmega32A 15 ...
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... Overview This section describes the different memories in the ATmega32A. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega32A features an EEPROM Memory for data storage. All three memory spaces are linear and regular ...
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... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 2048bytes of internal data SRAM in the ATmega32A are all accessible through all these addressing modes. The Register File is described in 8155C–AVR–02/11 ...
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... I/O Registers $00 $01 $02 ... $3D $3E $3F On-chip Data SRAM Access Cycles T1 clk CPU Address Compute Address Data WR Data RD Memory Access Instruction ATmega32A Data Address Space $0000 $0001 $0002 ... $001D $001E $001F $0020 $0021 $0022 ... $005D $005E $005F Internal SRAM $0060 $0061 ... ...
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... CPU itself can execute instructions incorrectly, if the supply voltage is too low. 8155C–AVR–02/11 ® ® AVR ATmega32A contains 1024bytes of data EEPROM memory organized as contains a detailed description on EEPROM Programming is likely to rise or fall slowly on Power-up/down. This causes the device for CC “Preventing EEPROM Corruption” on page 19 ...
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... All ATmega32A I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions ...
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... Initial Value • Bits [7:4] – Reserved Bits These bits are reserved bits in the ATmega32A and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt ...
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... EEPROM write function must also wait for any ongoing SPM command to finish. 8155C–AVR–02/11 EEPROM Programming Time Number of Calibrated RC Oscillator Symbol 1. Uses 1MHz clock, independent of CKSEL Fuse setting. ATmega32A for details about boot Table 7-1 lists the typical pro- (1) Cycles ...
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... Start eeprom write by setting EEWE sbi EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); ATmega32A 23 ...
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... Start eeprom read by writing EERE sbi EECR,EERE ; Read data from data register in r16,EEDR ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; ATmega32A 24 ...
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... I/O Control Unit clk ASY Clock Multiplexer Timer/Counter External RC External Clock Oscillator Oscillator is halted, enabling TWI address reception in all sleep modes. I/O ATmega32A Figure CPU Core RAM ADC clk CPU clk FLASH Reset Logic Watchdog Timer Source Clock Watchdog Clock Watchdog ...
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... ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. 335. Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out (V CC 4.1ms 65ms ATmega32A (1) CKSEL3:0 1111 - 1010 1000 - 0101 0100 - 0001 = 3.0V) Number of Cycles CC 4.3ms 4K (4,096) ...
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... This option should not be used with crystals, only with ceramic resonators. ATmega32A Figure 8-2. Either a quartz crystal or a Table 8-3. For ceramic resonators, the XTAL2 XTAL1 GND Table 8-3 ...
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... By programming the CKOPT Fuse, the user can enable internal Start-up Times for the Low-frequency Crystal Oscillator Clock Selection Start-up Time from Additional Delay Power-down and from Reset Power-save ( 32K CK ATmega32A Additional Delay from Reset (V = 5.0V) Recommended Usage CC Ceramic resonator, fast rising 4.1ms power Ceramic resonator, slowly 65ms rising power Ceramic resonator, BOD – ...
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... Additional Delay Start-up Time from from Reset Power-down and Power-save ( ( This option should not be used when operating close to the maximum frequency of the device. ATmega32A NC XTAL2 XTAL1 GND Frequency Range (MHz) 0.1 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0 = 5.0V) Recommended Usage CC – ...
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... Start-up Time from Power-down and Power-save The device is shipped with this option selected. 31. To run the device on an external clock, the CKSEL fuses must be programmed ATmega32A Table 8-8. If selected, it will operate with no external Nominal Frequency (MHz) 1.0 2.0 4.0 8.0 Additional Delay ...
Page 31
... Start-up Times for the External Clock Selection Start-up Time from Power-down and Power-save The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator and the internal capacitors have the same nominal value of 36pF. ATmega32A Additional Delay from Reset (V = 5.0V) Recommended Usage CC – BOD enabled 4 ...
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... CAL7 CAL6 CAL5 R/W R/W R/W Device Specific Calibration Value Table Internal RC Oscillator Frequency Range. Min Frequency in Percentage of Nominal Frequency (%) $00 50 $7F 75 $FF 100 ATmega32A CAL4 CAL3 CAL2 CAL1 R/W R/W R/W R/W 8-11. Max Frequency in Percentage of Nominal Frequency (%) 100 150 200 ...
Page 33
... When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Inter- 8155C–AVR–02/11 presents the different clock systems in the ATmega32A, and their distri- Active Clock Domains and Wake Up Sources in the Different Sleep Modes Active Clock domains ...
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... TIMSK, and the Global Interrupt Enable bit in SREG is set. 8155C–AVR–02/11 and clk , while allowing the other clocks to run. CPU FLASH , clk I/O “Clock Sources” on page ATmega32A , and clk , while allowing the CPU FLASH “External Interrupts” on page 69 26. 34 ...
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... In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to configure the Brown-out Detector. 8155C–AVR–02/11 , allowing operation only of asynchronous ASY “Analog to Digital Converter” on page 209 “Analog Comparator” on page 206 “Brown-out Detector” on page 35 ATmega32A for details on how to for details on how to 35 ...
Page 36
... Timer” on page 36 for details on how to configure the Watchdog Timer. ) and the ADC clock (clk I/O “Digital Input Enable and Sleep Modes” on page 54 /2, the input buffer will use excessive power. CC ATmega32A “Internal Volt- ) are stopped, the input buffers of the ADC for 36 ...
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... Sleep Mode Select SM1 SM0 Standby mode and Extended Standby mode are only available with external crystals or resonators. ATmega32A SM0 ISC11 ISC10 ISC01 R/W R/W R/W R Table 9-2. Sleep Mode Idle ADC Noise Reduction Power-down Power-save Reserved Reserved (1) Standby (1) Extended Standby ...
Page 38
... Reset Sources The ATmega32A has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...
Page 39
... Reset Characteristics” on page rise. The RESET signal is activated again, without any delay, CC decreases below the detection level POT RST RESET t TOUT TIME-OUT INTERNAL RESET ATmega32A DATA BUS MCU Control and Status Register (MCUCSR) Delay Counters CK TIMEOUT 299. The POR is activated whenever . CC 39 ...
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... Figure 10-4. External Reset During Operation 10.2.3 Brown-out Detection ATmega32A has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed) ...
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... Figure 10-6. Watchdog Reset During Operation 10.3 Internal Voltage Reference ATmega32A features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V ref- erence to the ADC is generated from the internal bandgap reference. ...
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... Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega32A resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be fol- lowed when the Watchdog is disabled ...
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... Initial Value • Bits 7:5 – Reserved Bits These bits are reserved bits in the ATmega32A and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
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... WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret /* reset WDT */ _WDR(); /* Write logical one to WDTOE and WDE */ WDTCR |= (1<<WDTOE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; ATmega32A Typical Time-out Typical Time-out 3. 5. 17.1ms 16.3ms 34 ...
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... Interrupts This section describes the specifics of the interrupt handling as performed in ATmega32A. For a general explanation of the AVR interrupt handling, refer to page 13. 11.1 Interrupt Vectors in ATmega32A Table 11-1. Vector No Notes: Table 11-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also 8155C– ...
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... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 11-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega32A is: Address Labels $000 $002 $004 $006 ...
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... SPM_RDY ; Store Program Memory Ready Handler RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ldi r16,low(RAMEND) ATmega32A Comments ; Set Stack Pointer to top of RAM ; Enable interrupts ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler Comments ; IRQ0 Handler ; IRQ1 Handler ; ...
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... Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Write Self-Programming” on page 252 ATmega32A ; Enable interrupts 4 3 ...
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... Enable change of interrupt vectors ldi r16, (1<<IVCE) out GICR, r16 ; Move interrupts to boot Flash section ldi r16, (1<<IVSEL) out GICR, r16 ret /* Enable change of interrupt vectors */ GICR = (1<<IVCE); /* Move interrupts to boot Flash section */ GICR = (1<<IVSEL); ATmega32A 49 ...
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... Ground as indicated in CC for a complete list of parameters. Pxn C pin “Register Description” on page 55. Refer to the individual module sections for a full description of the alter- ATmega32A Figure 12-1. Refer to “Electrical Char Logic See Figure 23 "General Digital I/O" for Details 66. “ ...
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... I/O CLOCK I/O 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk and PUD are common to all ports. 66, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATmega32A Figure 12 DDxn Q CLR ...
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... Input 1 1 Input 0 X Output 1 X Output Figure 12-2, the PINxn Register bit and the preceding latch con- pd,max ATmega32A Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 12-3 ...
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... Figure 12-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of through the synchronizer is one system clock period. pd r16 out PORTx, r16 PINxn r17 ATmega32A XXX in r17, PINx 0x00 t pd, max t pd, min , a single signal transition on the pin will be delayed ...
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... Figure 12-2, the digital input signal can be clamped to ground at the input of the /2. CC ATmega32A “Alternate Port Functions” on page 55. 54 ...
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... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. 8155C–AVR–02/11 or GND is not recommended, since this may cause excessive currents if the pin is CC ATmega32A Figure 12-5 Figure 12-2 can be overridden by 55 ...
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... PUD are common to all ports. All other signals are unique for each pin. summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are generated internally ATmega32A PUOExn PUOVxn ...
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... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. Analog Input/ output This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally. ATmega32A Table 12-3. If some 57 ...
Page 58
... ADC1 (ADC input channel 1) PA0 ADC0 (ADC input channel 0) and Table 12-5 relate the alternate functions of Port A to the overriding signals Figure 12-5 on page 56. Overriding Signals for Alternate Functions in PA7:PA4 PA7/ADC7 PA6/ADC6 – ADC7 INPUT ADC6 INPUT ATmega32A PA5/ADC5 PA4/ADC4 – – ADC5 INPUT ...
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... MOSI (SPI Bus Master Output/Slave Input) SS (SPI Slave Select Input) AIN1 (Analog Comparator Negative Input) OC0 (Timer/Counter0 Output Compare Match Output) AIN0 (Analog Comparator Positive Input) INT2 (External Interrupt 2 Input) T1 (Timer/Counter1 External Counter Input) T0 (Timer/Counter0 External Counter Input) XCK (USART External Clock Input/Output) ATmega32A PA1/ADC1 PA0/ADC0 ...
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... MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. 8155C–AVR–02/11 and Table 12-8 relate the alternate functions of Port B to the overriding signals Figure 12-5 on page 56. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the ATmega32A 60 ...
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... OC0 ENABLE 0 OC0 0 0 INT2 ENABLE 0 1 – INT2 INPUT AIN1 INPUT AIN0 INPUT ATmega32A PB5/MOSI PB4/SS SPE • MSTR SPE • MSTR PORTB5 • PUD PORTB4 • PUD SPE • MSTR SPE • MSTR 0 0 SPE • MSTR 0 SPI MSTR OUTPUT ...
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... TDI (JTAG Test Data In) PC4 TDO (JTAG Test Data Out) PC3 TMS (JTAG Test Mode Select) PC2 TCK (JTAG Test Clock) PC1 SDA (Two-wire Serial Bus Data Input/Output Line) PC0 SCL (Two-wire Serial Bus Clock Line) ATmega32A Table 12-9. If the JTAG interface is 62 ...
Page 63
... Port C to the overriding signals Figure 12-5 on page 56. PC7/TOSC2 PC6/TOSC1 AS2 AS2 0 0 AS2 AS2 AS2 AS2 0 0 – – T/C2 OSC OUTPUT T/C2 OSC INPUT ATmega32A PC5/TDI PC4/TDO JTAGEN JTAGEN 1 0 JTAGEN JTAGEN 0 SHIFT_IR + SHIFT_DR 0 JTAGEN 0 TDO JTAGEN JTAGEN 0 0 – – TDI – 63 ...
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... ICP1 (Timer/Counter1 Input Capture Pin) OC1A (Timer/Counter1 Output Compare A Match Output) OC1B (Timer/Counter1 Output Compare B Match Output) INT1 (External Interrupt 1 Input) INT0 (External Interrupt 0 Input) TXD (USART Output Pin) RXD (USART Input Pin) ATmega32A (1) PC1/SDA PC0/SCL TWEN TWEN PORTC1 • PUD PORTC0 • ...
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... Table 12-14 relate the alternate functions of Port D to the overriding signals Figure 12-5 on page 56. PD7/OC2 PD6/ICP1 OC2 ENABLE 0 OC2 – ICP1 INPUT – – ATmega32A PD5/OC1A PD4/OC1B OC1A ENABLE OC1B ENABLE OC1A OC1B – – – – 65 ...
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... R/W R/W R DDA7 DDA6 DDA5 DDA4 R/W R/W R/W R PINA7 PINA6 PINA5 PINA4 N/A N/A N/A N/A ATmega32A PD1/TXD PD0/RXD TXEN RXEN 0 PORTD0 • PUD TXEN RXEN 1 0 TXEN 0 TXD – RXD – – ACME PUD PSR2 PSR10 R/W R/W R/W R ...
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... PINC7 PINC6 PINC5 PINC4 N/A N/A N/A N PORTD7 PORTD6 PORTD5 PORTD4 R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R ATmega32A PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R DDB3 DDB2 DDB1 DDB0 R/W R/W R/W R PINB3 PINB2 PINB1 PINB0 N/A ...
Page 68
... PIND – Port D Input Pins Address Bit Read/Write Initial Value 8155C–AVR–02/ PIND7 PIND6 PIND5 PIND4 N/A N/A N/A N/A ATmega32A PIND3 PIND2 PIND1 PIND0 N/A N/A N/A N/A PIND 68 ...
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... If the level is sampled twice by the Watchdog Oscillator clock but SM2 SM1 SM0 R/W R/W R/W R Table 13-1. The value on the INT1 pin is sampled before ATmega32A 296. The MCU will “System Clock and ISC11 ISC10 ISC01 ISC00 R/W R/W R/W R MCUCR ...
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... The falling edge of INT0 generates an interrupt request. 1 The rising edge of INT0 generates an interrupt request JTD ISC2 – JTRF R/W R Table 13-3 will generate an interrupt. Shorter pulses are not guaranteed to ATmega32A WDRF BORF EXTRF PORF R/W R/W R/W R/W See Bit Description MCUCSR 70 ...
Page 71
... Asynchronous External Interrupt Characteristics Parameter Minimum pulse width for asynchronous external interrupt INT1 INT0 INT2 – R/W R/W R INTF1 INTF0 INTF2 – R/W R/W R ATmega32A Condition Min Typ Max – – IVSEL IVCE R R R/W R – – – – ...
Page 72
... Note that when entering some sleep modes with the INT2 interrupt disabled, the input buffer on this pin will be disabled. This may cause a logic change in internal signals which will set the INTF2 Flag. See Modes” on page 54 8155C–AVR–02/11 for more information. ATmega32A “Digital Input Enable and Sleep 72 ...
Page 73
... The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register 8155C–AVR–02/11 “Pinout ATmega32A” on page 2. CPU accessible I/O Registers, including I/O 84. TCCRn ...
Page 74
... The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0 Register. The assignment is dependent on the mode of operation. DATA BUS count clear TCNTn Control Logic direction BOTTOM ATmega32A See “Output Compare 88. TOVn (Int. Req.) Clock Select Edge Detector clk Tn ...
Page 75
... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 78. (See “Modes of Operation” on page shows a block diagram of the output compare unit. ATmega32A in the following. T0 78.). 75 ...
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... TCNT0 when using the output compare unit, inde- pendently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals 8155C–AVR–02/11 DATA BUS OCRn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega32A TCNTn OCFn (Int.Req.) OCn COMn1:0 76 ...
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... The design of the output compare pin logic allows initialization of the OC0 state before the out- put is enabled. Note that some COM01:0 bit settings are reserved for certain modes of operation. 8155C–AVR–02/11 COMn1 Waveform COMn0 Generator FOCn clk I/O See “Register Description” on page 84. ATmega32A Figure 14-4 shows a simplified OCn PORT D ...
Page 78
... Table 14-3 on page 85. For fast PWM mode, refer to Table 14-5 on page (See “Compare Match Output Unit” on page Figure 14-8, 82. 0 Flag, the timer resolution can be increased by software. TOV ATmega32A Table 14-4 on page 86. 77.). Figure 14-9, Figure 14-10 and Figure 14-11 ...
Page 79
... PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and 8155C–AVR–02/ clk_I ---------------------------------------------- - OCn ⋅ ⋅ OCRn 1 + Figure 14-6. The TCNT0 value is in the timing diagram shown as a his- ATmega32A OCn Interrupt Flag Set (COMn1 OC0 clk_I ...
Page 80
... PWM modes, these modes are preferred for motor control applications. 8155C–AVR–02/11 TCNTn OCn OCn Period OCnPWM ATmega32A OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set (COMn1 (COMn1 Table 14-4 on page 85). The actual OC0 value ...
Page 81
... PWM mode. If the OCR0 is set equal to BOTTOM, the out- 8155C–AVR–02/ Table 14-5 on page f clk_I ----------------- - OCnPCPWM ⋅ N 510 ATmega32A Figure 14-7. OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 86). The actual OC0 81 ...
Page 82
... Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ATmega32A OCn has a transition from high to low even though Figure 14-7. When the OCR0A value is MAX the ) is therefore shown MAX ...
Page 83
... I/O Tn /8) I/O MAX - 1 shows the setting of OCF0 in all modes except CTC mode. I/O Tn /8) I/O OCRn - 1 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. ATmega32A /8) clk_I/O MAX BOTTOM OCRn OCRn + 1 OCRn Value BOTTOM + 1 /8) clk_I/O OCRn + 2 83 ...
Page 84
... Pulse Width Modulation (PWM) modes. See Operation” on page 8155C–AVR–02/11 caler (f /8) clk_I/O I/O Tn /8) I/O TOP - FOC0 WGM00 COM01 W R/W R 78. ATmega32A TOP BOTTOM TOP COM00 WGM01 CS02 CS01 R/W R/W R/W R Table 14-2 BOTTOM + 1 0 CS00 ...
Page 85
... A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare match is ignored, but the set or clear is done at BOTTOM. See for more details. shows the COM0[1:0] bit functionality when the WGM01:0 bits are set to phase cor- ATmega32A (1) Update of TOV0 Flag ...
Page 86
... I/O clk 0 1 /1024 (From prescaler) I External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge R/W R/W R R/W R/W R ATmega32A (1) “Phase Correct PWM Mode” on page TCNT0[7:0] R/W R/W R/W R OCR0[7:0] R/W R/W R/W R ...
Page 87
... PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00. 8155C–AVR–02/ OCIE2 TOIE2 TICIE1 OCIE1A R/W R/W R/W R OCF2 TOV2 ICF1 OCF1A R/W R/W R/W R ATmega32A OCIE1B TOIE1 OCIE0 TOIE0 R/W R/W R/W R OCF1B TOV1 OCF0 TOV0 R/W R/W R/W R TIMSK TIFR ...
Page 88
... Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 /clk T1 ATmega32A /8, f /64, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative T 0 ...
Page 89
... Q LE I/O Synchronization < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O I/O Clear Synchronization Synchronization clk 1. The synchronization logic on the input pins ( ATmega32A D Q Edge Detector (1) T1 T1/T0) is shown in Figure Tn_sync (To Clock Select Logic) /2.5. clk_I/O clk T0 15-1 ...
Page 90
... Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. 8155C–AVR–02/ ADTS2 ADTS1 ADTS0 – R/W R/W R ATmega32A ACME PUD PSR2 PSR10 R/W R/W R/W R SFIOR 90 ...
Page 91
... I/O pins, refer to bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 8155C–AVR–02/11 Figure 1-1 on page 2. CPU accessible I/O Registers, including I/O 112. ATmega32A Figure 16-1. For the actual 91 ...
Page 92
... Count Clear Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA 1. Refer to Figure 1-1 on page 2, Table 12-6 on page Timer/Counter1 pin placement and description. ATmega32A (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int.Req.) Waveform ...
Page 93
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR1A or ICR1 Register. The assign- ment is dependent of the mode of operation. ATmega32A (See 93 ...
Page 94
... Therefore, when both 8155C–AVR–02/11 ( Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H :. (1) unsigned int Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into TCNT1 See “About Code Examples” on page ATmega32A 6. 94 ...
Page 95
... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See “About Code Examples” on page ATmega32A 6. 95 ...
Page 96
... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; 1. See “About Code Examples” on page “Timer/Counter0 and Timer/Counter1 Prescalers” on page ATmega32A 6. 88. 96 ...
Page 97
... Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear “Modes of Operation” on page ATmega32A TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 103 ...
Page 98
... TEMP Register. 8155C–AVR–02/11 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ATmega32A Figure 16-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) ...
Page 99
... Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 8155C–AVR–02/11 94. ATmega32A “Accessing 16-bit Registers” (Figure 15-1 on page 89). The edge detector is also ...
Page 100
... TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) = TOP Waveform Generator BOTTOM WGMn3:0 ATmega32A 103.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) (16-bit Comparator ) OCFnx (Int.Req.) COMnx1:0 OCnx 100 ...
Page 101
... Normal mode. The OC1x Register keeps its value even when changing between waveform generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 8155C–AVR–02/11 94. ATmega32A “Accessing 16-bit Registers” 101 ...
Page 102
... COMnx1 Waveform COMnx0 D Generator FOCnx D PORT D clk I/O See “Register Description” on page 112. Table 16-2 on page ATmega32A Figure 16-5 shows a simplified Q 1 OCnx Pin OCnx DDR Table 16-2, Table 16-3 and 112. For fast PWM mode refer to ...
Page 103
... The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. 8155C–AVR–02/11 102.) “Timer/Counter Timing Diagrams” on page Figure 16-6. The counter value (TCNT1) ATmega32A 110. 103 ...
Page 104
... PWM mode well suited for power regulation, rectification, and DAC 8155C–AVR–02/ when OCR1A is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - OCnA ⋅ ATmega32A OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA 1 + 104 ...
Page 105
... The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low 8155C–AVR–02/11 ( TOP log R = ---------------------------------- - FPWM log ATmega32A ) + Figure 16-7. The figure OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set OCnA Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...
Page 106
... However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. 8155C–AVR–02/11 Table 16-2 on page f clk_I ---------------------------------- - OCnxPWM ⋅ TOP when OCR1A is set to zero (0x0000). This feature clk_I/O 1 ATmega32A 112). The actual OC1x ) 106 ...
Page 107
... TOP actively while the Timer/Counter is running in the phase correct mode can result in an 8155C–AVR–02/ TOP log + ---------------------------------- - PCPWM log Figure 16-8 ATmega32A Figure 16-8. The figure OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) (COMnx1 (COMnx1 illustrates, changing the 107 ...
Page 108
... Figure The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and 8155C–AVR–02/11 f OCnxPCPWM 16-9). ATmega32A Table 16-2 on page f clk_I/O = --------------------------- - ⋅ ⋅ TOP 112) ...
Page 109
... R = ---------------------------------- - PFCPWM Figure 16-9. The figure shows phase and frequency correct shows the output generated is, in contrast to the phase correct mode, symmetri- ATmega32A ( ) TOP + log OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update ...
Page 110
... OCRnx OCFnx Figure 16-11 8155C–AVR–02/11 f OCnxPFCPWM Figure 16-10 I/O Tn /1) I/O OCRnx - 1 shows the same timing data, but with the prescaler enabled. ATmega32A f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown shows a timing diagram for the setting of OCF1x. OCRnx OCRnx + 1 OCRnx Value ...
Page 111
... Tn (clk /1) I/O TCNTn TOP - 1 TCNTn TOP - 1 (FPWM) (if used as TOP) OCRnx Old OCRnx Value shows the same timing data, but with the prescaler enabled. ATmega32A OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 BOTTOM + 1 TOP - 2 111 ...
Page 112
... TOP) OCRnx Old OCRnx Value COM1A1 COM1A0 COM1B1 R/W R/W R Table 16-2 Compare Output Mode, non-PWM COM1A0/COM1B0 ATmega32A /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value COM1B0 FOC1A FOC1B WGM11 R R shows the COM1x1:0 bit functionality when the Description Normal port operation, OC1A/OC1B disconnected. ...
Page 113
... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. “Phase Correct PWM Mode” on page 106. ATmega32A (1) Description Normal port operation, OC1A/OC1B disconnected. WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM13:0 settings, normal port operation, OC1A/OC1B disconnected ...
Page 114
... CTC 0 1 Reserved 1 0 Fast PWM 1 1 Fast PWM ICNC1 ICES1 – R/W R ATmega32A (See “Modes of Operation” on page Update of x TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF BOTTOM 0x01FF BOTTOM 0x03FF BOTTOM ICR1 BOTTOM ...
Page 115
... No clock source (Timer/Counter stopped clk /1 (No prescaling) I clk /8 (From prescaler) I clk /64 (From prescaler) I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge. ATmega32A Figure 115 ...
Page 116
... R/W R/W R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R See “Accessing 16-bit Registers” on page 94 ICR1[15:8] ICR1[7:0] R/W R/W R/W R ATmega32A R/W R/W R/W R See “Accessing 16-bit R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R TCNT1H ...
Page 117
... TOV1 Flag, located in TIFR, is set OCF2 TOV2 ICF1 R/W R/W R This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. ATmega32A OCIE1A OCIE1B TOIE1 OCIE0 R/W R/W R/W R ...
Page 118
... TOV1 Flag is set when the timer overflows. Refer to behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 8155C–AVR–02/11 ATmega32A Table 16-5 on page 114 for the TOV1 Flag 118 ...
Page 119
... I/O pins, refer to bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page Figure 17-1. 8-bit Timer/Counter Block Diagram 8155C–AVR–02/11 “Pinout ATmega32A” on page 132. TCCRn count clear Control Logic ...
Page 120
... OCR2 Register. The assignment is dependent on the mode of operation default equal to the MCU clock, clk T2 135. For details on clock sources and prescaler, see 132. ATmega32A See “Output Compare Table 17-1 are also used exten- . When the AS2 I/O “ ...
Page 121
... T2 is present or not. A CPU write overrides (has priority over) all counter clear or T2 124. can be used for generating a CPU interrupt. TOV2 124). Figure 17-3 shows a block diagram of the output compare unit. ATmega32A TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler (“Modes of Operation” ...
Page 122
... OCR2 value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. 8155C–AVR–02/11 DATA BUS OCRn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 COMn1:0 ATmega32A TCNTn OCFn (Int.Req.) OCxy 122 ...
Page 123
... OC2 Register performed on the next compare match. For compare output actions in the non-PWM modes refer to page 134, and for phase correct PWM refer to 8155C–AVR–02/11 COMn1 Waveform COMn0 Generator FOCn clk I/O “Register Description” on page 132 Table 17-3 on page ATmega32A Figure 17-4 shows a simplified OCn OCn Pin PORT D ...
Page 124
... TCNT2 and OCR2, and then counter (TCNT2) is cleared. 8155C–AVR–02/11 (See “Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page Flag, the timer resolution can be increased by software. There TOV2 ATmega32A 123.). 128. ) will be set in the same TOV2 Flag in this case behaves like a ninth TOV2 Figure 17-5 ...
Page 125
... The counter is then cleared at the following timer clock cycle. The timing diagram for the fast 8155C–AVR–02/ clk_I ---------------------------------------------- - OCn ⋅ ⋅ OCRn 1 + Flag is set in the same timer clock cycle that the TOV2 ATmega32A OCn Interrupt Flag Set (COMn1 OC2 ) = 125 ...
Page 126
... The TCNT2 value is in the timing diagram shown as a his- TCNTn OCn OCn Period set each time the counter reaches MAX. If the inter- TOV2 f OCnPWM ATmega32A OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set (COMn1 (COMn1 Table 17-4 on page 134). The actual OC2 ...
Page 127
... OC2 Register at compare match between OCR2 and TCNT2 when the counter decrements. The 8155C–AVR–02/11 TCNTn OCn OCn Period 1 TOV2 ATmega32A OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 set each time the counter reaches BOTTOM. The ...
Page 128
... OCnPCPWM Figure 17-7 contains timing data for basic Timer/Counter operation. The figure shows the I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ATmega32A f clk_I/O = ----------------- - ⋅ N 510 OCn has a transition from high to low even though Figure 17-7 ...
Page 129
... I/O Tn /8) I/O MAX - 1 shows the setting of OCF2 in all modes except CTC mode. I/O Tn /8) I/O OCRn - 1 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. ATmega32A /8) clk_I/O MAX BOTTOM OCRn OCRn + 1 OCRn Value BOTTOM + 1 /8) clk_I/O OCRn + 2 129 ...
Page 130
... OCR2 or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. 8155C–AVR–02/11 caler (f /8) clk_I/O clk I/O clk Tn /8) I/O TOP - 1 ATmega32A TOP BOTTOM BOTTOM + 1 TOP 130 ...
Page 131
... Interrupt Flag. The output compare pin is changed on the timer clock and is not synchronized to the processor clock. 8155C–AVR–02/11 ) again becomes active, TCNT2 will read as the previous value (before entering I/O ATmega32A 131 ...
Page 132
... By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously IO /256, and clk /1024. Additionally, clk T2S T2S FOC2 WGM20 COM21 COM20 W R/W R ATmega32A 10-BIT T/C PRESCALER 0 TIMER/COUNTER2 CLOCK SOURCE clk T2 . clk is by default connected to the main T2S T2S /8, clk T2S as well as 0 (stop) may be selected. T2S WGM21 ...
Page 133
... Compare Output Mode, non-PWM Mode COM20 Description 0 0 Normal port operation, OC2 disconnected Toggle OC2 on compare match 1 0 Clear OC2 on compare match 1 1 Set OC2 on compare match ATmega32A Table 17-2 and “Modes of Operation” (1) Update of TOV2 Flag TOP OCR2 Set on 0xFF Immediate MAX 0xFF TOP ...
Page 134
... T2S clk 0 1 T2S 1 0 clk clk ATmega32A (1) “Fast PWM Mode” on page 125 (1) “Phase Correct PWM Mode” on page /(No prescaling) /8 (From prescaler) /32 (From prescaler) /64 (From prescaler) /128 (From prescaler) /256 (From prescaler) /1024 (From prescaler) for Table 134 ...
Page 135
... TCNT2[7:0] R/W R/W R/W R OCR2[7:0] R/W R/W R/W R – – – – AS2 R ATmega32A R/W R/W R/W R R/W R/W R/W R TCN2UB OCR2UB TCR2UB When AS2 is I/O TCNT2 OCR2 ASSR 135 ...
Page 136
... PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00. 8155C–AVR–02/ OCIE2 TOIE2 TICIE1 OCIE1A R/W R/W R/W R OCF2 TOV2 ICF1 OCF1A R/W R/W R/W R ATmega32A OCIE1B TOIE1 OCIE0 TOIE0 R/W R/W R/W R OCF1B TOV1 OCF0 TOV0 R/W R/W R/W R TIMSK ...
Page 137
... Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. 8155C–AVR–02/ ADTS2 ADTS1 ADTS0 – R/W R/W R ATmega32A ACME PUD PSR2 PSR10 R/W R/W R/W R SFIOR 137 ...
Page 138
... Double Speed (CK/2) Master SPI Mode 18.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega32A and peripheral devices or between several AVR devices. Figure 18-1. SPI Block Diagram Note: The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two Shift Registers, and a Master clock generator. The SPI Master initiates the 8155C– ...
Page 139
... Low periods: longer than 2 CPU clock cycles. High periods: longer than 2 CPU clock cycles. 8155C–AVR–02/11 MSB MASTER LSB MISO 8 BIT SHIFT REGISTER MOSI SPI SCK CLOCK GENERATOR SS ATmega32A MSB SLAVE LSB MISO 8 BIT SHIFT REGISTER MOSI SHIFT SCK ENABLE SS 139 ...
Page 140
... SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined See “Alternate Functions of Port B” on page 59 direction of the user defined SPI pins. ATmega32A “Alternate Port Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the 140 ...
Page 141
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “About Code Examples” on page ATmega32A 6. 141 ...
Page 142
... Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; 1. See “About Code Examples” on page ATmega32A 6. 142 ...
Page 143
... Bit 6 – SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. 8155C–AVR–02/ SPIE SPE DORD MSTR R/W R/W R/W R ATmega32A CPOL CPHA SPR1 SPR0 R/W R/W R/W R SPCR 143 ...
Page 144
... CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup Relationship Between SCK and the Oscillator Frequency SPR1 ATmega32A for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and Figure 18-4 for an example. The CPHA Trailing Edge Setup Sample SPR0 SCK Frequency osc osc f / ...
Page 145
... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega32A is also used for program memory and EEPROM down- loading or uploading. See 18.3.5 SPDR – SPI Data Register ...
Page 146
... SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega32A Trailing Edge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit 3 Bit 4 Bit 5 Bit 6 ...
Page 147
... Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. A simplified block diagram of the USART transmitter is shown in 8155C–AVR–02/11 Figure 19-1. CPU accessible I/O Registers and I/O pins are shown in bold. ATmega32A 147 ...
Page 148
... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to Figure 1-1 on page 2, Table 12-14 on page pin placement. ATmega32A Clock Generator OSC SYNC LOGIC PIN XCK CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN CONTROL ...
Page 149
... The XCK pin is only active when using Synchronous mode. Figure 19-2 8155C–AVR–02/11 shows a block diagram of the clock generation logic. ATmega32A Figure 19-1) if the Buffer Registers 149 ...
Page 150
... Input from XCK pin (Internal Signal). Used for synchronous slave operation. Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock). contains equations for calculating the baud rate (in bits per second) and for calculat- ATmega32A U2X / ...
Page 151
... Baud rate (in bits per second, bps) System Oscillator clock frequency Contents of the UBRRH and UBRRL Registers 4095) 172). Figure 19-2 for details. depends on the stability of the system clock source therefore recommended to osc ATmega32A Equation for Calculating Equation for Calculating (1) Baud Rate f OSC BAUD ...
Page 152
... Bits inside brackets are (IDLE Start bit, always low. Data bits (0 to 8). Parity bit. Can be odd or even. Stop bit, always high. No transfers on the communication line (RxD or TxD). An IDLE line must high. ATmega32A Sample Sample FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) 152 ...
Page 153
... even n 1 – ⊕ odd n 1 – Parity bit using even parity even Parity bit using odd parity odd Data bit n of the character n ATmega32A … ⊕ ⊕ ⊕ ⊕ ⊕ … ⊕ ⊕ ⊕ ⊕ ⊕ ...
Page 154
... Set baud rate */ UBRRH = (unsigned char)(baud>>8); UBRRL = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRB = (1<<RXEN)|(1<<TXEN); /* Set frame format: 8data, 2stop bit */ UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0); 1. See “About Code Examples” on page ATmega32A 6. 154 ...
Page 155
... UCSRA,UDRE rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDR,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<<UDRE Put data into buffer, sends the data */ UDR = data; 1. See “About Code Examples” on page ATmega32A 6. 155 ...
Page 156
... UCSRB |= (1<<TXB8); /* Put data into buffer, sends the data */ UDR = data; 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRB is static (that is, only the TXB8 bit of the UCSRB Register is used after initialization). ATmega32A 156 ...
Page 157
... Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDR I/O location. The following code example shows a simple USART receive function based on polling of the Receive Complete (RXC) Flag. When using frames with less than eight bits the most significant 8155C–AVR–02/11 ATmega32A 157 ...
Page 158
... UCSRA, RXC rjmp USART_Receive ; Get and return received data from buffer in r16, UDR ret (1) /* Wait for data to be received */ while ( !(UCSRA & (1<<RXC Get and return received data from buffer */ return UDR; 1. See “About Code Examples” on page ATmega32A 6. 158 ...
Page 159
... UCSRA; resh = UCSRB; resl = UDR error, return - status & (1<<FE)|(1<<DOR)|(1<<PE) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “About Code Examples” on page ATmega32A 6. 159 ...
Page 160
... The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (PE) Flag can then be read by software to check if the frame had a parity error. 8155C–AVR–02/11 and “Parity Checker” on page 160. ATmega32A 160 ...
Page 161
... RxD line is idle (that is, no communication activity). 8155C–AVR–02/11 (1) sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush (1) unsigned char dummy; while ( UCSRA & (1<<RXC) ) dummy = UDR; 1. See “About Code Examples” on page ATmega32A 6. Figure 19-5 161 ...
Page 162
... Note that the receiver only uses the first stop bit of a frame. Figure 19-7 of the next frame. 8155C–AVR–02/11 IDLE Figure 19 shows the sampling of the stop bit and the earliest possible beginning of the start bit ATmega32A START shows the sampling of the data bits and the par- BIT ...
Page 163
... Middle sample number used for majority voting for Double Speed mode the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate the ratio of the fastest incoming data rate that can be fast accepted in relation to the receiver baud rate. ATmega32A STOP 1 (A) (B) ( 0/1 ...
Page 164
... ATmega32A Max Total Error Recommended Max Receiver (%) Error (%) +6.67/-6.8 ±3.0 +5.79/-5.88 ±2.5 +5.11/-5.19 ±2.0 +4.58/-4.54 ±2.0 +4.14/-4.19 ±1.5 +3.78/-3.83 ±1.5 Max Total Error ...
Page 165
... When doing a write access of this I/O location, the high bit of the value written, the USART Reg- ister Select (URSEL) bit, controls which one of the two registers that will be written. If URSEL is zero during a write operation, the UBRRH value will be updated. If URSEL is one, the UCSRC setting will be updated. 8155C–AVR–02/11 ATmega32A 165 ...
Page 166
... UCSRC,r16 :. ( Set UBRRH UBRRH = 0x02 Set the USBS and the UCSZ1 bit to one, and */ /* the remaining bits to zero. */ UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1 See “About Code Examples” on page ATmega32A 6. 166 ...
Page 167
... SBIS), since these also will change the state of the FIFO. 8155C–AVR–02/11 (1) ; Read UCSRC in r16,UBRRH in r16,UCSRC ret (1) unsigned char ucsrc; /* Read UCSRC */ ucsrc = UBRRH; ucsrc = UCSRC; return ucsrc; 1. See “About Code Examples” on page R/W R/W R ATmega32A RXB[7:0] TXB[7:0] R/W R/W R/W R UDR (Read) UDR (Write) R/W 0 167 ...
Page 168
... This bit only has effect for the asynchronous operation. Write this bit to zero when using syn- chronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from effectively dou- bling the transfer rate for asynchronous communication. 8155C–AVR–02/ RXC TXC UDRE ATmega32A DOR PE U2X MPCM R R R/W R UCSRA 168 ...
Page 169
... RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDR. 8155C–AVR–02/11 “Multi-processor Communication Mode” on page RXCIE TXCIE UDRIE RXEN R/W R/W R/W R ATmega32A 164 TXEN UCSZ2 RXB8 TXB8 R/W R UCSRB 169 ...
Page 170
... R/W R/W R UMSEL Bit Settings UMSEL Mode 0 Asynchronous Operation 1 Synchronous Operation UPM Bits Settings UPM1 UPM0 ATmega32A UPM0 USBS UCSZ1 UCSZ0 R/W R/W R/W R section which describes how to access this register. Parity Mode Disabled Reserved Enabled, Even Parity Enabled, Odd Parity 0 ...
Page 171
... Rising XCK Edge Falling XCK Edge URSEL – – R R/W R/W R section which describes how to access this register. ATmega32A Stop Bit(s) 1-bit 2-bit UCSZ0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit Received Data Sampled (Input on RxD Pin) Falling XCK Edge ...
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... ATmega32A Table “Asynchronous Operational ⎞ • Closest Match – 100% ⎠ BaudRate f = 2.0000MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 95 0.0% 51 0.2% 47 0. ...
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... UBRR = 0, Error = 0.0% 8155C–AVR–02/ 1.8432MHz osc U2X = 1 U2X = 0 Error UBRR Error – – – – – – 125Kbps 115.2Kbps ATmega32A f = 2.0000MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 0 0.0% – – – – – – 230.4Kbps 125Kbps U2X = 1 ...
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... ATmega32A f = 7.3728MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 207 0.2% 191 0.0% 103 0.2% 95 0.0% 51 0.2% 47 0.0% 34 -0.8% 31 0. ...
Page 175
... ATmega32A MHz f = 14.7456MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0. ...
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... Max 1. 8155C–AVR–02/11 (Continued) U2X = 0 UBRR 416 207 103 1Mbps UBRR = 0, Error = 0.0% ATmega32A f = 16.0000MHz osc U2X = 1 Error UBRR -0.1% 832 0.2% 416 0.2% 207 0.6% 138 0.2% 103 -0.8% 68 0.2% 51 2.1% 34 0.2% 25 -3. ...
Page 177
... TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol. Figure 20-1. TWI Bus Interconnection SDA SCL 8155C–AVR–02/11 Device 1 Device 2 Device 3 ATmega32A V CC ........ Device 177 ...
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... The device placing data on the bus. The device reading data from the bus. Figure 20-1, both bus lines are connected to the positive supply voltage through “Two-wire Serial Interface Characteristics” on page SDA SCL Data Stable Data Change ATmega32A 300. Two Data Stable 178 ...
Page 179
... Note that transmitting the general call address followed by a Read bit is meaningless, as this would cause contention if several slaves started transmitting different data. All addresses of the format 1111 xxx should be reserved for future purposes. 8155C–AVR–02/11 START STOP START ATmega32A REPEATED START STOP 179 ...
Page 180
... SLA+R/W and the STOP condition, depending on the software protocol imple- mented by the application software. 8155C–AVR–02/11 Addr MSB 1 2 START Data MSB 1 2 SLA+R/W shows a typical data transmission. Note that several data bytes can be transmitted ATmega32A Addr LSB R/W ACK Data LSB ACK ...
Page 181
... Addr MSB Addr LSB R/W ACK START SLA+R/W TA low SCL from Master A SCL from Master B SCL bus Line TB Masters Start Counting Low Period ATmega32A Data MSB Data LSB Data Byte TA high TB low high Masters Start Counting High Period ACK 9 STOP 181 ...
Page 182
... The TWI module is comprised of several submodules, as shown in drawn in a thick line are accessible through the AVR data bus. 8155C–AVR–02/11 START SDA from Master A SDA from Master B SDA Line SCL Line ATmega32A Master A Loses Arbitration, SDA SDA A Figure 20-9. All registers 182 ...
Page 183
... Address Match Unit Address Register (TWAR) Address Comparator SCL frequency Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See Table 27-2 on page 300 ATmega32A SDA Spike Filter Bit Rate Generator Prescaler Bit Rate Register Ack ...
Page 184
... After the TWI has been addressed by own slave address or general call • After the TWI has received a data byte • After a STOP or REPEATED START has been received while still addressed as a slave • When a bus error has occurred due to an illegal START or STOP condition 8155C–AVR–02/11 ATmega32A 184 ...
Page 185
... SLA TWINT set. Status code indicates SLA+W sent, ACK received ATmega32A 7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, making sure that TWINT is written to one Data A STOP 6 ...
Page 186
... TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting. In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made, for example by using include-files. 8155C–AVR–02/11 ATmega32A 186 ...
Page 187
... MT_DATA_ACK) ERROR(); TWCR = (1<<TWINT)|(1<<TWEN)| (1<<TWSTO); ATmega32A Comments Send START condition Wait for TWINT Flag set. This indicates that the START condition has been transmitted Check value of TWI Status Register. Mask prescaler bits ...
Page 188
... Table 20-2 to Table 20-11). In order to enter a Master mode, a START condition must be transmitted. The for- Device 1 Device 2 MASTER SLAVE TRANSMITTER RECEIVER TWINT TWEA TWSTA ATmega32A 20-5. Note that the prescaler bits are masked to zero Device 3 ........ Device n R1 TWSTO TWWC TWEN – TWIE ...
Page 189
... STA 0 1 Load SLA Load SLA Load SLA Load data byte TWDR action TWDR action TWDR action 1 ATmega32A Table 20-2). In order to enter MT mode, TWSTO TWWC TWEN TWSTO TWWC TWEN TWSTO TWWC TWEN TWSTO TWWC TWEN TWEA Next Action Taken by TWI Hardware X SLA+W will be transmitted ...
Page 190
... No TWDR action TWDR action TWDR action 1 ATmega32A X Data byte will be transmitted and ACK or NOT ACK will be received X Repeated START will be transmitted X STOP condition will be transmitted and TWSTO Flag will be reset X STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset ...
Page 191
... MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. 8155C–AVR–02/ SLA W $ DATA From master to slave From slave to master 20-13). In order to enter a Master mode, a START condition must be transmitted. The for- ATmega32A A DATA A P $ $20 ...
Page 192
... X 1 TWINT TWEA TWSTA Table 20-3. Received data can be read from the TWDR Register when the TWINT TWINT TWEA TWSTA TWINT TWEA TWSTA ATmega32A V CC ........ Device n R1 TWSTO TWWC TWEN Table 20-2). In order to enter MR mode, TWSTO TWWC TWEN TWSTO TWWC TWEN ...
Page 193
... Read data byte Read data byte Read data byte 1 ATmega32A TWEA Next Action Taken by TWI Hardware X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+W will be transmitted Logic will switch to masTer Transmitter mode ...
Page 194
... From master to slave From slave to master 20-15). All the status codes mentioned in this section assume that the prescaler bits are Device 1 Device 2 SLAVE MASTER RECEIVER TRANSMITTER TWA6 TWA5 TWA4 Device’s Own Slave Address ATmega32A DATA A DATA A P $50 $ $10 P Other master ...
Page 195
... Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. 8155C–AVR–02/11 TWINT TWEA TWSTA TWSTO ATmega32A TWWC TWEN – TWIE Table 20-4. 195 ...
Page 196
... No action ATmega32A TWEA Next Action Taken by TWI Hardware 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned ...
Page 197
... Arbitration lost as master and addressed as slave by general call DATA From master to slave From slave to master 20-17). All the status codes mentioned in this section assume that the prescaler bits are Device 1 Device 2 SLAVE MASTER TRANSMITTER RECEIVER ATmega32A A DATA A DATA $60 $80 $80 $88 A $68 A ...
Page 198
... Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. 8155C–AVR–02/11 TWA6 TWA5 TWA4 TWA3 Device’s Own Slave Address TWINT TWEA TWSTA TWSTO ATmega32A TWA2 TWA1 TWA0 TWGCE TWWC TWEN – TWIE Table 20-5. 198 ...
Page 199
... No TWDR action TWDR action TWDR action 1 ATmega32A TWEA Next Action Taken by TWI Hardware 0 Last data byte will be transmitted and NOT ACK should be received 1 Data byte will be transmitted and ACK should be re- ceived 0 Last data byte will be transmitted and NOT ACK should ...
Page 200
... From master to slave From slave to master n Application Software Response To TWCR To/from TWDR STO TWINT STA No TWDR action No TWCR action TWDR action 0 ATmega32A DATA A DATA $B8 $C0 A All 1's $C8 Any number of data bytes A and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus ...