ATMEGA32A-PU Atmel, ATMEGA32A-PU Datasheet - Page 112

• Manufacturer Part Number: ATMEGA32A-PU
• Description: MCU AVR 32K FLASH 16MHZ 40-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Rom Size: 1024 B
• Height: 4.83 mm
• Length: 52.58 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 13.97 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.10 Register Description
16.10.1
8155C–AVR–02/11
TCCR1A – Timer/Counter1 Control Register A
Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (f
• Bit 7:6 – COM1A1:0: Compare Output Mode for Compare unit A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Compare unit B
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-
tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen-
dent of the WGM13:0 bits setting.
WGM13:0 bits are set to a normal or a CTC mode (non-PWM).
Table 16-2.
Bit
Read/Write
Initial Value
COM1A1/COM1B1
(PC and PFC PWM)
and ICFn
(CTC and FPWM)
TOVn
(Update at TOP)
TCNTn
TCNTn
OCRnx
as TOP)
(clk
clk
clk
0
0
1
1
I/O
(FPWM)
I/O
Tn
/8)
(if used
COM1A1
Compare Output Mode, non-PWM
R/W
7
0
COM1A0
R/W
6
0
COM1A0/COM1B0
TOP - 1
TOP - 1
COM1B1
Old OCRnx Value
R/W
0
1
0
1
Table 16-2
5
0
COM1B0
R/W
4
0
shows the COM1x1:0 bit functionality when the
Description
Normal port operation, OC1A/OC1B disconnected.
Toggle OC1A/OC1B on compare match
Clear OC1A/OC1B on compare match (Set output
to low level)
Set OC1A/OC1B on compare match (Set output to
high level)
TOP
TOP
FOC1A
W
3
0
FOC1B
W
clk_I/O
2
0
BOTTOM
TOP - 1
/8)
New OCRnx Value
WGM11
R/W
1
0
ATmega32A
WGM10
BOTTOM + 1
R/W
0
0
TOP - 2
TCCR1A
112