ATMEGA32A-PU Atmel, ATMEGA32A-PU Datasheet - Page 171

• Manufacturer Part Number: ATMEGA32A-PU
• Description: MCU AVR 32K FLASH 16MHZ 40-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Rom Size: 1024 B
• Height: 4.83 mm
• Length: 52.58 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 13.97 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.11.5
8155C–AVR–02/11
UBRRL and UBRRH – USART Baud Rate Registers
Table 19-6.
• Bit 2:1 – UCSZ1:0: Character Size
The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Char-
acter Size) in a frame the Receiver and Transmitter use.
Table 19-7.
• Bit 0 – UCPOL: Clock Polarity
This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is
used. The UCPOL bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCK).
Table 19-8.
The UBRRH Register shares the same I/O location as the UCSRC Register. See the
UBRRH/ UCSRC Registers” on page 165
Bit
Read/Write
Initial Value
UCPOL
0
1
UCSZ2
0
0
0
0
1
1
1
1
Transmitted Data Changed (Output of TxD
Pin)
Rising XCK Edge
Falling XCK Edge
USBS Bit Settings
UCSZ Bits Settings
UCPOL Bit Settings
URSEL
USBS
R/W
R/W
15
7
0
0
0
1
R/W
14
R
–
6
0
0
UCSZ1
0
0
1
1
0
0
1
1
R/W
13
R
–
5
0
0
section which describes how to access this register.
R/W
12
R
–
4
0
0
UBRR[7:0]
UCSZ0
0
1
0
1
0
1
0
1
R/W
R/W
11
3
0
0
Received Data Sampled (Input on RxD
Pin)
Falling XCK Edge
Rising XCK Edge
R/W
Stop Bit(s)
R/W
10
2
0
0
UBRR[11:8]
1-bit
2-bit
R/W
R/W
Character Size
9
1
0
0
ATmega32A
Reserved
Reserved
Reserved
5-bit
6-bit
7-bit
8-bit
9-bit
R/W
R/W
8
0
0
0
“Accessing
UBRRH
UBRRL
171