ATMEGA32A-PU Atmel, ATMEGA32A-PU Datasheet - Page 259

• Manufacturer Part Number: ATMEGA32A-PU
• Description: MCU AVR 32K FLASH 16MHZ 40-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Rom Size: 1024 B
• Height: 4.83 mm
• Length: 52.58 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 13.97 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.8
25.8.1
25.8.2
8155C–AVR–02/11
Self-Programming the Flash
Performing Page Erase by SPM
Filling the Temporary Buffer (Page Loading)
Notes:
The program memory is updated in a page by page fashion. Before programming a page with
the data stored in the temporary page buffer, the page must be erased. The temporary page buf-
fer is filled one word at a time using SPM and the buffer can be filled either before the page
erase command or between a page erase and a page write operation:
Alternative 1, fill the buffer before a Page Erase
Alternative 2, fill the buffer after Page Erase
If only a part of the page needs to be changed, the rest of the page must be stored (for example
in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1,
the Boot Loader provides an effective Read-Modify-Write feature which allows the user software
to first read the page, do the necessary changes, and then write back the modified data. If alter-
native 2 is used, it is not possible to read the old data while loading since the page is already
erased. The temporary page buffer can be accessed in a random sequence. It is essential that
the page address used in both the page erase and page write operation is addressing the same
page. See
code example.
To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCR and
execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer must
be written zero during this operation.
Note:
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
“00000001” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The con-
tent of PCWORD in the Z-register is used to address the data in the temporary buffer. The
temporary buffer will auto-erase after a page write operation or by writing the RWWSRE bit in
SPMCR. It is also erased after a system reset. Note that it is not possible to write more than one
time to each address without erasing the temporary buffer.
Note:
• Fill temporary page buffer
• Perform a Page Erase
• Perform a Page Write
• Perform a Page Erase
• Fill temporary page buffer
• Perform a Page Write
• Page Erase to the RWW section: The NRWW section can be read during the page erase.
• Page Erase to the NRWW section: The CPU is halted during the operation.
1. The different variables used in
2. PCPAGE and PCWORD are listed in
If an iterrupt occurs in the timed sequence, the four cycle access cannot be guaranteed. In order
to ensure atomic operation disable interrupts before writing to SPMCSR.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be
lost.
“Simple Assembly Code Example for a Boot Loader” on page 261
Figure 25-3
“Page Size” on page
are listed in
Table 25-8 on page
269.
ATmega32A
263.
for an assembly
259