ATMEGA32A-PU Atmel, ATMEGA32A-PU Datasheet - Page 350

• Manufacturer Part Number: ATMEGA32A-PU
• Description: MCU AVR 32K FLASH 16MHZ 40-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Rom Size: 1024 B
• Height: 4.83 mm
• Length: 52.58 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 13.97 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8155C–AVR–02/11
23 JTAG Interface and On-chip Debug System ..................................... 228
24 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 234
25 Boot Loader Support – Read-While-Write Self-Programming ......... 253
22.5
22.6
22.7
22.8
22.9
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
23.9
23.10
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
25.9
Prescaling and Conversion Timing ................................................................212
Changing Channel or Reference Selection ...................................................215
ADC Noise Canceler .....................................................................................217
ADC Conversion Result .................................................................................222
Register Description ......................................................................................223
Features ........................................................................................................228
Overview ........................................................................................................228
TAP – Test Access Port ................................................................................228
TAP Controller ...............................................................................................230
Using the Boundary-scan Chain ....................................................................231
Using the On-chip Debug System .................................................................231
On-chip Debug Specific JTAG Instructions ...................................................232
Using the JTAG Programming Capabilities ...................................................233
Register Description ......................................................................................233
Bibliography ...................................................................................................233
Features ........................................................................................................234
Overview ........................................................................................................234
Data Registers ...............................................................................................234
Boundary-scan Specific JTAG Instructions ...................................................236
Boundary-scan Chain ....................................................................................237
ATmega32A Boundary-scan Order ...............................................................247
Boundary-scan Description Language Files ..................................................252
Register Description ......................................................................................252
Features ........................................................................................................253
Overview ........................................................................................................253
Application and Boot Loader Flash Sections .................................................253
Read-While-Write and no Read-While-Write Flash Sections ........................254
Boot Loader Lock Bits ...................................................................................256
Entering the Boot Loader Program ................................................................257
Addressing the Flash during Self-Programming ............................................258
Self-Programming the Flash ..........................................................................259
Register Description ......................................................................................265
ATmega32A
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