DSPIC30F3010-20I/SP Microchip Technology, DSPIC30F3010-20I/SP Datasheet

IC DSPIC MCU/DSP 24K 28DIP

DSPIC30F3010-20I/SP

Manufacturer Part Number
DSPIC30F3010-20I/SP
Description
IC DSPIC MCU/DSP 24K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3010-20I/SP

Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
20
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F301020ISP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F3010-20I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F3010/3011
Data Sheet
High-Performance,
16-Bit Digital Signal Controllers
© 2010 Microchip Technology Inc.
DS70141F

Related parts for DSPIC30F3010-20I/SP

DSPIC30F3010-20I/SP Summary of contents

Page 1

... Microchip Technology Inc. dsPIC30F3010/3011 High-Performance, 16-Bit Digital Signal Controllers Data Sheet DS70141F ...

Page 2

... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... Single-Cycle Hardware Fractional/ Integer Multiplier • All DSP Instructions Single Cycle • ±16-bit Single-Cycle Shift © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Peripheral Features: • High-Current Sink/Source I/O Pins: 25 mA/25 mA • Timer module with Programmable Prescaler: - Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules • ...

Page 4

... Selectable Power Management modes: - Sleep, Idle and Alternate Clock modes dsPIC30F Motor Control and Power Conversion Family Program SRAM Device Pins Mem. Bytes/ Bytes Instructions dsPIC30F3010 28 24K/8K 1024 dsPIC30F3011 40/44 24K/8K 1024 DS70141F-page 4 CMOS Technology: • Low-Power, High-Speed Flash Technology • ...

Page 5

... EMUC3/AN1/V REF AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 40-Pin PDIP EMUD3/AN0/V REF EMUC3/AN1/V AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 AN6/OCFA/RB6 OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 FLTA/INT0/RE8 EMUD2/OC2/IC2/INT2/RD1 © 2010 Microchip Technology Inc. dsPIC30F3010/3011 MCLR +/CN2/RB0 -/CN3/RB1 3 26 PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 6 23 PWM3L/RE4 ...

Page 6

... Pin Diagrams (Continued) (1) 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V DS70141F-page dsPIC30F3010 OSC2/CLKO/RC15 OSC1/CLKI AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 externally. SS © 2010 Microchip Technology Inc. ...

Page 7

... Pin Diagrams (Continued) 44-Pin TQFP PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 RF1 RF0 V V PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 © 2010 Microchip Technology Inc. dsPIC30F3010/3011 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 32 2 OSC2/CLKO/RC15 31 3 OSC1/CLKI dsPIC30F3011 6 AN8/RB8 AN7/RB7 26 8 AN6/OCFA/RB6 9 25 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 DS70141F-page 7 ...

Page 8

... Pin Diagrams (Continued) (1) 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V DS70141F-page RF1 5 29 RF0 6 dsPIC30F3011 OSC2/CLKO/RC15 OSC1/CLKI AN8/RB8 AN7/RB7 AN6/OCFA/RB6 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 externally ...

Page 9

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com © 2010 Microchip Technology Inc. dsPIC30F3010/3011 to receive the most current information on all of our products. DS70141F-page 9 ...

Page 10

... NOTES: DS70141F-page 10 © 2010 Microchip Technology Inc. ...

Page 11

... The devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture. Figure 1-2 illustrate device block diagrams for the dsPIC30F3011 and dsPIC30F3010 devices. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Manual” dsPIC30F Figure 1-1 and ...

Page 12

... FIGURE 1-1: dsPIC30F3011 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH PCL Program Counter Loop Stack Address Latch Control Control Logic Logic Program Memory (24 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch ...

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... FIGURE 1-2: dsPIC30F3010 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH PCL Program Counter Stack Loop Address Latch Control Control Logic Logic Program Memory (24 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch ...

Page 14

... Table 1-1 provides a brief description of the device I/O pinout and the functions that are multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. ...

Page 15

... Schmitt Trigger input with CMOS levels I = Input © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Description Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. In-Circuit Serial Programming data input/output pin. ...

Page 16

... Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-2: dsPIC30F3010 I/O PIN DESCRIPTIONS Pin Buffer Pin Name Type Type ...

Page 17

... TABLE 1-2: dsPIC30F3010 I/O PIN DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type OSC1 I ST/CMOS OSC2 I/O — PGD I/O ST PGC I ST RB0-RB5 I/O ST RC13-RC15 I/O ST RD0-RD1 I/O ST RE0-RE5, I/O ST RE8 RF2-RF3 I/O ST SCK1 I/O ST SDI1 I ST SDO1 O — SCL I/O ...

Page 18

... NOTES: DS70141F-page 18 © 2010 Microchip Technology Inc. ...

Page 19

... Moreover, only the lower 16 bits of each instruction word can be accessed using this method. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 • Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions. ...

Page 20

... Programmer’s Model The programmer’s model is shown in consists of 16x16-bit working registers (W0 through W15), 2x40-bit accumulators (ACCA and ACCB), STATUS Register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Coun- ter (PC) ...

Page 21

... DSP ACCA Accumulators ACCB PC22 TBLPAG Data Table Page Address PSVPAG OAB SAB DA SRH © 2010 Microchip Technology Inc. dsPIC30F3010/3011 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 0 Program Space Visibility Page Address ...

Page 22

... Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/ 16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. DIVF – 16/16 signed fractional divide 2. DIV.sd – ...

Page 23

... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2010 Microchip Technology Inc. dsPIC30F3010/3011 40-Bit Accumulator A 40-Bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-Bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill DS70141F-page 23 ...

Page 24

... MULTIPLIER The 17x17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value ...

Page 25

... If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 2.4.2.2 Accumulator ‘Write Back’ The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a ...

Page 26

... Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space may also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder ...

Page 27

... Reset - GOTO Instruction Reset - Target Address Interrupt Vector Table Manual” Alternate Vector Table Program Memory (8K instructions) Data EEPROM UNITID (32 instr.) Device Configuration PROGRAM SPACE MEMORY MAP FOR dsPIC30F3010/3011 000000 000002 000004 Vector Tables 00007E Reserved 000080 000084 0000FE 000100 User Flash ...

Page 28

... TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User User TBLRD/TBLWT (TBLPAG<7> Configuration TBLRD/TBLWT (TBLPAG<7> Program Space Visibility User FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Using Program 0 Counter Using 0 PSVPAG Reg Program Space ...

Page 29

... Program Memory ‘Phantom’ Byte (Read as ‘0’). © 2010 Microchip Technology Inc. dsPIC30F3010/3011 A set of table instructions are provided to move byte or word-sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the lsw of the program address; ...

Page 30

... FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MSB) PC Address 0x000000 00000000 0x000002 00000000 00000000 0x000004 0x000006 00000000 Program Memory ‘Phantom’ Byte (Read as ‘0’) 3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page ...

Page 31

... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Program Space 0x0000 (1) PSVPAG 0x00 8 ...

Page 32

... FIGURE 3-6: dsPIC30F3010/3011 DATA SPACE MEMORY MAP MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 1 Kbyte 0x09FF 0x0A01 SRAM Space 0x0BFF 0x0C01 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70141F-page 32 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 ...

Page 33

... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA Using any W © 2010 Microchip Technology Inc. dsPIC30F3010/3011 SFR SPACE UNUSED Y SPACE UNUSED UNUSED MAC Class Ops Read-Only Indirect EA Using W10, W11Indirect EA Using W8, W9 ...

Page 34

... DATA SPACES The X data space is used by all instructions and sup- ports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...

Page 35

... A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...

Page 36

TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 ...

Page 37

TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 ...

Page 38

... NOTES: DS70141F-page 38 © 2010 Microchip Technology Inc. ...

Page 39

... Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2010 Microchip Technology Inc. dsPIC30F3010/3011 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...

Page 40

... MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP Accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instruc- tions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode ...

Page 41

... Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2010 Microchip Technology Inc. dsPIC30F3010/3011 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register MODCON<15:0> contains enable flags, as well register field to specify the W address registers. The XWM and YWM fields select which registers will operate with Modulo Addressing ...

Page 42

... MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W regis- ter important to realize that the address boundar- ies check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decre- menting buffers) boundary addresses (not just equal to) ...

Page 43

... TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 512 256 128 © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Decimal XB<14:0> Bit-Reversed Address Modifier Value Bit-Reversed Address A0 Decimal 0x0100 0x0080 0x0040 ...

Page 44

... NOTES: DS70141F-page 44 © 2010 Microchip Technology Inc. ...

Page 45

... MCU and DSC Programmer’s Reference (DS70157). The dsPIC30F3010/3011 has 29 interrupt sources and 4 processor exceptions (traps), which must be arbitrated based on a priority scheme. The CPU is responsible for reading the Interrupt Vector Table (IVT) and transferring the address con- tained in the interrupt vector to the program counter ...

Page 46

... Interrupt Priority The user-assignable Interrupt Priority (IP<2:0>) bits for each individual interrupt source are located in the 3 LSbs of each nibble, within the IPCx register(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user ...

Page 47

... Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 5.3 Traps Traps can be considered as non-maskable interrupts, indicating a software or hardware error, which adhere to a predefined priority as shown in ...

Page 48

... Address Error Trap: This trap is initiated when any of the following circumstances occurs misaligned data word access is attempted data fetch from our unimplemented data memory location is attempted data access of an unimplemented program memory location is attempted instruction fetch from vector space is attempted. ...

Page 49

... ISR uses fast context saving. 5.7 External Interrupt Requests The dsPIC30F3010/3011 interrupt controller supports three external interrupt request signals, INT0-INT2. These inputs are edge sensitive; they require a low-to- high or a high-to-low transition to generate an interrupt request. The INTCON2 register has five bits, INT0EP- INT4EP, that select the polarity of the edge detection circuitry ...

Page 50

TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF ...

Page 51

... Addressing Using Table Instruction User/Configuration Space Select © 2010 Microchip Technology Inc. dsPIC30F3010/3011 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...

Page 52

... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instruc- tions or 96 bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program 32 instructions at one time. ...

Page 53

... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2010 Microchip Technology Inc. dsPIC30F3010/3011 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, program Flash, program and set WREN bit. ...

Page 54

... LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the Table Pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...

Page 55

TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — ...

Page 56

... NOTES: DS70141F-page 56 © 2010 Microchip Technology Inc. ...

Page 57

... NVMADRU register, is used to address the EEPROM location being accessed. TBLRDL and TBLWTL instruc- tions are used to read and write data EEPROM. The dsPIC30F3010/3011 devices have 1 Kbyte (512 words) of data EEPROM, with an address range from 0x7FFC00 to 0x7FFFFE. A word write operation should be preceded by an erase of the corresponding memory location(s) ...

Page 58

... Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in the NVMCON register ...

Page 59

... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2010 Microchip Technology Inc. dsPIC30F3010/3011 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...

Page 60

... WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 [ W0]++ TBLWTL W2 , MOV #data2,W2 ...

Page 61

... WR PORT Read LAT Read PORT © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins, and writes to the port pins, write the latch (LATx). Any bit and its associated data and control registers that are not valid for a particular device will be disabled ...

Page 62

... FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Peripheral Module Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module Read TRIS Data Bus WR TRIS TRIS Latch WR LAT + WR PORT Data Latch Read LAT Read PORT 8.2 ...

Page 63

TABLE 8-1: dsPIC30F3011 PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C6 — — — — PORTB 02C8 — — — — LATB 02CA — — — — TRISC 02CC TRISC15 TRISC14 TRISC13 ...

Page 64

... TABLE 8-2: dsPIC30F3010 PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C6 — — — — PORTB 02C8 — — — — LATB 02CB — — — — TRISC 02CC TRISC15 TRISC14 TRISC13 — PORTC 02CE RC15 RC14 RC13 — ...

Page 65

... CN7IE CN6IE CN5IE CNPU1 00C4 CN7PUE CN6PUE CN5PUE Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 for CN pin Bit 5 Bit 4 Bit 3 Bit 2 CN4IE CN3IE CN2IE CN4PUE CN3PUE CN2PUE CN1PUE ...

Page 66

... NOTES: DS70141F-page 66 © 2010 Microchip Technology Inc. ...

Page 67

... Interrupt on 16-bit Period register match or falling edge of external gate signal © 2010 Microchip Technology Inc. dsPIC30F3010/3011 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. presents a block diagram of the 16-bit timer module. 16-Bit Timer Mode: In the 16-Bit Timer mode, the ...

Page 68

... FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER) Equal Reset 0 T1IF Event Flag 1 TGATE SOSCO/ T1CK LPOSCEN SOSCI 9.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal T to increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit, TGATE (T1CON< ...

Page 69

... XTAL SOSCO pF 100K © 2010 Microchip Technology Inc. dsPIC30F3010/3011 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscillator output signal the value specified in the Period register, and is then reset to ‘0’. ...

Page 70

TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note ...

Page 71

... These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 For 32-bit timer/counter operation, Timer2 is the lsw and Timer3 is the msw of the 32-bit timer. Note: For 32-bit timer operation, T3CON control bits are ignored ...

Page 72

... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 Write TMR2 Read TMR2 16 Reset TMR3 MSB ADC Event Trigger Comparator x 32 Equal PR3 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer Configuration bit, T32 T2CON(<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register ...

Page 73

... Comparator x 16 Reset 0 T3IF Event Flag 1 TGATE Note: The dsPIC30F3010/3011 devices do not have external pin inputs to Timer3. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) © 2010 Microchip Technology Inc. dsPIC30F3010/3011 PR2 TMR2 ...

Page 74

... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal T to increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit, TGATE (T2CON<6>), must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...

Page 75

TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — Legend: u ...

Page 76

... NOTES: DS70141F-page 76 © 2010 Microchip Technology Inc. ...

Page 77

... Timer configuration bit, T32 T4CON(<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T4CON register. The dsPIC30F3010/3011 devices do not have external pin inputs to Timer4 or Timer5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) © ...

Page 78

... TIMER4 BLOCK DIAGRAM (TYPE B TIMER) Equal Comparator x 16 Reset 0 T4IF Event Flag 1 TGATE Note: The dsPIC30F3010/3011 devices do not have external pin inputs to Timer4 or Timer5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) DS70141F-page 78 PR4 TMR4 Q D TGATE ...

Page 79

... Reset 0 T5IF Event Flag 1 TGATE Note: The dsPIC30F3010/3011 devices do not have external pin inputs to Timer4 or Timer5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) © 2010 Microchip Technology Inc. dsPIC30F3010/3011 PR5 Comparator x 16 ...

Page 80

TABLE 11-1: TIMER4/5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON — TSIDL — T5CON 0120 TON — TSIDL — Legend: u ...

Page 81

... Interrupt on input capture event These operating modes are determined by setting the appropriate bits in the ICxCON register (where x = 1,2,...,N). Note: The dsPIC30F3010/3011 devices have four capture channels. The channels are designated IC1, IC2, IC7 and IC8 to maintain software compatibility with other dsPIC30F devices. ...

Page 82

... Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • Capture every falling edge • Capture every rising edge • Capture every 4th rising edge • Capture every 16th rising edge • Capture every rising and falling edge These simple Input Capture modes are configured by setting the appropriate bits, ICM< ...

Page 83

... If the input capture module is defined as ICM<2:0> = 111 in CPU Idle mode, the input capture pin will serve only as an external interrupt pin. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 12.3 Input Capture Interrupts The input capture channels have the ability to generate an interrupt based upon the selected number of capture events. The selection number is set by control bits, ICI< ...

Page 84

TABLE 12-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC7BUF 0158 IC7CON 015A — — ICSIDL ...

Page 85

... Interrupt on Output Compare/PWM Event These operating modes are determined by setting the appropriate bits in the 16-bit OCxCON SFR (where x = 1,2,3,...,N). The dsPIC30F3010/3011 devices have 4/2 compare channels, respectively. OCxRS and OCxR in the figure represent the Dual Compare registers. In the Dual Compare mode, the OCxR register is used for the first compare and OCxRS is used for the second compare ...

Page 86

... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers: Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the output compare module. 13.2 Simple Output Compare Match Mode When control bits, OCM< ...

Page 87

... T3IF = 1 (Interrupt Flag) OCxR = OCxRS TMR3 = Duty Cycle (OCxR) © 2010 Microchip Technology Inc. dsPIC30F3010/3011 When the selected TMRx is equal to its respective Period register, PRx, the following four events occur on the next increment cycle: • TMRx is cleared. • The OCx pin is set. ...

Page 88

... Output Compare Operation During CPU Sleep Mode When the CPU enters the Sleep mode, all internal clocks are stopped. Therefore, when the CPU enters the Sleep state, the output compare channel will drive the pin to the active state that was observed prior to entering the CPU Sleep state ...

Page 89

... OCSIDL — Legend: — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 2: These registers are not available on dsPIC30F3010 devices. (1) Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Output Compare 1 Secondary Register Output Compare 1 Main Register — ...

Page 90

... NOTES: DS70141F-page 90 © 2010 Microchip Technology Inc. ...

Page 91

... Programmable INDX Digital Filter 3 Note 1: In dsPIC30F3010/3011, the UPDN pin is not available. Up/Down logic bit can still be polled by software. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 The operational features of the QEI include: • Three input channels for two phase signals and index pulse • ...

Page 92

... Quadrature Encoder Interface Logic A typical incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship ...

Page 93

... To enable the filter output for channels, QEA, QEB and INDX, the QEOUT bit must be ‘1’. The filter network for all channels is disabled on POR and BOR. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 14.5 Alternate 16-Bit Timer/Counter When the QEI module is not configured for the QEI mode, QEIM< ...

Page 94

... QEI Module Operation During CPU Idle Mode Since the QEI module can function as a Quadrature Encoder Interface 16-bit timer, the following section describes operation of the module in both modes. 14.7.1 QEI OPERATION DURING CPU IDLE MODE When the CPU is placed in the Idle mode, the QEI ...

Page 95

TABLE 14-1: QEI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name QEICON 0122 CNTERR — QEISIDL INDX UPDN DFLTCON 0124 — — — — POSCNT 0126 MAXCNT 0128 ADPCFG 02A8 — — ...

Page 96

... NOTES: DS70141F-page 96 © 2010 Microchip Technology Inc. ...

Page 97

... The PWM module has the following features: • 6 PWM I/O pins with 3 duty cycle generators • 16-bit resolution © 2010 Microchip Technology Inc. dsPIC30F3010/3011 • ‘On-the-Fly’ PWM frequency changes • Edge and Center-Aligned Output modes • Single Pulse Generation mode • ...

Page 98

... FIGURE 15-1: PWM MODULE BLOCK DIAGRAM PWMCON1 PWMCON2 DTCON1 FLTACON OVDCON PTMR Comparator PTPER PTPER Buffer PTCON Comparator SEVTDIR SEVTCMP PWM Time Base Note: The details of PWM Generator 1 and 2 are not shown for clarity. DS70141F-page 98 PWM Enable and Mode SFRs ...

Page 99

... The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 15.1.1 FREE-RUNNING MODE In the Free-Running mode, the PWM time base counts upwards until the value in the Time Base Period register (PTPER) is matched ...

Page 100

... DOUBLE-UPDATE MODE In the Double-Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR regis- ter is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. The Double-Update mode provides two additional functions to the user ...

Page 101

... PWM period. In addition, the out- put on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to the value held in the PTPER register. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 FIGURE 15-3: CENTER-ALIGNED PWM Period/2 PTPER ...

Page 102

... When the PWM time base is in the Continuous Up/ Down Count mode with double updates, new duty cycle values are updated when the value of the PTMR regis- ter is zero, and when the value of the PTMR register matches the value in the PTPER register. The contents ...

Page 103

... PWM I/O pins are driven to the inactive state, the PTEN bit is cleared and an interrupt is generated. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Dead Time 15.10 PWM Output Override The PWM output override bits allow the user to manually drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units ...

Page 104

... PWM Output and Polarity Control There are three device Configuration bits associated with the PWM module that provide PWM output pin control: • HPOL Configuration bit • LPOL Configuration bit • PWMPIN Configuration bit These three bits in the FBORPOR Configuration register (see Section 20.6 “ ...

Page 105

... PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for a Continuous Up/Down Count mode. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 15.14.1 SPECIAL EVENT TRIGGER POSTSCALER The PWM Special Event Trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio. The postscaler is configured by writing the SEVOPS< ...

Page 106

TABLE 15-1: PWM REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PTCON 01C0 PTEN — PTSIDL — PTMR 01C2 PTDIR PTPER 01C4 — SEVTCMP 01C6 SEVTDIR PWMCON1 01C8 — — — — PWMCON2 01CA ...

Page 107

... If any trans- mit data has been written to the buffer register, the © 2010 Microchip Technology Inc. dsPIC30F3010/3011 contents of the transmit buffer are moved to SPI1SR. The received data is thus placed in SPI1BUF and the transmit data in SPI1SR is ready for the next transfer. ...

Page 108

... Framed SPI Support The module supports a basic framed SPI protocol in Master or Slave mode. The control bit, FRMEN, enables framed SPI support and causes the SS1 pin to perform the Frame Synchronization (F function. The control bit, SPIFSD, determines whether FIGURE 16-1: ...

Page 109

... Therefore, when the SS1 pin is asserted low again, transmission/reception will begin at the MSb, even if SS1 has been deasserted in the middle of a transmit/receive. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 16.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut down. If ...

Page 110

TABLE 16-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend: — = unimplemented bit, ...

Page 111

... Thus, the I C module can operate either as a slave master bus. FIGURE 17-1: PROGRAMMER’S MODEL bit 15 bit 15 © 2010 Microchip Technology Inc. dsPIC30F3010/3011 17.1.1 VARIOUS I The following types • Slave operation with 7-bit addressing 2 • Slave operation with 10-bit addressing 2 • ...

Page 112

... FIGURE 17-2: I C™ BLOCK DIAGRAM Shift SCL Clock SDA Match Detect Stop bit Detect Stop bit Generate Shift Clock DS70141F-page 112 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload ...

Page 113

... ACK received from the master. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 17.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL ...

Page 114

... MODE SLAVE TRANSMISSION Once a slave is addressed in this fashion, with the full 10-bit address (we will refer to this state as “PRIOR_ADDR_MATCH”), the master can begin sending data bytes for a slave reception operation. 17.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated ...

Page 115

... When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CRCV to determine if the address was device-specific general call address. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 2 17. Master Support As a master device, six operations are supported Slave • ...

Page 116

... I C MASTER RECEPTION Master mode reception is enabled by programming the Receive Enable (RCEN) bit (I2CCON<3>). The I module must be Idle before the RCEN bit is set; other- wise, the RCEN bit will be disregarded. The Baud Rate Generator begins counting, and on each rollover, the state of the SCL pin toggles, and data is shifted into the I2CRSR on the rising edge of each clock ...

Page 117

TABLE 17-2: I C™ REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — — — — I2CCON 0206 I2CEN ...

Page 118

... NOTES: DS70141F-page 118 © 2010 Microchip Technology Inc. ...

Page 119

... Internal Data Bus UTXBRK Data UxTX Parity Note dsPIC30F3010 only has UART1. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 18.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • ...

Page 120

... FIGURE 18-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic DS70141F-page 120 Internal Data Bus 16 Write Read UxRXREG Low Byte URX8 Receive Buffer Control – ...

Page 121

... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented 1). © 2010 Microchip Technology Inc. dsPIC30F3010/3011 18.3 Transmitting Data 18.3.1 TRANSMITTING IN 8-BIT DATA MODE ...

Page 122

... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding Interrupt Flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on the UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR) ...

Page 123

... No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not been received yet. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 18.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables the Address Detect mode, in which a 9th bit (URX8) value of ‘ ...

Page 124

... Auto Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a selected capture input. To enable this mode, the user must program the input capture module to detect the falling and rising edges of the Start bit. ...

Page 125

... WAKE LPBACK UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE — — — UTX8 — — — URX8 Baud Rate Generator Prescaler (NOT AVAILABLE ON dsPIC30F3010) Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 — — — WAKE LPBACK ABAUD TRMT URXISEL1 URXISEL0 ADDEN — — ...

Page 126

... NOTES: DS70141F-page 126 © 2010 Microchip Technology Inc. ...

Page 127

... REF REF being able to operate while the device is in Sleep mode. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 The ADC module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) • A/D Control Register 3 (ADCON3) • A/D Input Select register (ADCHS) • ...

Page 128

... AN5 AN8 AN0 AN1 AN2 AN3 AN3 AN4 AN4 AN5 AN5 (1) AN6 AN6 (1) AN7 AN7 AN8 (1) AN8 AN1 Note 1: Not available on dsPIC30F3010 devices. DS70141F-page 128 + CH1 ADC S/H - 10-Bit Result + CH2 S/H - 16-word, 10-bit Dual Port + CH3 S/H CH1,CH2, - CH3,CH0 Sample/Sequence ...

Page 129

... SIMSAM bit is not applicable. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 The CHPS bits select how many channels are sam- pled. This can vary from channels. If the CHPS bits select 1 channel, the CH0 channel will be sampled at the sample clock and converted ...

Page 130

... Programming the Start of Conversion Trigger The conversion trigger will terminate acquisition and start the requested conversions. The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for up to five alternate sources of conversion trigger. When SSRC<2:0> = 000, the conversion trigger is under software control ...

Page 131

... T 5.0 kΩ AD 300 ksps Note 1: External V - and V + pins must be used for correct operation. See Figure 19-2 for recommended REF REF circuit. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Table 19-1 Max V Temperature S DD 500Ω 4.5V -40°C to +85°C to 5.5V ANx 500Ω ...

Page 132

... The configuration guidelines give the required setup values for the conversion speeds above 500 ksps, since they require external V pins usage and there REF are some differences in the configuration procedure. Configuration details that are not critical to the conversion speed have been omitted. ...

Page 133

... ADCS<5:0> control bits in the ADCON3 register • Configure the sampling time writing: SAMC<4:0> = 00010 © 2010 Microchip Technology Inc. dsPIC30F3010/3011 19.7.3 600 ksps CONFIGURATION GUIDELINE The configuration for 600 ksps operation is dependent on whether a single input pin sampled or whether multiple pins will be sampled. ...

Page 134

... A/D Acquisition Requirements The analog input model of the 10-bit ADC is shown in Figure 19-3. The total sampling time for the ADC is a function of the internal amplifier settling time, device V and the holding capacitor charge time. DD For the ADC to meet its specified accuracy, the Charge ...

Page 135

... Integer 0 © 2010 Microchip Technology Inc. dsPIC30F3010/3011 If the ADC interrupt is enabled, the device will wake-up from Sleep. If the ADC interrupt is not enabled, the ADC module will then be turned off, although the ADON bit will remain set ...

Page 136

... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the ADC port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared ...

Page 137

... Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 2: These bits are not available on dsPIC30F3010 devices. Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 — — ...

Page 138

... NOTES: DS70141F-page 138 © 2010 Microchip Technology Inc. ...

Page 139

... In the Idle mode, the clock sources are still active, but the CPU is shut off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...

Page 140

... TABLE 20-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 MHz-10 MHz crystal on OSC1:OSC2. XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled. XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled. XT w/PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2, 16x PLL enabled ...

Page 141

... OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 TUN<3:0> 4 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2010 Microchip Technology Inc. dsPIC30F3010/3011 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Timer Clock ...

Page 142

... Oscillator Configurations 20.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<2:0> Configuration bits that select one of four oscillator groups, b) and FPR<4:0> Configuration bits that select one of 15 oscillator choices within the primary group. ...

Page 143

... RC oscillator (nominal 7.37 MHz). The user can tune the FRC oscillator within a range of +10.5% © 2010 Microchip Technology Inc. dsPIC30F3010/3011 (840 kHz) and -12% (960 kHz) in steps of 1.50% around the factory calibrated setting, as shown in Table 20-4 ...

Page 144

... If one of the above conditions is not true, the LPRC will shut-off after the PWRT expires. Note 1: OSC2 pin function is determined by the Primary Oscillator mode (FPR<3:0>). 2: OSC1 pin cannot be used as an I/O pin, even if the secondary oscillator or an internal clock source is selected at all times ...

Page 145

... Byte Write 0x78 to OSCCON high Byte Write 0x9A to OSCCON high : Byte Write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 DS70141F-page 145 ...

Page 146

... Reset The dsPIC30F3010/3011 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during normal operation) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Reset cause by trap lockup (TRAPR) h) Reset caused by illegal opcode using an ...

Page 147

... V DD MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset © 2010 Microchip Technology Inc. dsPIC30F3010/3011 T OST T PWRT T OST T PWRT T OST T PWRT ) DD ): CASE 1 DD ...

Page 148

... POR with Long Crystal Start-up Time (with FSCM Enabled) The oscillator start-up circuitry is not linked to the POR circuitry. Some crystal circuits (especially low- frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after the POR timer and the PWRT have expired: • ...

Page 149

... Trap Reset 0x000000 Illegal Operation Reset 0x000000 Legend unchanged unknown Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ...

Page 150

... Watchdog Timer (WDT) 20.4.1 WATCHDOG TIMER OPERATION The primary function of the Watchdog Timer (WDT reset the processor in the event of a software malfunction. The WDT is a free-running timer, which runs off an on-chip RC oscillator, requiring no external component. Therefore, the WDT timer will continue to operate even if the main processor clock (e ...

Page 151

... CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Any interrupt that is individually enabled (using the IE bit) and meets the prevailing priority level will be able to wake-up the processor. The processor will process the interrupt and branch to the ISR ...

Page 152

... In-Circuit Debugger ® When MPLAB ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This func- tion allows simple debugging functions when used with MPLAB IDE. When the device has this feature enabled, some of the resources are not available for general use ...

Page 153

TABLE 20-7: SYSTEM INTEGRATION REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name RCON 0740 TRAPR IOPUWR BGST — — OSCCON 0742 — — COSC<1:0> — OSCTUN 0744 — — — — — Legend: ...

Page 154

... NOTES: DS70141F-page 154 © 2010 Microchip Technology Inc. ...

Page 155

... The destination, which could either be the File register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modifier) or File register (specified by the value of ‘ ...

Page 156

... Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (uncondi- ...

Page 157

... Y data space Prefetch Address register for DSP instructions Wy ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space Prefetch Destination register for DSP instructions ∈ {W4..W7} Wyd © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Description DS70141F-page 157 ...

Page 158

... TABLE 21-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...

Page 159

... CPSLT CPSLT Wb CPSNE CPSNE Wb DAW DAW Wn © 2010 Microchip Technology Inc. dsPIC30F3010/3011 # of Description words Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws< ...

Page 160

... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 26 DEC DEC f DEC f,WREG DEC Ws,Wd 27 DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 29 DIV DIV.S Wm,Wn DIV.SD Wm,Wn DIV.U Wm,Wn DIV.UD Wm,Wn 30 DIVF DIVF Wm, #lit14,Expr DO Wn,Expr ...

Page 161

... RESET RESET 60 RETFIE RETFIE 61 RETLW RETLW #lit10,Wn 62 RETURN RETURN © 2010 Microchip Technology Inc. dsPIC30F3010/3011 # of Description words Move Move Move f to WREG Move 16-bit Literal to Wn Move 8-bit Literal to Wn Move Move Move WREG to f Move Double from W(ns):W( Move Double from Ws to W(nd + 1):W(nd) ...

Page 162

... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 63 RLC RLC f RLC f,WREG RLC Ws,Wd 64 RLNC RLNC f RLNC f,WREG RLNC Ws,Wd 65 RRC RRC f RRC f,WREG RRC Ws,Wd 66 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd 67 SAC SAC Acc,#Slit4,Wdo SAC ...

Page 163

... XOR XOR f XOR f,WREG XOR #lit10,Wn XOR Wb,Ws,Wd XOR Wb,#lit5, Ws,Wnd © 2010 Microchip Technology Inc. dsPIC30F3010/3011 # of Description words Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-Extend Status Flags cycle Affected ...

Page 164

... NOTES: DS70141F-page 164 © 2010 Microchip Technology Inc. ...

Page 165

... Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2010 Microchip Technology Inc. dsPIC30F3010/3011 22.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...

Page 166

... MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use ...

Page 167

... Microchip Technology Inc. dsPIC30F3010/3011 22.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- chip's most cost effective high-speed hardware ...

Page 168

... PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured ® Windows programming interface supports baseline (PIC10F, ...

Page 169

... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 (except V and MCLR) (Note 1) ..................................... -0. ....................................................................................................... 0V to +13.25V ) .......................................................................................................... ± ...

Page 170

... DC Characteristics TABLE 23-1: OPERATING MIPS VS. VOLTAGE V Range Temp Range DD 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C TABLE 23-2: THERMAL OPERATING CONDITIONS Rating dsPIC30F301X-30I Operating Junction Temperature Range ...

Page 171

... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: This is the limit to which V DD © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min Typ Max 2.5 — ...

Page 172

... TABLE 23-5: DC CHARACTERISTICS: OPERATING CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Operating Current ( DC31a 1.4 2.5 DC31b 1.4 2.5 DC31c 1.4 2.5 DC31e 3.0 4.5 DC31f 2.8 4.5 DC31g 2.8 4.5 DC30a 3.2 5.0 DC30b 3.3 5.0 DC30c 3.3 5.0 DC30e 6 ...

Page 173

... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with core off, clock on and all modules turned off. IDLE © 2010 Microchip Technology Inc. dsPIC30F3010/3011 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial ...

Page 174

... TABLE 23-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Power-Down Current ( DC60a 0.3 14.0 DC60b 1.0 27.0 DC60c 12.0 55.0 DC60e 0.5 20.0 DC60f 2.0 40.0 DC60g 17.0 90.0 DC61a 8.0 12.0 DC61b 8.0 12.0 DC61c 8.0 12.0 DC61e 14 ...

Page 175

... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min ...

Page 176

... TABLE 23-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Output Low Voltage OL DO10 I/O Ports DO16 OSC2/CLKO ( Oscillator mode) V Output High Voltage OH DO20 I/O Ports DO26 OSC2/CLKO ( Oscillator mode) Capacitive Loading Specs (2) on Output Pins DO50 C 2 OSC2/SOSC2 pin ...

Page 177

... EB DD Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...

Page 178

... AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 23-12: TEMPERATURE AND VOLTAGE SPECIFICATIONS – CHARACTERISTICS FIGURE 23-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 ...

Page 179

... Measurements are taken ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 T © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...

Page 180

... TABLE 23-14: PLL CLOCK TIMING SPECIFICATIONS (V AC CHARACTERISTICS Param Symbol Characteristic No. OS50 F PLL Input Frequency Range PLLI OS51 F On-Chip PLL Output SYS OS52 T PLL Start-up Time (lock time) LOC Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested ...

Page 181

... CY (1) (MHz) Mode EC 0.200 Note 1: Assumption: Oscillator Postscaler is divide Instruction Execution Cycle Time Instruction Execution Frequency: MIPS = (F © 2010 Microchip Technology Inc. dsPIC30F3010/3011 (3) (3) MIPS MIPS (2) (μsec) w/o PLL w PLL x4 20.0 0.05 — 1.0 1.0 4.0 0.4 2.5 10.0 0.16 6.25 — ...

Page 182

... TABLE 23-17: AC CHARACTERISTICS: INTERNAL FRC ACCURACY Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) (2) AC CHARACTERISTICS Operating temperature Param Characteristic No. Internal FRC Accuracy @ FRC Freq. = 7.37 MHz OS63 FRC Note 1: Frequency is calibrated to 7.37 MHz (±2%) at 25°C and 5V. TUN bits can be used to compensate for temperature drift ...

Page 183

... Measurements are taken in RC mode and EC mode where CLKO output These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 DI35 DI40 New Value DO31 DO32 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...

Page 184

... FIGURE 23-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 Oscillator Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-2 for load conditions. ...

Page 185

... Band Gap Start-up Time BGAP Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) Min ...

Page 186

... FIGURE 23-7: TIMER1 AND 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK TMRX Note: Refer to Figure 23-2 for load conditions. TABLE 23-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TA10 T H TxCK High Time TX TA11 T L TxCK Low Time TX TA15 T P TxCK Input Period Synchronous, ...

Page 187

... TxCK Low Time TC15 TtxP TxCK Input Period Synchronous, TC20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Min Typ Synchronous, 0 — ...

Page 188

... FIGURE 23-8: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS QEB POSCNT TABLE 23-25: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TQ10 TtQH TQCK High Time TQ11 TtQL TQCK Low Time TQ15 TtQP TQCP Input Period TQ20 T Delay from External TQCK Clock ...

Page 189

... TccF OCx Output Fall Time OC11 TccR OCx Output Rise Time Note 1: These parameters are characterized but not tested in manufacturing. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 IC10 IC11 IC15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature A -40° ...

Page 190

... FIGURE 23-11: OCx/PWM MODULE TIMING CHARACTERISTICS OCFA/OCFB OC15 OCx TABLE 23-28: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. OC15 T Fault Input to PWM I/O FD Change OC20 T Fault Input Pulse Width FLT Note 1: These parameters are characterized but not tested in manufacturing. ...

Page 191

... T FD I/O Change MP30 T Minimum Pulse Width FH Note 1: These parameters are characterized but not tested in manufacturing. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 MP30 MP11 MP10 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) Min ...

Page 192

... FIGURE 23-14: QEA/QEB INPUT CHARACTERISTICS QEA (input) QEB (input) QEB Internal TABLE 23-30: QUADRATURE DECODER TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TQ30 T L Quadrature Input Low Time QU TQ31 T H Quadrature Input High Time QU TQ35 T IN Quadrature Input Period QU TQ36 T P Quadrature Phase Period ...

Page 193

... Alignment of index pulses to QEA and QEB is shown for position counter reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB), but index pulse recognition occurs on falling edge. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 TQ50 TQ55 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...

Page 194

... FIGURE 23-16: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP35 SDOx SP31 SDIx MSb In SP40 SP41 Note: Refer to Figure 23-2 for load conditions. TABLE 23-32: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...

Page 195

... These parameters are characterized but not tested in manufacturing. 2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in master mode must not violate this specification. 3: Assumes 50 pF load on all SPI pins. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 SP10 SP21 SP35 SP20 LSb BIT14 - - - - - -1 ...

Page 196

... FIGURE 23-18: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SS X SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) SP35 SDO X SDI SDI X SP40 Note: Refer to Figure 23-2 for load conditions. DS70141F-page 196 SP70 SP72 SP73 SP73 SP72 MSb BIT14 - - - - - -1 SP30,SP31 MSb In BIT14 - - - -1 ...

Page 197

... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...

Page 198

... FIGURE 23-19: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SS X SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SP30,SP31 SDI SDI X MSb In SP41 SP40 Note: Refer to Figure 23-2 for load conditions. DS70141F-page 198 SP70 SP72 SP73 SP35 SP73 SP72 ...

Page 199

... The minimum clock period for SCx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) ...

Page 200

... FIGURE 23-20: I C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM30 SDA Start Condition Note: Refer to Figure 23-2 for load conditions. 2 FIGURE 23-21: I C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 ...

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