PIC18LF2420-I/ML Microchip Technology, PIC18LF2420-I/ML Datasheet
PIC18LF2420-I/ML
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... PIC18F2420/2520/4420/4520 Microcontrollers with 10-Bit A/D © 2008 Microchip Technology Inc. Data Sheet 28/40/44-Pin Enhanced Flash and nanoWatt Technology DS39631E ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F4420 16K 8192 PIC18F4520 32K 16384 © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Peripheral Highlights (Continued): • Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all 4 modes) and I Master and Slave modes • Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN/J2602 ...
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... RB7/KBI3/PGD RB6//KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 (1) RB3/AN9/CCP2 RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RB3/AN9/CCP2 (1) RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RC7/RX/DT RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 (1) RB3/AN9/CCP2 RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 © 2008 Microchip Technology Inc. ...
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... RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 (1) RB3/AN9/CCP2 44-pin QFN RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 Note 1: RB3 is the alternate pin for CCP2 multiplexing. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 RC0/T1OSO/T13CKI 2 OSC2/CLKO/RA6 31 3 OSC1/CLKI/RA7 PIC18F4420 PIC18F4520 RE2/CS/AN7 27 7 RE1/WR/AN6 26 8 RE0/RD/AN5 ...
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... Appendix C: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 396 Appendix D: Migration from High-End to Enhanced Devices............................................................................................................. 396 Index .................................................................................................................................................................................................. 397 The Microchip Web Site ..................................................................................................................................................................... 407 Customer Change Notification Service .............................................................................................................................................. 407 Customer Support .............................................................................................................................................................................. 407 Reader Response .............................................................................................................................................................................. 408 PIC18F2420/2520/4420/4520 Product Identification System ............................................................................................................ 409 DS39631E-page 4 © 2008 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 DS39631E-page 5 ...
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... PIC18F2420/2520/4420/4520 NOTES: DS39631E-page 6 © 2008 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F2420 • PIC18LF2420 • PIC18F2520 • PIC18LF2520 • PIC18F4420 • PIC18LF4420 • PIC18F4520 • PIC18LF4520 This family offers the advantages of all PIC18 microcontrollers – namely, high computational perfor- mance at an economical price – ...
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... Standard devices with Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2420), accommodate an operating V range of 4.2V to 5.5V. DD Low-voltage parts, designated by “LF” (such as PIC18LF2420), function over an extended V of 2.0V to 5.5V. © 2008 Microchip Technology Inc. for range DD ...
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... MCLR (optional), WDT Programmable High/Low-Voltage Detect Programmable Brown-out Reset Instruction Set 75 Instructions; 83 with Extended Instruction Set Enabled Packages 28-Pin SPDIP 28-Pin SOIC 28-Pin QFN © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 PIC18F2520 DC – 40 MHz 16384 32768 8192 16384 768 1536 256 256 ...
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... PORTA RA0/AN0 RA1/AN1 RA2/AN2/V -/CV REF REF RA3/AN3/V + REF RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT OSC2/CLKO (3) /RA6 OSC1/CLKI (3) /RA7 PORTB RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 (1) RB3/AN9/CCP2 RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 (1) RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTE (2) MCLR/V /RE3 PP © 2008 Microchip Technology Inc. ...
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... RE3 is only available when MCLR functionality is disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. 3: Refer to Section 2.0 “Oscillator Configurations” for additional information. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Data Bus<8> Data Latch 8 Data Memory ( 3 ...
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... Crystal Oscillator mode. O — mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2008 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Pin Buffer Type Type PORTA is a bidirectional I/O port ...
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... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2008 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Pin Buffer Type Type PORTC is a bidirectional I/O port ...
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... Crystal Oscillator mode. O — mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2008 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Pin Buffer Type Type PORTA is a bidirectional I/O port ...
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... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. 17 I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2008 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Pin Buffer Type Type PORTC is a bidirectional I/O port ...
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... Enhanced CCP1 output. 4 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O — Enhanced CCP1 output. 5 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O — Enhanced CCP1 output. CMOS = CMOS compatible input or output I = Input P = Power Description © 2008 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Pin Buffer Type Type PORTE is a bidirectional I/O port ...
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... PIC18F2420/2520/4420/4520 NOTES: DS39631E-page 22 © 2008 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a fre- Note: quency out of the crystal manufacturer’s specifications. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 FIGURE 2-1: (1) C1 (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... Clock from Ext. System EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) OSC2 Open EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX /4 OSC2/CLKO OSC EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX I/O (OSC2) RA6 © 2008 Microchip Technology Inc. ...
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... Recommended values: 3 kΩ ≤ R ≤ 100 kΩ EXT C > EXT © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator ...
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... Three compensation techniques are discussed in Section 2.6.5.1 EUSART”, Section 2.6.5.2 “Compensating with the Timers” and Section 2.6.5.3 “Compensating with the CCP Module in Capture Mode”, but other techniques may be used. or temperature changes, which can “Compensating with the © 2008 Microchip Technology Inc. ...
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... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 R/W-0 R/W-0 R/W-0 ...
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... OSCTUNE<7> LP, XT, HS, RC, EC Peripherals T1OSC Internal Oscillator CPU IDLEN Clock Control FOSC<3:0> OSCCON<1:0> Clock Source Option for Other Modules WDT, PWRT, FSCM and Two-Speed Start-up © 2008 Microchip Technology Inc. ...
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... INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed ...
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... Source selected by the INTSRC bit (OSCTUNE<7>), see text. 2: Default output frequency of INTOSC on Reset. 3: DS39631E-page 30 (1) R/W-0 R R-0 IRCF0 OSTS IOFS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Feedback inverter disabled at quiescent voltage level See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. Note: © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 not require a device clock source (i.e., MSSP slave, PSP, INTx pins and others). Peripherals that may add ...
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... PIC18F2420/2520/4420/4520 NOTES: DS39631E-page 32 © 2008 Microchip Technology Inc. ...
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... IDLEN reflects its value when the SLEEP instruction is executed. Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. 2: © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 3.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: • ...
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... Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. Advance Information © 2008 Microchip Technology Inc. ...
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... PRI_RUN RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 n-1 n ...
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... The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n (1) Clock Transition OSC (1) OST (1) T PLL 1 2 n-1 n Clock (2) Transition PC OSTS bit Set . OSC Advance Information © 2008 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘ ...
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... SEC_IDLE mode will not occur. If the is CSD Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD PC Advance Information © 2008 Microchip Technology Inc. ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON< ...
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... CSD LP, XT OST HSPLL OST EC CSD (2) INTOSC T CSD is the PLL lock-out timer (parameter F12 also rc Advance Information Clock Ready Status Bit (OSCCON) OSTS IOFS (3) (3) OSTS rc (1) (1) IOFS (3) (3) OSTS rc (1) (1) IOFS (3) (3) OSTS rc (1) (1) IOFS © 2008 Microchip Technology Inc. ...
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... Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1. ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39631E-page 42 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 FIGURE 4- ...
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... BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. and operates as previously © 2008 Microchip Technology Inc. ...
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... INTIO1, INTIO2 66 ms Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly differ- ent from other oscillator modes ...
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... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39631E-page PWRT T OST T PWRT T OST T PWRT T OST © 2008 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET T = 1024 clock cycles. Note: OST ≈ max. First three stages of the PWRT timer. T PLL © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 , V RISE > PWRT PWRT T OST T PWRT T ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register Program Counter POR 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ( STKPTR Register BOR STKFUL STKUNF © 2008 Microchip Technology Inc. ...
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... PORTA pins, they are disabled and read ‘0’. The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit (CONFIG3H<1>). When 6: PBADEN = 1, PCFG<2:0> = 000; when PBADEN = 0, PCFG<2:0> = 111. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... PORTA pins, they are disabled and read ‘0’. The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit (CONFIG3H<1>). When 6: PBADEN = 1, PCFG<2:0> = 000; when PBADEN = 0, PCFG<2:0> = 111. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... RETFIE,RETLW High-Priority Interrupt Vector Low-Priority Interrupt Vector On-Chip Program Memory PIC18F2420/4420 Read ‘0’ © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘ ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h Top-of-Stack 00010 000D58h 00001 00000 Stack Pointer STKPTR<4:0> 00010 © 2008 Microchip Technology Inc. ...
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... SP<4:0>: Stack Pointer Location bits Bit 7 and bit 6 are cleared by user software POR. Note 1: © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”. © 2008 Microchip Technology Inc. nn ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code 0006h is encoded in the program Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2008 Microchip Technology Inc. ...
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... SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 5.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When ‘a’ The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 7Fh 80h Access RAM High (SFRs) FFh © 2008 Microchip Technology Inc. ...
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... FFh = 1100 00h Bank 12 FFh = 1101 00h Bank 13 FFh 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Data Memory Map 000h Access RAM 07Fh 080h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR ...
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... This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. (2) From Opcode © 2008 Microchip Technology Inc. ...
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... Unimplemented registers are read as ‘0’. 2: This register is not available on 28-pin devices. 3: © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 The SFRs can be classified into two sets: those asso- ciated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral func- tions. The Reset and Interrupt registers are described in their respective chapters, while the ALU’ ...
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... N/A 49, 69 N/A 49, 69 N/A 49, 69 N/A 49, 69 N/A 49, 69 50, 69 ---- 0000 50, 69 xxxx xxxx 50, 59 ---- 0000 N/A 50, 69 N/A 50, 69 N/A 50, 69 N/A 50, 69 N/A 50, 69 50, 69 ---- 0000 50, 69 xxxx xxxx C 50, 67 ---x xxxx © 2008 Microchip Technology Inc. ...
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... The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is 4: read-only. RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. 5: When disabled, these bits read as ‘0’. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Bit 4 Bit 3 Bit 2 T0SE ...
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... RE0 (2) 52, 117 ---- xxxx RD0 52, 114 xxxx xxxx RC0 52, 111 xxxx xxxx RB0 52, 108 xxxx xxxx RA0 52, 105 xx0x 0000 © 2008 Microchip Technology Inc. ...
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... For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second 2: operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the bits in the STATUS register ...
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... Example 5-5. EXAMPLE 5-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h; NEXT CLRF POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H, 1; All done with ; Bank1? BRA NEXT ; NO, clear next CONTINUE ; YES, continue © 2008 Microchip Technology Inc. ...
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... In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “ ...
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... Figure 5-9. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 24.2.1 “Extended Instruction Syntax”. © 2008 Microchip Technology Inc. ...
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... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 000h 060h 080h Bank 0 100h Bank 1 ...
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... These instructions are executed as described in Section 24.2 “Extended Instruction Set”. Bank 0 Bank 0 Bank 1 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory 00h Bank 1 “Window” 5Fh Bank 0 7Fh 80h SFRs FFh Access Bank © 2008 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. The EEIF interrupt flag bit (PIR2<4>) is set Note: when the write is complete. It must be cleared in software. When set, Table Latch (8-bit) TABLAT © 2008 Microchip Technology Inc. ...
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... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error Note 1: condition. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 R/W-0 R/W-x R/W-0 ...
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... Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE READ – TBLPTR<21:0> TBLPTRL 0 © 2008 Microchip Technology Inc. ...
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... WORD_EVEN TBLRD*+ MOVFW TABLAT, W MOVF WORD_ODD © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts © 2008 Microchip Technology Inc. ...
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... EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 The long write is necessary for programming the inter- nal Flash. Instruction execution is halted while in a long write cycle ...
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... TBLWT holding register. ; loop until buffers are full © 2008 Microchip Technology Inc. ...
Page 83
... PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 ; point to Flash program memory ; access Flash program memory ; enable write to memory ; disable interrupts ; write 55h ...
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... PIC18F2420/2520/4420/4520 NOTES: DS39631E-page 82 © 2008 Microchip Technology Inc. ...
Page 85
... EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory ...
Page 86
... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error Note 1: condition. DS39631E-page 84 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/S-0 R/S bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 87
... EECON1, WR BSF INTCON, GIE BCF EECON1, WREN © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- cution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
Page 88
... Set for memory ; Set for Data EEPROM ; Disable interrupts ; Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Disable writes ; Enable interrupts © 2008 Microchip Technology Inc. ...
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... EEPGD CFGS IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE RBIE TMR0IF — FREE ...
Page 90
... PIC18F2420/2520/4420/4520 NOTES: DS39631E-page 88 © 2008 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 ...
Page 92
... WREG ; ADDWFC RES3 BTFSS ARG2H ARG2H:ARG2L neg? BRA SIGN_ARG1 ; no, check ARG1 MOVF ARG1L SUBWF RES2 ; MOVF ARG1H SUBWFB RES3 ; SIGN_ARG1 BTFSS ARG1H ARG1H:ARG1L neg? BRA CONT_CODE ; no, done MOVF ARG2L SUBWF RES2 ; MOVF ARG2H SUBWFB RES3 ; CONT_CODE : © 2008 Microchip Technology Inc ...
Page 93
... Individual interrupts can be disabled through their corresponding enable bits. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 94
... INT2IF INT2IE INT2IP IPEN IPEN PEIE/GIEL IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP © 2008 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIE ...
Page 95
... None of the RB<7:4> pins have changed state A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and Note 1: allow the bit to be cleared. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Interrupt flag bits are set when an interrupt Note: ...
Page 96
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39631E-page 94 R/W-1 U-0 R/W-1 INTEDG2 — TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-1 — RBIP bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding Note: enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 R/W-0 R/W-0 ...
Page 98
... R-0 R/W-0 R/W-0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 99
... A TMR1 register capture occurred (must be cleared in software TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 R/W-0 R/W-0 R/W-0 EEIF BCLIF HLVDIF U = Unimplemented bit, read as ‘ ...
Page 100
... Disables the TMR1 overflow interrupt This bit is unimplemented on 28-pin devices and will read as ‘0’. Note 1: DS39631E-page 98 R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 101
... Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 R/W-0 R/W-0 R/W-0 EEIE BCLIE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 ...
Page 102
... Low priority This bit is unimplemented on 28-pin devices and will read as ‘0’. Note 1: DS39631E-page 100 R/W-1 R/W-1 R/W-1 TXIP SSPIP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 R/W-1 R/W-1 R/W-1 EEIP BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 104
... The operation of the SBOREN bit and the Reset flag bits is discussed in more detail in Section 4.1 “RCON Register”. R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 9.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L regis- ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
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... PIC18F2420/2520/4420/4520 NOTES: DS39631E-page 104 © 2008 Microchip Technology Inc. ...
Page 107
... Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. ...
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... System cycle clock output (F modes. O DIG LATA<7> data output. Disabled in external oscillator modes. I TTL PORTA<7> data input. Disabled in external oscillator modes. I ANA Main oscillator input connection. I ANA Main clock input connection. Description /4) in RC, INTIO1 and EC Oscillator OSC © 2008 Microchip Technology Inc. ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator Note 1: configuration; otherwise, they are read as ‘0’. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Bit 5 Bit 4 ...
Page 110
... PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. RB3 can be configured by the Configuration bit, CCP2MX, as the alternate peripheral pin for the CCP2 module (CCP2MX = 0). © 2008 Microchip Technology Inc. ...
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... PBADEN is set and digital inputs when PBADEN is cleared. Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1. 2: All other pin functions are disabled when ICSP or ICD are enabled. 3: © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 I/O I/O Type ...
Page 112
... Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF — TMR0IP — INT2IE INT1IE — VCFG1 VCFG0 PCFG3 PCFG2 Reset Bit 1 Bit 0 Values on page RB1 RB0 INT0IF RBIF 49 — RBIP 49 INT2IF INT1IF 49 PCFG1 PCFG0 51 © 2008 Microchip Technology Inc. ...
Page 113
... TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for additional information. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 On a Power-on Reset, these pins are Note: configured as digital inputs ...
Page 114
... LATC<7> data output PORTC<7> data input Asynchronous serial receive data input (EUSART module). O DIG Synchronous serial data output (EUSART module); takes priority over port data Synchronous serial data input (EUSART module). User must configure as an input. Description © 2008 Microchip Technology Inc. ...
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... SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC PORTC Data Latch Register (Read and Write to Data Latch) TRISC PORTC Data Direction Register © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Reset ...
Page 116
... EXAMPLE 10-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs © 2008 Microchip Technology Inc. ...
Page 117
... P1D 0 DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer Don’t care Legend: (TRIS bit does not affect port direction or is overridden for this option). © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 I/O I/O Type O DIG LATD<0> data output. ...
Page 118
... These registers and/or bits are unimplemented on 28-oin devices. Note 1: DS39631E-page 116 Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 IBOV PSPMODE — TRISE2 DC1B1 DC1B0 CCP1M3 CCP1M2 Reset Bit 1 Bit 0 Values on page RD1 RD0 TRISE1 TRISE0 52 CCP1M1 CCP1M0 51 © 2008 Microchip Technology Inc. ...
Page 119
... The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register, read and write the latched output value for PORTE. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 The fourth pin of PORTE (MCLR/V only pin. Its operation is controlled by the MCLRE Con- figuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin ...
Page 120
... TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output DS39631E-page 118 R/W-0 U-0 R/W-1 — PSPMODE TRISE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TRISE1 TRISE0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 121
... Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). Note 1: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are 2: implemented only when PORTE is implemented (i.e., 40/44-pin devices). © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 I/O I/O Type ...
Page 122
... Set Interrupt Flag PSPIF (PIR1<7>) I/O pins have diode protection to V Note: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) One bit of PORTD D Q RDx pin CK TTL PORTE Pins Read RD TTL Chip Select CS TTL Write WR TTL and © 2008 Microchip Technology Inc. ...
Page 123
... INTCON GIE/GIEH PEIE/GIEL TMR0IF PIR1 PSPIF ADIF PIE1 PSPIE ADIE IPR1 PSPIP ADIP ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 124
... PIC18F2420/2520/4420/4520 NOTES: DS39631E-page 122 © 2008 Microchip Technology Inc. ...
Page 125
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
Page 126
... Sync with Internal TMR0L Clocks Delay There is a delay between OSC Set TMR0IF TMR0L on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2008 Microchip Technology Inc. ...
Page 127
... RA6 Legend: Shaded cells are not used by Timer0. PORTA<7:6> and their direction bits are individually configured as port pins based on various primary Note 1: oscillator modes. When disabled, these bits read as ‘0’. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
Page 128
... PIC18F2420/2520/4420/4520 NOTES: DS39631E-page 126 © 2008 Microchip Technology Inc. ...
Page 129
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 130
... Special Event Trigger Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2008 Microchip Technology Inc. ...
Page 131
... T1OSI XTAL 32.768 kHz T1OSO See the Notes with Table 12-1 for additional Note: information about capacitor selection. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 132
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. © 2008 Microchip Technology Inc. ...
Page 133
... CPFSGT hours RETURN CLRF hours RETURN © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 monitoring TMR1L within the interrupt routine until it increments, and then updating the TMR1H:TMR1L register pair while the clock is low, or one-half of the period of the clock source. Assuming that Timer1 is being used as a Real-Time Clock, the clock source is a 32.768 kHz crystal oscillator ...
Page 134
... DS39631E-page 132 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF RCIF TXIF SSPIF CCP1IF RCIE TXIE SSPIE CCP1IE RCIP TXIP SSPIP CCP1IP Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 TMR2IP TMR1IP TMR1CS TMR1ON 50 © 2008 Microchip Technology Inc. ...
Page 135
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options ...
Page 136
... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF SSPIF CCP1IF TXIE SSPIE CCP1IE TXIP SSPIP CCP1IP Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 TMR2IP TMR1IP © 2008 Microchip Technology Inc. ...
Page 137
... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...
Page 138
... Clear TMR3 TMR3L 8 1 Synchronize Detect 0 Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize Detect 0 Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR3H 8 8 Internal Data Bus © 2008 Microchip Technology Inc. ...
Page 139
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 140
... PIC18F2420/2520/4420/4520 NOTES: DS39631E-page 138 © 2008 Microchip Technology Inc. ...
Page 141
... I/O state) 1011 = Compare mode, trigger special event; reset timer; CCP2 match starts A/D conversion (CCPxIF bit is set) 11xx = PWM mode © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 The capture and compare operations described in this chapter apply to all standard and Enhanced CCP modules ...
Page 142
... Changing the pin assignment of CCP2 does not auto- matically change any requirements for configuring the port pin. Users must always verify that the appropriate TRIS register is configured correctly for CCP2 operation, regardless of where it is located. Interaction © 2008 Microchip Technology Inc. ...
Page 143
... CCP1CON<3:0> Q1:Q4 CCP2CON<3:0> CCP2 pin Prescaler ÷ © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 15.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false inter- rupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
Page 144
... Set CCP1IF Output Compare Logic Match 4 CCP1CON<3:0> 0 Special Event Trigger 1 (Timer1/Timer3 Reset, A/D Trigger) T3CCP2 Set CCP2IF Compare Output Match Logic 4 CCP2CON<3:0> Special Event Trigger mode CCP1 pin TRIS Output Enable CCP2 pin TRIS Output Enable © 2008 Microchip Technology Inc. ...
Page 145
... Capture/Compare/PWM Register 2 High Byte CCP2CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. These bits are unimplemented on 28-pin devices; always maintain these bits clear. Note 1: © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE ...
Page 146
... CCPRxH until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. • OSC (TMR2 Prescale Value) L:CCP CON<5:4>) • • (TMR2 Prescale Value) OSC © 2008 Microchip Technology Inc. ...
Page 147
... CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 16.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 EQUATION 15-3: PWM Resolution (max) If the PWM duty cycle value is longer than ...
Page 148
... CCP2M2 PSSAC1 PSSAC0 PSSBD1 (1) (1) (1) PDC5 PDC4 PDC3 PDC2 Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 49 PD POR BOR 48 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 TMR2IP TMR1IP CCP1M1 CCP1M0 CCP2M1 CCP2M0 51 (1) (1) PSSBD0 51 (1) (1) (1) PDC1 PDC0 51 © 2008 Microchip Technology Inc. ...
Page 149
... PWM mode, P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode, P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode, P1A, P1C active-low; P1B, P1D active-low © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 and automatic shutdown and restart. The enhanced features are discussed in detail in Section 16.4 “ ...
Page 150
... The latter is more generic and will work for either single or multi-output PWM. and Timer RC2 RD5 All 40/44-Pin Devices: CCP1 RD5/PSP5 P1A P1B P1A P1B and Section 15.3 “Compare or for PWM Operation” RD6 RD7 RD6/PSP6 RD7/PSP7 RD6/PSP6 RD7/PSP7 P1C P1D © 2008 Microchip Technology Inc. ...
Page 151
... CCP1 pin and latch D.C. PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register ...
Page 152
... The general relationship of the outputs in all configurations is summarized in Figure 16-2 and Figure 16-3. 9.77 kHz 39.06 kHz FFh FFh OSC log F PWM bits log(2) 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2008 Microchip Technology Inc. ...
Page 153
... OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Dead-band delay is programmed using the PWM1CON register (see Section 16.4.6 “Programmable Note 1: Dead-Band Delay”). © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 0 Duty Cycle Period (1) Delay Delay 0 Duty ...
Page 154
... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2008 Microchip Technology Inc. ...
Page 155
... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. Note © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The TRISC<2> and TRISD<7:5> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
Page 156
... Reduce PWM for a PWM period before bits changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. QC FET Driver FET Driver QD © 2008 Microchip Technology Inc. ...
Page 157
... Note 1: All signals are shown as active-high the turn-on delay of power switch, QC, and its driver the turn-off delay of power switch, QD, and its driver. OFF © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals ...
Page 158
... R/W-0 R/W-0 (1) (1) (1) PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ( cycles, between the scheduled and actual time for a PWM OSC OSC R/W-0 R/W-0 R/W-0 (1) (1) (1) PDC2 PDC1 PDC0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 159
... PSSBD<1:0>: Pins B and D Shutdown State Control bits 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Reserved on 28-pin devices; maintain these bits clear. Note 1: © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 R/W-0 R/W-0 R/W-0 ECCPAS0 PSSAC1 PSSAC0 U = Unimplemented bit, read as ‘ ...
Page 160
... PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Resumes ECCPASE Cleared by Firmware PWM Resumes © 2008 Microchip Technology Inc. ...
Page 161
... Wait until TMRx overflows (TMRxIF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 16.4.10 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change ...
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... Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 49 PD POR BOR 48 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 TMR2IP TMR1IP 52 TMR3IF CCP2IF 52 TMR3IE CCP2IE 52 TMR3IP CCP2IP TMR1CS TMR1ON TMR3CS TMR3ON CCP1M1 CCP1M0 51 (1) (1) PSSBD1 PSSBD0 51 (1) (1) (1) PDC2 PDC1 PDC0 51 © 2008 Microchip Technology Inc. ...
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... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four ...
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... SSPIF interrupt is set. During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-0 R bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by Note 1: writing to the SSPBUF register. When enabled, these pins must be properly configured as input or output. 2: Bit combinations not specifically listed here are either reserved or implemented © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 R/W-0 R/W-0 (2) (3) CKP ...
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... The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. The SSPBUF register cannot be used with Note: read-modify-write instructions such as BCF, BTFSC and COMF, etc. detect bit each © 2008 Microchip Technology Inc. ...
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... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
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... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 5 bit 4 bit 3 bit 2 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2008 Microchip Technology Inc. ...
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... SSPIF Interrupt Flag SSPSR to SSPBUF © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output ...
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... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39631E-page 168 bit 6 bit 5 bit 4 bit 3 bit 2 bit 6 bit 5 bit 4 bit 3 bit bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2008 Microchip Technology Inc. ...
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... Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary 2: oscillator modes. When disabled, these bits read as ‘0’. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 17.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer ...
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... SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. When the © 2008 Microchip Technology Inc. ...
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... This bit holds the R/W bit information following the last address match. This bit is only valid from the 2: address match to the next Start bit, Stop bit or not ACK bit. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. 3: © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 2 C™ MODE) R-0 ...
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... DS39631E-page 172 2 C™ MODE) R/W-0 R/W-0 (1) CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) /(4 * (SSPADD + 1)) OSC R/W-0 R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown 2 C conditions were not valid for a (2) © 2008 Microchip Technology Inc. ...
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... For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I Note 1: set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2: © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 2 C™ MODE) R/W-0 ...
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... Read the SSPBUF register (clears BF bit) and clear flag bit, SSPIF. 7. Receive Repeated Start condition. 8. Receive first (high) byte of address (bits, SSPIF and BF, are set). 9. Read the SSPBUF register (clears BF bit) and clear flag bit, SSPIF. © 2008 Microchip Technology Inc. ...
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... The clock must be released by setting bit, CKP (SSPCON<4>). See Section 17.4.4 “Clock Stretching” for more details. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 17.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
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... PIC18F2420/2520/4420/4520 2 FIGURE 17-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESSING) DS39631E-page 176 © 2008 Microchip Technology Inc. ...
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... FIGURE 17-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESSING) © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 DS39631E-page 177 ...
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... PIC18F2420/2520/4420/4520 2 FIGURE 17-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESSING) DS39631E-page 178 © 2008 Microchip Technology Inc. ...
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... FIGURE 17-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESSING) © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 DS39631E-page 179 ...
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... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-Bit Slave Transmit mode (see Figure 17-11). © 2008 Microchip Technology Inc. ...
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... SDA DX SCL CKP WR SSPCONx © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-12) ...
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... PIC18F2420/2520/4420/4520 2 FIGURE 17-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESSING) DS39631E-page 182 © 2008 Microchip Technology Inc. ...
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... FIGURE 17-14: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESSING) © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 DS39631E-page 183 ...
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... UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure 17-15). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Receiving Data ACK ‘0’ ‘1’ © 2008 Microchip Technology Inc. ...
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... Generate a Stop condition on SDA and SCL. FIGURE 17-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 The MSSP module, when configured in Note Master mode, does not allow queueing of events. For instance, the user is not ...
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... SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. © 2008 Microchip Technology Inc. ...
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... C interface does not conform to the 400 kHz I Note 1: 100 kHz) in all details, but may be used with care where higher rates are required by the application. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...
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... DX – 1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count 03h 02h © 2008 Microchip Technology Inc. ...
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... FIGURE 17-19: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 If, at the beginning of the Start condition, Note: the SDA and SCL pins are already sam- pled low during the Start condition, the ...
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... SSPCON2 is disabled until the Repeated Start condition is complete. S bit set by hardware SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG Write to SSPBUF occurs here T BRG Sr = Repeated Start 1st bit T BRG © 2008 Microchip Technology Inc. ...
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... SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 17.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...
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... PIC18F2420/2520/4420/4520 2 FIGURE 17-21 MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESSING) DS39631E-page 192 © 2008 Microchip Technology Inc. ...
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... FIGURE 17-22 MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESSING) © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 DS39631E-page 193 ...
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... SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup Stop condition later, the PEN bit is BRG WCOL Status Flag ACKEN automatically cleared Cleared in software BRG © 2008 Microchip Technology Inc. ...
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... FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 17.4.17 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘ ...
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... Repeated Start or Stop conditions. SEN cleared automatically because of bus collision. MSSP module reset into Idle state. SSPIF and BCLIF are cleared in software SSPIF and BCLIF are cleared in software © 2008 Microchip Technology Inc. ...
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... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 ...
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... Repeated Start condition is complete. Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. Cleared in software T T BRG BRG © 2008 Microchip Technology Inc. ‘0’ ‘0’ Interrupt cleared in software ‘0’ ...