DSPIC30F3011-30I/PT Microchip Technology, DSPIC30F3011-30I/PT Datasheet

IC DSPIC MCU/DSP 24K 44TQFP

DSPIC30F3011-30I/PT

Manufacturer Part Number
DSPIC30F3011-30I/PT
Description
IC DSPIC MCU/DSP 24K 44TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3011-30I/PT

Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
44-TQFP, 44-VQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Data Ram Size
1024 B
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011, DM300018
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F301130IPT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F3011-30I/PT
Manufacturer:
MICROCHIP
Quantity:
316
Part Number:
DSPIC30F3011-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F3011-30I/PT
Manufacturer:
MICROCHI
Quantity:
20 000
Part Number:
DSPIC30F3011-30I/PT
0
The dsPIC30F3010/3011 (Rev. A2) samples that you
have received were found to conform to the
specifications and functionality described in the
following documents:
• DS70157 – “dsPIC30F/33F Programmer’s
• DS70141 – “dsPIC30F3010/3011 Data Sheet”
• DS70046 – “dsPIC30F Family Reference Manual”
The exceptions to the specifications in the documents
listed above are described in this section. These
exceptions are described for the specific devices that
are listed below:
• dsPIC30F3010
• dsPIC30F3011
These devices may be identified by the following
message that appears in the MPLAB
Window under MPLAB IDE, when a “Reset and
Connect” operation is performed within MPLAB IDE:
Setting Vdd source to target
Target Device dsPIC30F3011 found,
revision = Rev 0x1002
...Reading ICD Product ID
Running ICD Self Test
...Passed
MPLAB ICD 2 Ready
The errata described in this section will be addressed
in
dsPIC30F3011 devices.
© 2008 Microchip Technology Inc.
Reference Manual”
future
revisions
dsPIC30F3010/3011 Rev. A2 Silicon Errata
of
dsPIC30F3010
®
ICD 2 Output
dsPIC30F3010/3011
and
Silicon Errata Summary
The following list summarizes the errata described in
this document:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Output Compare Module in PWM Mode
MAC Class Instructions with ±4 Address
Modification
Sequential MAC instructions, which prefetch data
from Y data space using ±4 address modification,
will cause an address error trap.
Decimal Adjust Instruction
The Decimal Adjust instruction, DAW.b, may
improperly clear the Carry bit, C (SR<0>).
PSV Operations Using SR
In certain instructions, fetching one of the
operands from program memory using Program
Space Visibility (PSV) will corrupt specific bits in
the STATUS Register, SR.
PSV Operations
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
Early Termination of Nested DO Loops
When using two DO loops in a nested fashion,
terminating the inner-level DO loop by setting the
EDT (CORCON<11>) bit will produce unexpected
results.
4x PLL Operation
The 4x PLL mode of operation may not function
correctly for certain input frequencies.
Sequential Interrupts
Sequential interrupts after modifying the CPU IPL,
interrupt IPL, interrupt enable or interrupt flag may
cause an address error trap.
DISI Instruction
The DISI instruction will not disable interrupts if a
DISI instruction is executed in the same
instruction
decrements to zero.
32 kHz Low-Power (LP) Oscillator
The LP oscillator does not function when the
device is placed in Sleep mode.
Output compare will produce a glitch when
loading 0% duty cycle in PWM mode. It will also
miss the next compare after the glitch.
cycle
that
the
DS80389B-page 1
DISI
counter

Related parts for DSPIC30F3011-30I/PT

DSPIC30F3011-30I/PT Summary of contents

Page 1

... These devices may be identified by the following message that appears in the MPLAB Window under MPLAB IDE, when a “Reset and Connect” operation is performed within MPLAB IDE: Setting Vdd source to target Target Device dsPIC30F3011 found, revision = Rev 0x1002 ...Reading ICD Product ID Running ICD Self Test ...Passed ...

Page 2

... The PLL LOCK Status bit (OSCCON<5>) can occasionally get cleared and generate an Oscillator Failure Trap even when the PLL is still locked and functioning correctly. The following sections describe the errata and work around to these errata, where they may apply. ® DSC , DD © 2008 Microchip Technology Inc. ...

Page 3

... Adding an accumulator write back (a dummy write back if needed) to either of the MAC class instructions not use the + = address modification not prefetch data from Y data space. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 2. Module: CPU – Instruction DAW.b The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR< ...

Page 4

... Result in W4 (3) SR<1:0> bits , Result in W2 (3) SR<1:0> bits (4) SR<15:10> bits CORRECT RESULTS ;Load PSVPAG register ;Enable PSV ;Set up W1 for ;indirect PSV access ;from 0x000200 ;works ok ;Load W2 with data ;from program memory ;Carry flag and W4 ;results are ok! © 2008 Microchip Technology Inc. ...

Page 5

... For details on the functionality of the EDT bit, see Section 2.9.2.4 “Early Termination of the DO Loop” in the “dsPIC30F Family Reference Manual” (DS70046). © 2008 Microchip Technology Inc. dsPIC30F3010/3011 6. Module: 4x PLL Operation When the 4x PLL mode of operation is selected, the specified input frequency range of 4-10 MHz is not fully supported ...

Page 6

... One may use a large DISI value and then set the DISICNT register to zero, as shown in Example 6. A macro may also be used to perform this task, as shown in Example 7. // protect CPU IPL modification // set CPU IPL remove DISI protection // safely modify the CPU IPL © 2008 Microchip Technology Inc. ...

Page 7

... Timer may be enabled prior to entering Sleep mode. When the Watchdog Timer expires, code execution will resume from the instruction immediately following the SLEEP instruction. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 10. Module: Output Compare in PWM Mode If the desired duty cycle is 0 (OCxRS = 0), the ...

Page 8

... Module: 8x PLL Mode POSRES bit If 8x PLL mode is used, the input frequency range is 5 MHz-10 MHz instead of 4 MHz-10 MHz. Work around None PLL is used, make sure the input crystal or clock frequency is 5 MHz or greater. © 2008 Microchip Technology Inc. ...

Page 9

... AD (1) 750 ksps Up to 153. 500 ksps Up to 256. 300 ksps Work around None. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 R Max V Temperature S DD 500Ω 4.5V to 5.5V -40°C to +85°C 5.0 kΩ 4.5V to 5.5V -40°C to +125°C 5.0 kΩ 3.0V to 5.5V -40° ...

Page 10

... POSCNT, the variable will toggle bit 15. Example 8 shows the code required for this global variable. // Instead of 0xFFFF // Clear QEI interrupt flag // x=2 for dsPIC30F // x=3 for dsPIC33F © 2008 Microchip Technology Inc. ...

Page 11

... For example, if the SDA and SCL pins are shared with the UART and SPI pins, and the UART has higher precedence on the port latch pin. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 18. Module 10-bit Addressing mode, some address matches don't set the RBF flag or load the receive register I2CxRCV, if the lower address byte matches the reserved addresses ...

Page 12

... If the D_A flag and the I2COV flag are both set, a valid data byte was received and a previous valid data byte was lost. It will be necessary to code for handling this overflow condition. © 2008 Microchip Technology Inc slave interrupt 2 C nodes. ...

Page 13

... CPU execution is halted (after a breakpoint is reached), PTMR will start counting PTDIR was zero. Work around None. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 25. Module: Timer When the timer is being operated in Asynchronous mode using the secondary oscillator (32.768 kHz) and the device is put into Sleep mode, a clock ...

Page 14

... APPENDIX A: REVISION HISTORY Revision A (8/2008) Original version of the document. Revision B (9/2008) Updated issue 26 (PLL Lock Status Bit). DS80389B-page 14 © 2008 Microchip Technology Inc. ...

Page 15

... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 16

... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. 01/02/08 ...

Related keywords