PIC24HJ64GP206-I/PT Microchip Technology, PIC24HJ64GP206-I/PT Datasheet

IC PIC MCU FLASH 32KX16 64TQFP

PIC24HJ64GP206-I/PT

Manufacturer Part Number
PIC24HJ64GP206-I/PT
Description
IC PIC MCU FLASH 32KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ64GP206-I/PT

Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN, I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
13
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 18 Channel
Controller Family/series
PIC24
No. Of I/o's
53
Ram Memory Size
8KB
Cpu Speed
40MIPS
No. Of Timers
13
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Height
1 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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PIC24HJXXXGPX06/X08/X10
Data Sheet
High-Performance,
16-Bit Microcontrollers
© 2007 Microchip Technology Inc.
DS70175F

Related parts for PIC24HJ64GP206-I/PT

PIC24HJ64GP206-I/PT Summary of contents

Page 1

... PIC24HJXXXGPX06/X08/X10 © 2007 Microchip Technology Inc. Data Sheet High-Performance, 16-Bit Microcontrollers DS70175F ...

Page 2

... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... Output pins can drive from 3.0V to 3.6V • All digital input pins are 5V tolerant • sink on all I/O pins © 2007 Microchip Technology Inc. On-Chip Flash and SRAM: • Flash program memory 256 Kbytes • Data SRAM Kbytes (includes 2 Kbytes ...

Page 4

... Fully static design • 3.3V (±10%) operating voltage • Industrial temperature • Low-power consumption Packaging: • 100-pin TQFP (14x14x1 mm and 12x12x1 mm) • 64-pin TQFP (10x10x1 mm) Note: See the device variant tables for exact peripheral features per device. © 2007 Microchip Technology Inc. ...

Page 5

... MCU embedded applications. The device names, pin counts, memory sizes and periph- eral availability of each family are listed below, followed by their pinout diagrams. PIC24H General Purpose Family Variants Program Device Pins Flash Memory (KB) PIC24HJ64GP206 64 64 PIC24HJ64GP210 100 64 PIC24HJ64GP506 64 64 PIC24HJ64GP510 ...

Page 6

... SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF Note: The PIC24HJ64GP206 device does not have the SCL2 and SDA2 pins. DS70175F-page 4 48 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 47 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 46 OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/U1CTS/INT2/RD9 42 IC1/INT1/RD8 PIC24HJ64GP206 OSC2/CLKO/RC15 PIC24HJ128GP206 39 OSC1/CLKIN/RC12 PIC24HJ256GP206 SCL1/RG2 36 SDA1/RG3 ...

Page 7

... AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 PIC24HJ128GP306 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 DS70175F-page 5 ...

Page 8

... AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF DS70175F-page 6 48 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 47 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 46 OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/U1CTS/INT2/RD9 42 IC1/INT1/RD8 41 V PIC24HJ64GP506 40 OSC2/CLKO/RC15 PIC24HJ128GP506 39 OSC1/CLKIN/RC12 SCL1/RG2 36 SDA1/RG3 35 U1RTS/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 U1TX/SDO1/RF3 SS DD © 2007 Microchip Technology Inc. ...

Page 9

... AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 20 AN5/CN7/RB5 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 PIC24HJ64GP210 PIC24HJ128GP210 PIC24HJ128GP310 PIC24HJ256GP210 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 IC4/RD11 71 70 IC3/RD10 IC2/RD9 69 IC1/RD8 68 INT4/RA15 67 INT3/RA14 OSC2/CLKO/RC15 63 OSC1/CLKIN/RC12 TDO/RA5 61 TDI/RA4 ...

Page 10

... AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 DS70175F-page 8 PIC24HJ64GP510 PIC24HJ128GP510 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 72 71 IC4/RD11 70 IC3/RD10 IC2/RD9 69 68 IC1/RD8 INT4/RA15 67 66 INT3/RA14 OSC2/CLKO/RC15 63 OSC1/CLKIN/RC12 TDO/RA5 61 TDI/RA4 60 59 SDA2/RA3 58 SCL2/RA2 SCL1/RG2 57 SDA1/RG3 56 55 SCK1/INT0/RF6 54 SDI1/RF7 SDO1/RF8 53 52 U1RX/RF2 51 U1TX/RF3 © 2007 Microchip Technology Inc. ...

Page 11

... AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 PIC24HJ256GP610 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 72 71 IC4/RD11 70 IC3/RD10 69 IC2/RD9 68 IC1/RD8 INT4/RA15 67 66 INT3/RA14 OSC2/CLKO/RC15 63 OSC1/CLKIN/RC12 TDO/RA5 60 TDI/RA4 SDA2/RA3 59 SCL2/RA2 ...

Page 12

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70175F-page 10 © 2007 Microchip Technology Inc. ...

Page 13

... Microchip (www.microchip.com) for PIC24H Family Reference sections. This document contains device specific information for the following devices: • PIC24HJ64GP206 • PIC24HJ64GP210 • PIC24HJ64GP506 • PIC24HJ64GP510 • PIC24HJ128GP206 • PIC24HJ128GP210 • PIC24HJ128GP506 • PIC24HJ128GP510 • PIC24HJ128GP306 • PIC24HJ128GP310 • PIC24HJ256GP206 • PIC24HJ256GP210 • ...

Page 14

... Latch Control Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support 16-bit ALU MCLR ECAN1,2 UART1,2 CN1-23 SPI1,2 I2C1,2 PORTA DMA RAM PORTB DMA 16 Controller PORTC PORTD 16 PORTE 16 16 PORTF 16 PORTG © 2007 Microchip Technology Inc. ...

Page 15

... RG12-RG15 I/O ST Legend: CMOS = CMOS compatible input or output; Analog = Analog input ST = Schmitt Trigger input with CMOS levels Output Input Power © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Description Analog input channels. Positive supply for analog modules. Ground reference for analog modules. External clock source input. Always associated with OSC1 pin function. ...

Page 16

... UART2 ready to send. UART2 receive. UART2 transmit. Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. © 2007 Microchip Technology Inc. ...

Page 17

... A block diagram of the CPU is shown in Figure 2-1, and the programmer’s model PIC24HJXXXGPX06/X08/X10 is shown in Figure 2-2. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 2.1 Data Addressing Overview The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU). ...

Page 18

... DS70175F-page 16 X Data Bus Data Latch PCH PCL X RAM Address Loop Control Latch Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support DMA 16 RAM DMA Controller 16-bit ALU 16 To Peripheral Modules © 2007 Microchip Technology Inc. ...

Page 19

... FIGURE 2-2: PIC24HJXXXGPX06/X08/X10 PROGRAMMER’S MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer SPLIM PC0 0 Program Space Visibility Page Address ...

Page 20

... The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70175F-page 18 U-0 U-0 — — (2) R-0 R/W-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (2) U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W bit 0 © 2007 Microchip Technology Inc. ...

Page 21

... Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 DS70175F-page 19 ...

Page 22

... Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70175F-page 20 U-0 U-0 U-0 — — — U-0 R/C-0 R/W-0 (1) — IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 U-0 — — bit 0 ‘1’ = Bit is set ...

Page 23

... The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 2.4.3 MULTI-BIT DATA SHIFTER The multi-bit data shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...

Page 24

... PIC24HJXXXGPX06/X08/X10 NOTES: DS70175F-page 22 © 2007 Microchip Technology Inc. ...

Page 25

... The PIC24HJXXXGPX06/X08/X10 architecture fea- tures separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 3.1 Program Address Space The program PIC24HJXXXGPX06/X08/X10 devices is 4M instructions ...

Page 26

... Reserved Reserved Device Configuration Device Configuration Registers Registers Reserved Reserved DEVID (2) DEVID (2) 0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 0x00ABFE 0x00AC00 0x0157FE 0x015800 0x02ABFE 0x02AC00 0x7FFFFE 0x800000 0xF7FFFE 0xF80000 0xF80017 0xF80010 0xFEFFFE 0xFF0000 0xFFFFFE © 2007 Microchip Technology Inc. ...

Page 27

... Program Memory ‘Phantom’ Byte (read as ‘0’) © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 3.1.2 INTERRUPT AND TRAP VECTORS All PIC24HJXXXGPX06/X08/X10 devices reserve the addresses between 0x00000 and 0x000200 for hard- coded program execution vectors. A hardware Reset ...

Page 28

... Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field using Indirect Addressing mode using a working register as an Address Pointer. © 2007 Microchip Technology Inc. are used by the ...

Page 29

... SFR Space 0x07FF 0x0801 8 Kbyte SRAM Space 0x1FFF 0x2001 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x1FFE 0x2000 DMA RAM 0x27FE 0x2800 ...

Page 30

... DMA RAM location. Therefore, the DMA RAM provides a reliable means of transferring DMA data without ever having to stall the CPU. Note: DMA RAM can be used for general purpose data storage if the DMA function is not required in an application. 8 Kbyte Near Data Space © 2007 Microchip Technology Inc. ...

Page 31

TABLE 3-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...

Page 32

TABLE 3-3: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr — — — INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF ...

Page 33

TABLE 3-4: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...

Page 34

TABLE 3-5: INPUT CAPTURE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ...

Page 35

TABLE 3-6: OUTPUT COMPARE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C ...

Page 36

TABLE 3-7: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — I2C1TRN 0202 — — — I2C1BRG 0204 — — — I2C1ON 0206 I2CEN — I2CSIDL SCLREL I2C1STAT 0208 ...

Page 37

TABLE 3-10: UART2 REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr U2MODE 0230 UARTEN — USIDL IREN U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — U2TXREG 0234 — — — — U2RXREG 0236 — — — ...

Page 38

TABLE 3-13: ADC1 REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 AD1CON1 0320 ADON — ADSIDL ADDMAB AD1CON2 0322 VCFG<2:0> — AD1CON3 0324 ADRC — — AD1CHS123 0326 — — — — AD1CHS0 ...

Page 39

TABLE 3-15: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE — — — DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A — — — — ...

Page 40

TABLE 3-15: DMA REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA5PAD 03C4 DMA5CNT 03C6 — — — — DMA6CON 03C8 CHEN SIZE DIR HALF DMA6REQ 03CA FORCE — — — DMA6STA 03CC DMA6STB ...

Page 41

TABLE 3-17: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0400- 041E C1RXFUL1 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 C1RXFUL2 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 ...

Page 42

TABLE 3-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF1EID 0446 EID<15:8> C1RXF2SID 0448 SID<10:3> C1RXF2EID 044A EID<15:8> C1RXF3SID 044C SID<10:3> C1RXF3EID 044E EID<15:8> C1RXF4SID 0450 SID<10:3> C1RXF4EID ...

Page 43

TABLE 3-19: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = File Name Addr Bit 15 Bit 14 Bit 13 C2CTRL1 0500 — — CSIDL C2CTRL2 0502 — — — C2VEC 0504 — — — C2FCTRL 0506 DMABS<2:0> C2FIFO 0508 ...

Page 44

TABLE 3-21: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0500- 051E C2BUFPNT1 0520 F3BP<3:0> C2BUFPNT2 0522 F7BP<3:0> C2BUFPNT3 0524 F12BP<3:0> C2BUFPNT4 0526 F15BP<3:0> C2RXM0SID 0530 C2RXM0EID 0532 C2RXM1SID 0534 ...

Page 45

TABLE 3-21: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C2RXF11EID 056E C2RXF12SID 0570 C2RXF12EID 0572 C2RXF13SID 0574 C2RXF13EID 0576 C2RXF14SID 0578 C2RXF14EID 057A C2RXF15SID 057C C2RXF15EID 057E Legend: ...

Page 46

TABLE 3-22: PORTA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISA 02C0 TRISA15 TRISA14 TRISA13 TRISA12 PORTA 02C2 RA15 RA14 RA13 RA12 LATA 02C4 LATA15 LATA14 LATA13 LATA12 (2) ODCA 06C0 ODCA15 ODCA14 ...

Page 47

TABLE 3-26: PORTE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISE 02D8 — — — — PORTE 02DA — — — — LATE 02DC — — — — Legend unknown value ...

Page 48

TABLE 3-29: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> PLLFBD 0746 — — — — OSCTUN 0748 — ...

Page 49

... PC<22:16> 000000000 <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 3.2.7 DATA RAM PROTECTION FEATURE The PIC24H product family supports Data RAM protec- tion features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security ...

Page 50

... This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> the configuration memory (TBLPAG<7> = 1). normal execution, the © 2007 Microchip Technology Inc. ...

Page 51

... Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Table 3-33 and Figure 3-6 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P< ...

Page 52

... Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS70175F-page 50 Program Counter 0 23 bits 1/0 TBLPAG 8 bits 24 bits Select 1 0 PSVPAG 8 bits 23 bits 0 EA 1/0 16 bits bits Byte Select © 2007 Microchip Technology Inc. ...

Page 53

... FIGURE 3-7: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’. ...

Page 54

... PSV Area 0x800000 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2007 Microchip Technology Inc. ...

Page 55

... Program Counter Using 1/0 Table Instruction User/Configuration Space Select © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user can write program memory data either in blocks or ‘ ...

Page 56

... Flash in RTSP mode. A programming operation is nominally duration and the processor stalls (waits) until the oper- ation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. required for © 2007 Microchip Technology Inc. ...

Page 57

... Memory page erase operation (ERASE = operation (ERASE = 0) 0001 = Memory row program operation (ERASE = operation (ERASE = 1) 0000 = Program or erase a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 (1) U-0 U-0 — — ...

Page 58

... Initialize in-page EA<15:0> pointer ; Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2007 Microchip Technology Inc. ...

Page 59

... MOV #0x55, W0 MOV W0, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 ; ; Initialize NVMCON ; ; Initialize PM Page Boundary SFR ; An example program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ; Write PM low word into program latch ...

Page 60

... PIC24HJXXXGPX06/X08/X10 NOTES: DS70175F-page 58 © 2007 Microchip Technology Inc. ...

Page 61

... Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Note: Refer to the specific peripheral or CPU section of this manual for register Reset states ...

Page 62

... PIC24HJXXXGPX06/X08/X10 FIGURE 5-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction MCLR WDT Module Sleep or Idle Internal Regulator V DD Trap Conflict Illegal Opcode Uninitialized W Register DS70175F-page 60 Glitch Filter BOR POR V Rise DD Detect SYSRST © 2007 Microchip Technology Inc. ...

Page 63

... All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 (1) U-0 U-0 U-0 — ...

Page 64

... All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70175F-page 62 (1) © 2007 Microchip Technology Inc. ...

Page 65

... Clock Source Determinant POR Oscillator Configuration bits (FNOSC<2:0>) BOR MCLR COSC Control bits (OSCCON<14:12>) WDTR SWR © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Setting Event Trap conflict event Illegal opcode or uninitialized W register access MCLR Reset RESET instruction WDT time-out PWRSAV #SLEEP instruction ...

Page 66

... Oscillator Control register, OSCCON, depends on the type of Reset and the programmed values of the oscillator Configuration bits in the FOSC Configuration register. FSCM Notes Delay — FSCM FSCM LOCK FSCM — 3 — 3 — 3 — 3 — 3 — auto- FSCM © 2007 Microchip Technology Inc. ...

Page 67

... PIC24HJXXXGPX06/X08/X10 devices implement unique interrupts and 5 nonmaskable traps. These are summarized in Table 6-1 and Table 6-2. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 6.1.1 ALTERNATE VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1 ...

Page 68

... Note 1: See Table 6-1 for the list of implemented interrupt vectors. DS70175F-page 66 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 (1) (1) © 2007 Microchip Technology Inc. ...

Page 69

... Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 AIVT Address 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C DMA0 – DMA Channel 0 0x00011E IC2 – ...

Page 70

... AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error DMA Error Trap Reserved Reserved © 2007 Microchip Technology Inc. ...

Page 71

... The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...

Page 72

... IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit 0 U-0 U-0 U-0 — — — bit 8 R/W-0 U-0 U-0 PSV — — bit 0 ‘1’ = Bit is set © 2007 Microchip Technology Inc. ...

Page 73

... Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — — — ...

Page 74

... Interrupt on positive edge DS70175F-page 72 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 INT4EP INT3EP INT2EP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 INT1EP INT0EP bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 75

... DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF ...

Page 76

... Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70175F-page 74 © 2007 Microchip Technology Inc. ...

Page 77

... AD2IF: ADC2 Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 T5IF T4IF ...

Page 78

... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70175F-page 76 © 2007 Microchip Technology Inc. ...

Page 79

... DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 C1IF: ECAN1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 OC8IF OC7IF ...

Page 80

... Interrupt request has not occurred bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70175F-page 78 © 2007 Microchip Technology Inc. ...

Page 81

... SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 T7IF: Timer7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — — ...

Page 82

... Unimplemented: Read as ‘0’ DS70175F-page 80 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-0 DMA6IF — U2EIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 U-0 U1EIF — bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 83

... DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE ...

Page 84

... Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70175F-page 82 © 2007 Microchip Technology Inc. ...

Page 85

... AD2IE: ADC2 Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 ...

Page 86

... Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70175F-page 84 © 2007 Microchip Technology Inc. ...

Page 87

... DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 C1IE: ECAN1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 OC8IE OC7IE ...

Page 88

... Interrupt request enabled 0 = Interrupt request not enabled bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70175F-page 86 © 2007 Microchip Technology Inc. ...

Page 89

... SI2C2IE: I2C2 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 T7IE: Timer7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — — — R/W-0 ...

Page 90

... Unimplemented: Read as ‘0’ DS70175F-page 88 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-0 DMA6IE — U2EIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 U-0 U1EIE — bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 91

... Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 92

... Interrupt is priority 1 000 = Interrupt source is disabled DS70175F-page 90 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC2IP<2:0> bit 8 R/W-0 R/W-0 DMA0IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 93

... Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 94

... Interrupt is priority 1 000 = Interrupt source is disabled DS70175F-page 92 U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 DMA1IP<2:0> bit 8 R/W-0 R/W-0 U1TXIP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 95

... Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — ...

Page 96

... Interrupt is priority 1 000 = Interrupt source is disabled DS70175F-page 94 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC7IP<2:0> bit 8 R/W-0 R/W-0 INT1IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 97

... Unimplemented: Read as ‘0’ bit 2-0 DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 98

... Interrupt is priority 1 000 = Interrupt source is disabled DS70175F-page 96 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2RXIP<2:0> bit 8 R/W-0 R/W-0 T5IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 99

... Unimplemented: Read as ‘0’ bit 2-0 SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 100

... Interrupt is priority 1 000 = Interrupt source is disabled DS70175F-page 98 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC4IP<2:0> bit 8 R/W-0 R/W-0 DMA3IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 101

... Unimplemented: Read as ‘0’ bit 2-0 IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 102

... Interrupt is priority 1 000 = Interrupt source is disabled DS70175F-page 100 R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 DMA4IP<2:0> bit 8 R/W-0 R/W-0 OC8IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 103

... Unimplemented: Read as ‘0’ bit 2-0 T7IP<2:0>: Timer7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 104

... Interrupt is priority 1 000 = Interrupt source is disabled DS70175F-page 102 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 INT4IP<2:0> bit 8 R/W-0 R/W-0 T9IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 105

... Unimplemented: Read as ‘0’ bit 2-0 C2IP<2:0>: ECAN2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — — — U-0 ...

Page 106

... Unimplemented: Read as ‘0’ DS70175F-page 104 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 107

... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — ...

Page 108

... Interrupt is priority 1 000 = Interrupt source is disabled DS70175F-page 106 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 C1TXIP<2:0> bit 8 R/W-0 R/W-0 DMA6IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 109

... Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 1111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 R-0 R-0 — R-0 R-0 R-0 VECNUM< ...

Page 110

... Note that only user interrupts with a priority level less can be disabled. Trap sources (level 8-level 15) cannot be disabled. The DISI instruction provides a convenient way to dis- able interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. © 2007 Microchip Technology Inc. ...

Page 111

... ADC1 ADC2 ECAN1 Reception ECAN1 Transmission ECAN2 Reception ECAN2 Transmission © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 The DMA controller features eight identical data transfer channels. Each channel has its own set of control and status registers. Each DMA channel can be configured to group ...

Page 112

... An additional pair of status registers, DMACS0 and DMACS1 are common to all DMAC channels. DS70175F-page 110 Peripheral Indirect Address DMA Controller DMA Channels DMA DS Bus DMA Ready Peripheral 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1 © 2007 Microchip Technology Inc. ...

Page 113

... MODE<1:0>: DMA Channel Operating Mode Select bits 11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer Continuous, Ping-Pong modes enabled 01 = One-Shot, Ping-Pong modes disabled 00 = Continuous, Ping-Pong modes disabled © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 U-0 HALF NULLW — ...

Page 114

... U-0 U-0 U-0 — — R/W-0 U-0 U-0 (2) (2) (2) IRQSEL4 IRQSEL3 IRQSEL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) U-0 U-0 — — — bit 8 R/W-0 R/W-0 (2) (2) (2) IRQSEL1 IRQSEL0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 115

... R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 STB<15:0>: Secondary DMA RAM Start Address bits (source or destination) © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 STA<15:8> R/W-0 R/W-0 R/W-0 STA<7:0> Unimplemented bit, read as ‘0’ ...

Page 116

... U-0 U-0 — — — R/W-0 R/W-0 R/W-0 CNT<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 (2) CNT<9:8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 117

... XWCOL5: Channel 5 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 4 XWCOL4: Channel 4 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/C-0 R/C-0 R/C-0 PWCOL4 PWCOL3 PWCOL2 ...

Page 118

... Write collision detected write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected DS70175F-page 116 © 2007 Microchip Technology Inc. ...

Page 119

... PPST1: Channel 1 Ping-Pong Mode Status Flag bit 1 = DMA1STB register selected 0 = DMA1STA register selected bit 0 PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 = DMA0STB register selected 0 = DMA0STA register selected © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 R-1 R-1 — R-0 R-0 R-0 ...

Page 120

... DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits DS70175F-page 118 R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...

Page 121

... Secondary Oscillator SOSCO LPOSCEN SOSCI Note 1: See Figure 8-2 for PLL details © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 • An on-chip PLL to scale the internal operating frequency to the required system clock frequency • The internal FRC oscillator can also be used with the PLL, thereby allowing full-speed operation without any external clock generation hardware • ...

Page 122

... MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. For a primary oscillator or FRC oscillator, output ‘F the PLL output ‘F ’ is given by: OSC EQUATION 8-2: F OSC OSC IN © 2007 Microchip Technology Inc. is divided OSC ). are supported by the /2 OSC ’, IN CALCULATION ...

Page 123

... Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 EQUATION 8-3: F OSC ...

Page 124

... Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete DS70175F-page 122 R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R/W-y R/W-y NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...

Page 125

... PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 00000 = Input/2 (default) 00001 = Input/3 • • • 11111 = Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-1 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE< ...

Page 126

... DS70175F-page 124 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 127

... Center frequency (7.37 MHz nominal) 111111 = Center frequency – 0.375% (7.345 MHz) • • • 100001 = Center frequency – 11.625% (6.52 MHz) 100000 = Center frequency – 12% (6.49 MHz) © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — — — ...

Page 128

... If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. (OSCCON<5>) and the CF © 2007 Microchip Technology Inc. ...

Page 129

... PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 stops clock operation and halts all code execution. Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assem- ...

Page 130

... If a PMD bit is set, the corresponding mod- ule is disabled after a delay of 1 instruction cycle. Similarly PMD bit is cleared, the corresponding module is enabled after a delay of 1 instruction cycle (assuming the module control registers are already configured to enable module operation). © 2007 Microchip Technology Inc. possible ...

Page 131

... WR LAT + WR PORT CK Data Latch Read LAT Read Port © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 When a peripheral is enabled and actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the group output driver for the parallel port bit will be disabled peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port ...

Page 132

... CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. in either Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. capable of detecting input © 2007 Microchip Technology Inc. ...

Page 133

... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 • Interrupt on 16-bit Period register match or falling edge of external gate signal Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1) in the T1CON register. ...

Page 134

... Unimplemented: Read as ‘0’ DS70175F-page 132 U-0 U-0 — — R/W-0 U-0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 135

... For 32-bit timer/counter operation, Timer2, Timer4, Timer6 or Timer8 is the least significant word; Timer3, Timer5, Timer7 or Timer9 is the most significant word of the 32-bit timers. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Note: For 32-bit operation, T3CON, T5CON, T7CON and T9CON control bits are ignored ...

Page 136

... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70175F-page 134 (1) 1x Gate Sync PR2 PR3 Comparator LSB TMR3 TMR2 TMR3HLD 16 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2007 Microchip Technology Inc. ...

Page 137

... FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 1x Gate Sync TMR2 Sync Comparator PR2 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70175F-page 135 ...

Page 138

... In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. DS70175F-page 136 U-0 U-0 — — R/W-0 R/W-0 (1) T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 139

... External clock from pin TyCK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 (1) — — R/W-0 ...

Page 140

... PIC24HJXXXGPX06/X08/X10 NOTES: DS70175F-page 138 © 2007 Microchip Technology Inc. ...

Page 141

... Mode Select ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 3. Prescaler Capture Event modes -Capture timer value on every 4th rising edge of input at ICx pin ...

Page 142

... Timer selections may vary. Refer to the device data sheet for details. DS70175F-page 140 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 143

... Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to ‘100’. Disabling and re-enabling of the timer, and clear- © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 ing the TMRy register, are not required but may be advantageous for defining a pulse from a known event time boundary ...

Page 144

... Table 14-1 shows example PWM frequencies and resolutions for a device operating at 10 MIPS log 10 F PWM log (2) 10 • (Timer2 Prescale Value) /F )/log 2) bits PWM 10 2) bits 10 CALCULATING THE PWM PERIOD • (Timer Prescale Value bits = 16 MHz and a Timer2 CY © 2007 Microchip Technology Inc. ...

Page 145

... Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the time bases associated with the module. Note: Only OC1 and OC2 can trigger a DMA data transfer. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 61 Hz 122 Hz ...

Page 146

... Refer to the device data sheet for specific time bases available to the output compare module. DS70175F-page 144 U-0 U-0 U-0 — — — R-0 HC R/W-0 R/W-0 (1) OCFLT OCTSEL HS = Set in Hardware U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 OCM<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 147

... The module will not respond to SCL transitions while SPIROV is ‘1’, effectively disabling the module until SPIxBUF is read by user software. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Transmit writes are also double-buffered. The user writes to SPIxBUF. When the master or slave transfer is completed, the contents of the shift register (SPIxSR) are moved to the receive buffer ...

Page 148

... SPI1IF or SPI2IF bit gets set as a result of an SPI1 or SPI2 byte or word transfer. 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer SPIxTXB Write SPIxBUF 16 Internal Data Bus 1:1/4/16/64 F Primary CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock © 2007 Microchip Technology Inc. ...

Page 149

... User must write transmit data to/read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. FIGURE 15-3: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM PIC24H FIGURE 15-4: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM PIC24H © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 PROCESSOR 2 (SPI Slave) SDOx SDIx Serial Receive Buffer SDIx SDOx ...

Page 150

... Microchip Technology Inc. ...

Page 151

... SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — ...

Page 152

... The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). DS70175F-page 150 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE<2:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 (1) SMP CKE bit 8 R/W-0 R/W-0 PPRE<1:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 153

... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: Read as ‘0’ This bit must not be set to ‘1’ by the user application. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — ...

Page 154

... PIC24HJXXXGPX06/X08/X10 NOTES: DS70175F-page 152 © 2007 Microchip Technology Inc. ...

Page 155

... C slave operation with 10-bit address 2 • master operation with 7 or 10-bit address For details about the communication sequence in each of these modes, please refer to the “PIC24H Family Reference Manual”. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 2 16 Registers I2CxCON and I2CxSTAT are control and status registers, respectively ...

Page 156

... Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2007 Microchip Technology Inc. ...

Page 157

... The control bit, IPMIEN, enables the module to support the Intelligent Peripheral Management Interface (IPMI). When this bit is set, the module accepts and acts upon all addresses. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 16.8 General Call Address Support The general call address can address all devices. ...

Page 158

... SDAx is a ‘1’ and the data sampled on the SDAx pin = 0, then a bus collision has taken place. The 2 master will set the I C master events interrupt flag and 2 reset the master portion of the I C port to its Idle state. © 2007 Microchip Technology Inc. ...

Page 159

... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN ...

Page 160

... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress DS70175F-page 158 2 C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte master master master) © 2007 Microchip Technology Inc. ...

Page 161

... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 R/C-0 HS — ...

Page 162

... Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70175F-page 160 2 C slave device address byte. © 2007 Microchip Technology Inc. ...

Page 163

... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — ...

Page 164

... PIC24HJXXXGPX06/X08/X10 NOTES: DS70175F-page 162 © 2007 Microchip Technology Inc. ...

Page 165

... UART1 or UART2 transmission or reception DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e., UTXISEL<1:0> and URXISEL<1:0> = 00). © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 • Hardware Flow Control Option with UxCTS and UxRTS pins • ...

Page 166

... BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. Desired Baud Rate UART BAUD RATE WITH BRGH = Baud Rate = 4 • (BRGx + BRGx = – • Baud Rate denotes the instruction cycle clock /2). OSC CY © 2007 Microchip Technology Inc. /4 ...

Page 167

... Write 0x55 to UxTXREG – loads Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 17.5 Receiving in 8-bit or 9-bit Data Mode 1. Set up the UART (as described in Section 17.2 “ ...

Page 168

... DS70175F-page 166 MODE REGISTER x R/W-0 R/W-0 U-0 (1) IREN RTSMD — R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (2) R/W-0 R/W-0 UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 169

... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: This feature is only available for the 16x BRG mode (BRGH = 0). 2: Bit availability depends on pin availability. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 MODE REGISTER (CONTINUED) x DS70175F-page 167 ...

Page 170

... STATUS AND CONTROL REGISTER x U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R-0 R-1 UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 171

... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 STATUS AND CONTROL REGISTER (CONTINUED) x DS70175F-page 169 ...

Page 172

... PIC24HJXXXGPX06/X08/X10 NOTES: DS70175F-page 170 © 2007 Microchip Technology Inc. ...

Page 173

... Programmable link to input capture module (IC2 for both CAN1 and CAN2) for time-stamping and network synchronization • Low-power Sleep and Idle mode © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus ...

Page 174

... RXF11 Filter RXF10 Filter RXF9 Filter RXF8 Filter RXF7 Filter RXF6 Filter RXF5 Filter RXF4 Filter RXF3 Filter RXF2 Filter RXF1 Filter RXF0 Filter Buffer RXM2 Mask RXM1 Mask RXM0 Mask Control CPU Configuration Bus Logic Interrupts © 2007 Microchip Technology Inc. ...

Page 175

... The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2<14>) enables or disables the filter. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Note: Typically, if the CAN module is allowed to transmit in a particular mode of operation ...

Page 176

... Receiver Error Passive: The RXEP bit indicates that the receive error counter has exceeded the error passive limit of 127 and the module has gone into error passive state. © 2007 Microchip Technology Inc. ...

Page 177

... TXERRn bit will be set and the error condition may cause an interrupt. If the message loses arbitration during the transmission attempt, the TXLARBn bit is set. No interrupt is generated to signal the loss of arbitration. © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 18.5.4 AUTOMATIC PROCESSING OF REMOTE TRANSMISSION ...

Page 178

... definition, the nominal bit time has a minimum and a maximum the minimum nominal bit time is 1 μsec corresponding to a maximum bit rate of 1 MHz. Phase Phase Segment 1 Segment 2 Sample Point . Also, by definition, Q Sync © 2007 Microchip Technology Inc. ...

Page 179

... CAN module allows the user to choose between sam- pling three times at the same point or once at the same point, by setting or clearing the SAM bit (CiCFG2<6>). © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 Typically, the sampling of the bit should take place at about 60-70% through the bit time, depending on the system parameters ...

Page 180

... Use buffer window DS70175F-page 178 R/W-0 R/W-0 R/W-1 ABAT CANCKS U-0 R/W-0 U-0 — CANCAP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared CY OSC R/W-0 R/W-0 REQOP<2:0> bit 8 U-0 R/W-0 — — WIN bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 181

... DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compare up to data byte 3, bit 6 with EID<17> • • • 00001 = Compare up to data byte 1, bit 7 with EID<0> 00000 = Do not compare data bytes © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — — — ...

Page 182

... TRB2 buffer interrupt 0000001 = TRB1 buffer interrupt 0000000 = TRB0 Buffer interrupt DS70175F-page 180 R-0 R-0 R-0 FILHIT<4:0> R-0 R-0 R-0 ICODE<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...

Page 183

... Unimplemented: Read as ‘0’ bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits 11111 = RB31 buffer 11110 = RB30 buffer • • • 00001 = TRB1 buffer 00000 = TRB0 buffer © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 FSA< ...

Page 184

... TRB1 buffer 000000 = TRB0 buffer DS70175F-page 182 R-0 R-0 R-0 FBP<5:0> R-0 R-0 R-0 FNRB<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...

Page 185

... Unimplemented: Read as ‘0’ bit 3 FIFOIF: FIFO Almost Full Interrupt Flag bit bit 2 RBOVIF: RX Buffer Overflow Interrupt Flag bit bit 1 RBIF: RX Buffer Interrupt Flag bit bit 0 TBIF: TX Buffer Interrupt Flag bit © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R-0 R-0 R-0 TXBP RXBP TXWAR U-0 ...

Page 186

... TBIE: TX Buffer Interrupt Enable bit DS70175F-page 184 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 — FIFOIE RBOVIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 RBIE TBIE bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 187

... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 TERRCNT<7:0>: Transmit Error Count bits bit 7-0 RERRCNT<7:0>: Receive Error Count bits © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R-0 R-0 R-0 TERRCNT<7:0> R-0 R-0 R-0 RERRCNT<7:0> Unimplemented bit, read as ‘0’ ...

Page 188

... Q DS70175F-page 186 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 BRP<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared CAN CAN CAN CAN U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 189

... Bus line is sampled once at the sample point bit 5-3 SEG1PH<2:0>: Phase Buffer Segment 1 bits 111 = Length 000 = Length bit 2-0 PRSEG<2:0>: Propagation Time Segment bits 111 = Length 000 = Length © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 U-0 U-0 — — R/W-x R/W-x SEG1PH<2:0> ...

Page 190

... R/W-0 R/W-0 F2BP<3:0> R/W-0 R/W-0 R/W-0 F0BP<3:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 FLTEN9 FLTEN8 bit 8 R/W-1 R/W-1 FLTEN1 FLTEN0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 191

... F11BP<3:0>: RX Buffer Written when Filter 11 Hits bits bit 11-8 F10BP<3:0>: RX Buffer Written when Filter 10 Hits bits bit 7-4 F9BP<3:0>: RX Buffer Written when Filter 9 Hits bits bit 3-0 F8BP<3:0>: RX Buffer Written when Filter 8 Hits bits © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W Unimplemented bit, read as ‘ ...

Page 192

... F12BP<3:0>: RX Buffer Written when Filter 12 Hits bits DS70175F-page 190 R/W-0 R/W-0 R/W-0 F14BP<3:0> R/W-0 R/W-0 R/W-0 F12BP<3:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 193

... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 EID<15:0>: Extended Identifier bits 1 = Message address bit EIDx must be ‘ Message address bit EIDx must be ‘ © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-x R/W-x R/W-x SID7 SID6 SID5 U-0 ...

Page 194

... Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask DS70175F-page 192 R/W-0 R/W-0 R/W-0 F5MSK<1:0> R/W-0 R/W-0 R/W-0 F1MSK<1:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 F4MSK<1:0> bit 8 R/W-0 R/W-0 F0MSK<1:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 195

... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 EID<15:0>: Extended Identifier bits 1 = Include bit EIDx in filter comparison 0 = Bit EIDx is don’t care in filter comparison © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-x R/W-x R/W-x SID7 SID6 SID5 U-0 ...

Page 196

... RXFUL20 RXFUL19 RXFUL18 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/C-0 R/C-0 RXFUL9 RXFUL8 bit 8 R/C-0 R/C-0 RXFUL1 RXFUL0 bit Bit is unknown R/C-0 R/C-0 RXFUL25 RXFUL24 bit 8 R/C-0 R/C-0 RXFUL17 RXFUL16 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 197

... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 RXOVF<31:16>: Receive Buffer n Overflow bits 1 = Module pointed a write to a full buffer (set by module Overflow is cleared (clear by application software) © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/C-0 R/C-0 R/C-0 RXOVF12 RXOVF11 RXOVF10 ...

Page 198

... This bit is cleared when TXREQ is set. DS70175F-page 196 R-0 R/W-0 R/W-0 TXERRn TXREQn RTRENn R-0 R/W-0 R/W-0 (1) (1) TXERRm TXREQm RTRENm U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) R/W-0 R/W-0 TXnPRI<1:0> bit 8 R/W-0 R/W-0 TXmPRI<1:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 199

... EID11 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 EID<17:6>: Extended Identifier bits © 2007 Microchip Technology Inc. PIC24HJXXXGPX06/X08/X10 R/W-x R/W-x R/W-x SID10 SID9 SID8 R/W-x R/W-x R/W-x SID2 ...

Page 200

... Bit is cleared (1) R/W-x R/W-x R/W-x TRBnDm4 TRBnDm3 TRBnDm2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x R/W-x RTR RB1 bit 8 R/W-x R/W-x DLC1 DLC0 bit Bit is unknown R/W-x R/W-x TRBnDm1 TRBnDm0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

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