PIC24HJ64GP206-I/PT Microchip Technology, PIC24HJ64GP206-I/PT Datasheet - Page 48

• Manufacturer Part Number: PIC24HJ64GP206-I/PT
• Description: IC PIC MCU FLASH 32KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP206-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 13
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 18 Channel
• Controller Family/series: PIC24
• No. Of I/o's: 53
• Ram Memory Size: 8KB
• Cpu Speed: 40MIPS
• No. Of Timers: 13
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.10
The verify step involves reading back the code memory
space and comparing it against the copy held in the
programmer’s buffer. The Configuration registers are
verified with the rest of the code.
The verify process is illustrated in
reads occur a single byte at a time, so two bytes must
be read to compare against the word in the program-
mer’s buffer. Refer to
Memory”
memory.
FIGURE 5-9:
DS70152H-page 48
Note:
No
Verify Code Memory and
Configuration Word
for implementation details of reading code
Because
include the device code protection bit,
code
immediately after writing, if the code
protection is enabled. This is because the
device will not be readable or verifiable if
a device Reset occurs after the code-pro-
tect bit in the FGS Configuration register
has been cleared.
with Post-Increment
with Post-Increment
Set TBLPTR = 0
Read High Byte
Read Low Byte
Word = Expect
code memory
memory
verified?
Data?
Does
Start
End
VERIFY CODE
MEMORY FLOW
the
All
Section 5.8 “Reading Code
Yes
Yes
Configuration
should
Figure
No
Report Error
Failure
be
5-9. Memory
registers
verified
5.11
The Application ID Word is stored at address 0x8007F0
in executive code memory. To read this memory
location, you must use the SIX control code to move
this program memory location to the VISI register.
Then, the REGOUT control code must be used to clock
the contents of the VISI register out of the device. The
corresponding control and instruction codes that must
be serially transmitted to the device to perform this
operation are shown in
After the programmer has clocked out the Application
ID Word, it must be inspected. If the application ID has
the value 0xCB, the programming executive is resident
in memory and the device can be programmed using
the mechanism described in
Programming – Enhanced
application ID has any other value, the programming
executive is not resident in memory; it must be loaded
to memory before the device can be programmed. The
procedure for loading the programming executive to
memory is described in
the Programming Executive to
5.12
Exiting Program/Verify mode is done by removing V
from MCLR, as illustrated in
requirement for exit is that an interval P16 should
elapse between the last clock and program signals on
PGCx and PGDx before removing V
FIGURE 5-10:
PGDx
PGCx
MCLR
V
DD
Reading the Application ID Word
Exiting ICSP Mode
PGDx = Input
EXITING ICSP™ MODE
Table
© 2010 Microchip Technology Inc.
Section 6.0 “Programming
V
P16
IH
5-10.
ICSP”. However, if the
Figure
Section 3.0 “Device
Memory”.
P17
V
IH
IH
.
5-10. The only
IH