DSPIC33FJ16GS504-I/PT Microchip Technology, DSPIC33FJ16GS504-I/PT Datasheet - Page 205

IC DSPIC MCU/DSP 16K 44-TQFP

DSPIC33FJ16GS504-I/PT

Manufacturer Part Number
DSPIC33FJ16GS504-I/PT
Description
IC DSPIC MCU/DSP 16K 44-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS504-I/PT

Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
44-TQFP, 44-VQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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REGISTER 15-6:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-6
bit 5-3
FLTSTAT
Note 1: Software must clear the interrupt status here and the corresponding IFS bit in the interrupt controller.
HS/HC-0
R/W-0
2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
3: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
4: To operate in External Period Reset mode, configure FCLCONx<CLMOD> = 0 and PWMCONx<ITB> = 1.
DTC<1:0>
(1)
CAM bit is ignored.
yield unpredictable results.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
FLTSTAT: Fault Interrupt Status bit
1 = Fault interrupt is pending
0 = No Fault interrupt is pending. This bit is cleared by setting FLTIEN = 0.
CLSTAT: Current-Limit Interrupt Status bit
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending. This bit is cleared by setting CLIEN = 0.
TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending. This bit is cleared by setting TRGIEN = 0.
FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and the FLTSTAT bit is cleared
CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt enabled
0 = Current-limit interrupt disabled and the CLSTAT bit is cleared
TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an interrupt request
0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared
ITB: Independent Time Base Mode bit
1 = PHASEx/SPHASEx register provides time base period for this PWM generator
0 = PTPER register provides timing for this PWM generator
MDCS: Master Duty Cycle Register Select bit
1 = MDC register provides duty cycle information for this PWM generator
0 = PDCx/SDCx register provides duty cycle information for this PWM generator
DTC<1:0>: Dead-Time Control bits
00 = Positive dead time actively applied for all output modes
01 = Negative dead time actively applied for all output modes
10 = Dead-time function is disabled
11 = Reserved
Unimplemented: Read as ‘0’
CLSTAT
HS/HC-0
R/W-0
PWMCONx: PWMx CONTROL REGISTER
(1)
W = Writable bit
HC = Hardware Clearable bit
‘1’ = Bit is set
TRGSTAT
HS/HC-0
U-0
Preliminary
FLTIEN
(1)
R/W-0
U-0
(3)
(1)
(3)
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CLIEN
R/W-0
U-0
CAM
TRGIEN
R/W-0
R/W-0
(2,3)
x = Bit is unknown
XPRES
R/W-0
R/W-0
ITB
DS70318D-page 203
(3)
(4)
MDCS
R/W-0
R/W-0
IUE
bit 8
bit 0
(3)

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