DSPIC33FJ16GS504-I/PT Microchip Technology, DSPIC33FJ16GS504-I/PT Datasheet - Page 37

• Manufacturer Part Number: DSPIC33FJ16GS504-I/PT
• Description: IC DSPIC MCU/DSP 16K 44-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS504-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.5
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 ALU is 16 bits wide and is capable of addition,
subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are 2’s
complement in nature. Depending on the operation, the
ALU can affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC) Status
bits in the SR register. The C and DC Status bits operate
as Borrow and Digit Borrow bits, respectively, for
subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for information on the SR bits
affected by each instruction.
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 CPU incorporates hardware support for both multipli-
cation and division. This includes a dedicated hardware
multiplier and support hardware for 16-bit-divisor division.
3.5.1
Using the high-speed, 17-bit x 17-bit multiplier of the
DSP engine, the ALU supports unsigned, signed or
mixed sign operation in several MCU multiplication
modes:
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
© 2009 Microchip Technology Inc.
Arithmetic Logic Unit (ALU)
MULTIPLIER
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
Preliminary
3.5.2
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
• 32-bit signed/16-bit signed divide
• 32-bit unsigned/16-bit unsigned divide
• 16-bit signed/16-bit signed divide
• 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0 and
the remainder in W1. 16-bit signed and unsigned DIV
instructions can specify any W register for both the 16-bit
divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both 32-bit/
16-bit and 16-bit/16-bit instructions take the same
number of cycles to execute.
3.6
The DSP engine consists of a high-speed, 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 is a single-cycle instruction flow architecture; there-
fore, concurrent operation of the DSP engine with MCU
instruction flow is not possible. However, some MCU ALU
and DSP engine resources can be used concurrently by
the same instruction (for example, ED, EDAC).
The
accumulator-to-accumulator operations that require no
additional data. These instructions are ADD, SUB and
NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
• Fractional or integer DSP multiply (IF)
• Signed or unsigned DSP multiply (US)
• Conventional or convergent rounding (RND)
• Automatic saturation on/off for ACCA (SATA)
• Automatic saturation on/off for ACCB (SATB)
• Automatic saturation on/off for writes to data
• Accumulator Saturation mode selection
A block diagram of the DSP engine is shown in
Figure 3-3.
memory (SATDW)
(ACCSAT)
DSP
DSP Engine
DIVIDER
engine
can
also
perform
DS70318D-page 35
inherent