DSPIC33FJ64GS406-I/MR Microchip Technology, DSPIC33FJ64GS406-I/MR Datasheet

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... Microchip Technology Inc. High-Performance, 16-bit Digital Signal Controllers Preliminary Data Sheet DS70591C ...

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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

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... Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing) • Most peripherals support DMA  2010 Microchip Technology Inc. dsPIC33FJ64GS406/606/608/610 Digital I/O: • programmable digital I/O pins • Wake-up/Interrupt-on-Change for pins • Output pins can drive voltage from 3.0V to 3.6V • ...

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... Peripheral Features (Continued) • UART (up to two modules): - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4-character TX and RX FIFO buffers - LIN bus support © - IrDA encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS • ...

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... Uninterruptible Power Supply (UPS) Packaging: • 64-pin QFN (9x9x0.9 mm) • 64-pin TQFP (10x10x1 mm) • 80-pin TQFP (12x12x1 mm) • 100-pin TQFP (14x14x1 mm and 12x12x1 mm) Note: See the dsPIC33FJ32GS406/606/608/ 610 and dsPIC33FJ64GS406/606/608/ 610 Controller Families table for exact peripheral features per device. Preliminary DS70591C-page 5 ...

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... PRODUCT FAMILIES The device names, pin counts, memory sizes, and peripheral availability of each device are listed in Table 1. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 CONTROLLER FAMILIES Device dsPIC33FJ32GS406 dsPIC33FJ32GS606 dsPIC33FJ32GS608 80 32 ...

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... Pin Diagrams 64-Pin TQFP PWM3H/RE5 1 PWM4L/RE6 2 PWM4H/RE7 3 SCK2/FLT12/CN8/RG6 4 SDI2/FLT11/CN9/RG7 5 SDO2/FLT10/CN10/RG8 6 MCLR 7 SS2/FLT9/SYNCI2/T5CK/CN11/RG9 AN5/AQEB1/CN7/RB5 11 AN4/AQEA1/CN6/RB4 12 AN3/AINDX1/CN5/RB3 13 AN2/ASS1/CN4/RB2 14 PGEC3/B/AN1/CN3/RB1 15 PGED3/AN0/CN2/RB0 16  2010 Microchip Technology Inc. = Pins are tolerant 48 PGEC2/SOSCO/T1CK/CN0/RC14 47 PGED2/SOSCI/T4CK/CN1/RC13 46 OC1/QEB1/FLT5/RD0 45 IC4/QEA1/FLT4/INT4/RD11 44 IC3/INDX1/FLT3/INT3/RD10 43 IC2/FLT2/U1CTS/INT2/RD9 42 IC1/FLT1/SYNCI1/INT1/RD8 dsPIC33FJ32GS406 dsPIC33FJ64GS406 40 OSC2/REFCLKO/CLKO/RC15 39 OSC1/CLKIN/RC12 SCL1/RG2 ...

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... Pin Diagrams (Continued) 64-Pin QFN PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 AN5/AQEB1/CN7/RB5 12 AN4/AQEA1/CN6/RB4 13 AN3/AINDX1/CN5/RB3 14 AN2/ASS1/CN4/RB2 15 PGEC3/B/AN1/CN3/RB1 16 PGED3/AN0/CN2/RB0 Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS DS70591C-page 8 ...

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... Pin Diagrams (Continued) 64-Pin TQFP PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 AN5/CMP3B/AQEB1/CN7/RB5 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 AN3/CMP2B/AINDX1/CN5/RB3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 PGEC3/B/AN1/CMP1B/CN3/RB1 PGED3/AN0/CMP1A/CMP4C/CN2/RB0  2010 Microchip Technology Inc dsPIC33FJ32GS606 Preliminary = Pins are tolerant 48 PGEC2/SOSCO/T1CK/CN0/RC14 47 PGED2/SOSCI/T4CK/CN1/RC13 46 OC1/QEB1/FLT5/RD0 45 IC4/QEA1/FLT4/INT4/RD11 44 IC3/INDX1/FLT3/INT3/RD10 43 IC2/FLT2/U1CTS/INT2/RD9 42 IC1/FLT1/SYNCI1/INT1/RD8 OSC2/REFCLKO/CLKO/RC15 39 OSC1/CLKIN/RC12 ...

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... Pin Diagrams (Continued) 64-Pin TQFP PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 AN5/CMP3B/AQEB1/CN7/RB5 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 AN3/CMP2B/AINDX1/CN5/RB3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 PGEC3/B/AN1/CMP1B/CN3/RB1 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 DS70591C-page dsPIC33FJ64GS606 Preliminary = Pins are tolerant 48 PGEC2/SOSCO/T1CK/CN0/RC14 47 PGED2/SOSCI/T4CK/CN1/RC13 46 OC1/QEB1/FLT5/RD0 45 IC4/QEA1/FLT4/INT4/RD11 44 IC3/INDX1/FLT3/INT3/RD10 43 IC2/FLT2/U1CTS/INT2/RD9 42 IC1/FLT1/SYNCI1/INT1/RD8 OSC2/REFCLKO/CLKO/RC15 39 OSC1/CLKIN/RC12 SCL1/RG2 36 SDA1/RG3 35 U1RTS/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 ...

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... Pin Diagrams (Continued) 64-Pin QFN PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 AN5/CMP3B/AQEB1/CN7/RB5 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 AN3/CMP2B/AINDX1/CN5/RB3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 PGEC3/B/AN1/CMP1B/CN3/RB1 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS  2010 Microchip Technology Inc. ...

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... Pin Diagrams (Continued) 64-Pin QFN PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 AN5/CMP3B/AQEB1/CN7/RB5 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 AN3/CMP2B/AINDX1/CN5/RB3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 PGEC3/B/AN1/CMP1B/CN3/RB1 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS DS70591C-page 12 ...

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... Pin Diagrams (Continued) 80-Pin TQFP PWM3H/RE5 1 PWM4L/RE6 2 PWM4H/RE7 3 AN16/T2CK/RC1 4 AN17/T3CK/RC2 5 SCK2/FLT12/CN8/RG6 6 SDI2/FLT11/CN9/RG7 7 SDO2/FLT10/CN10/RG8 8 MCLR 9 SS2/FLT9/T5CK/CN11/RG9 TMS/FLT13/INT1/RE8 13 TDO/FLT14/INT2/RE9 14 AN5/CMP3B/AQEB1/CN7/RB5 15 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 16 AN3/CMP2B/AINDX1/CN5/RB3 17 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 18 PGEC3/AN1/CMP1B/CN3/RB1 19 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 20  2010 Microchip Technology Inc. = Pins are tolerant dsPIC33FJ32GS608 Preliminary PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/RD11 IC3/INDX1/FLT3/RD10 ...

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... Pin Diagrams (Continued) 80-Pin TQFP PWM3H/RE5 1 PWM4L/RE6 2 PWM4H/RE7 3 AN16/T2CK/RC1 4 AN17/T3CK/RC2 5 SCK2/FLT12/CN8/RG6 6 SDI2/FLT11/CN9/RG7 7 SDO2/FLT10/CN10/RG8 8 MCLR 9 SS2/FLT9/T5CK/CN11/RG9 TMS/FLT13/INT1/RE8 13 TDO/FLT14/INT2/RE9 14 AN5/CMP3B/AQEB1/CN7/RB5 15 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 16 AN3/CMP2B/AINDX1/CN5/RB3 17 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 18 PGEC3/AN1/CMP1B/CN3/RB1 19 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 20 DS70591C-page 14 = Pins are tolerant dsPIC33FJ64GS608 Preliminary  2010 Microchip Technology Inc. PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/RD11 ...

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... Pin Diagrams (Continued) 100-Pin TQFP SYNCI1/RG15 PWM3H/RE5 4 PWM4L/RE6 PWM4H/RE7 5 AN16/T2CK/RC1 6 AN17/T3CK/RC2 7 AN18/T4CK/RC3 8 AN19/T5CK/RC4 9 SCK2/FLT12/CN8/RG6 10 SDI2/FLT11/CN9/RG7 11 SDO2/FLT10/CN10/RG8 12 MCLR 13 SS2/FLT9/CN11/RG9 TMS/RA0 17 AN20/FLT13/INT1/RE8 18 AN21/FLT14/INT2/RE9 19 AN5/CMP3B/AQEB1/CN7/RB5 20 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 21 AN3/CMP2B/AINDX1/CN5/RB3 22 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 23 PGEC3/AN1/CMP1B/CN3/RB1 24 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 25  2010 Microchip Technology Inc. = Pins are tolerant dsPIC33FJ32GS610 Preliminary Vss ...

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... Pin Diagrams (Continued) 100-Pin TQFP SYNCI1/RG15 PWM3H/RE5 3 PWM4L/RE6 4 PWM4H/RE7 5 AN16/T2CK/RC1 6 AN17/T3CK/RC2 7 AN18/T4CK/RC3 8 AN19/T5CK/RC4 9 SCK2/FLT12/CN8/RG6 10 SDI2/FLT11/CN9/RG7 11 SDO2/FLT10/CN10/RG8 12 MCLR 13 SS2/FLT9/CN11/RG9 TMS/RA0 17 AN20/FLT13/INT1/RE8 18 AN21/FLT14/INT2/RE9 19 AN5/CMP3B/AQEB1/CN7/RB5 20 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 21 AN3/CMP2B/AINDX1/CN5/RB3 22 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 23 PGEC3/AN1/CMP1B/CN3/RB1 24 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 25 DS70591C-page 16 = Pins are tolerant dsPIC33FJ64GS610 Preliminary  2010 Microchip Technology Inc. ...

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... Table of Contents dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Product Families ............................................................... 6 1.0 Device Overview ........................................................................................................................................................................ 19 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 25 3.0 CPU............................................................................................................................................................................................ 35 4.0 Memory Organization ................................................................................................................................................................. 47 5.0 Flash Program Memory............................................................................................................................................................ 109 6.0 Resets ..................................................................................................................................................................................... 115 7.0 Interrupt Controller ................................................................................................................................................................... 123 8.0 Direct Memory Access (DMA) ...

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... TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...

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... The dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 families of devices contain extensive Digital Signal Processor (DSP) func- tionality with a high-performance 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ32GS406/ 606/608/610 and dsPIC33FJ64GS406/606/608/610 devices ...

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... FIGURE 1-1: BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCU PCH PCL 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode & Control Control Signals to Various Blocks Power-up Timing ...

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... TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name Type Type AN0-AN23 I Analog CLKI I ST/CMOS CLKO O OSC1 I ST/CMOS OSC2 I/O SOSCI I ST/CMOS SOSCO O CN0-CN23 I C1RX I C1TX O IC1-IC4 I INDX1, INDX2, AINDX1 I QEA1, QEA2, AQEA1 I QEB1, QEB2, AQEB1 I UPDN1 O CMOS ...

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... TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type U1CTS I U1RTS O U1RX I U1TX O U2CTS I U2RTS O U2RX I U2TX O SCK1 I/O SDI1 I SDO1 O SS1, ASS1 I/O SCK2 I/O SDI2 I SDO2 O SS2 I/O SCL1 I/O SDA1 I/O SCL2 ...

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... TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type FLT1-FLT23 I SYNCI1-SYNCI4 I SYNCO1-SYNCO2 O PWM1L O PWM1H O PWM2L O PWM2H O PWM3L O PWM3H O PWM4L O PWM4H O PWM5L O PWM5H O PWM6L O PWM6H O PWM7L O PWM7H O PWM8L O PWM8H O PWM9L O PWM9H O PGED1 I/O PGEC1 I PGED2 I/O ...

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... NOTES: DS70591C-page 24 Preliminary  2010 Microchip Technology Inc. ...

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... Basic Connection Requirements Getting started with dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 family of 16-bit Digital Signal Controllers (DSC) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • All V and V ...

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... FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION MCLR C dsPIC33F 0.1 µF Ceramic 0.1 µF 10  Ceramic 2.2.1 TANK CAPACITORS On boards with power traces running longer than six inches in length suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source ...

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... ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging pur- poses recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is ...

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... Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < F < 8 MHz to comply with device PLL IN start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in the FRC mode first ...

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... FIGURE 2-4: DIGITAL PFC ADC Channel FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION ADC Channel  2010 Microchip Technology Inc. I PFC | FET k 2 Driver ADC Channel PWM Output dsPIC33FJ32GS406 I PFC INPUT FET k 2 Driver ADC PWM Channel Output dsPIC33FJ32GS406 Preliminary ...

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... FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input k 7 ADC Channel FIGURE 2-7: MULTI-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input FET k 7 Driver ADC Channel dsPIC33FJ32GS608 DS70591C-page 30 5V Output I 5V FET Driver Analog ADC Comp. Channel dsPIC33FJ32GS606 FET Driver ...

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... FIGURE 2-8: OFF-LINE UPS Push-Pull Converter V BAT GND FET FET k Driver Driver 2 PWM PWM ADC or Analog Comp ADC ADC k 6 Battery Charger  2010 Microchip Technology Inc GND FET FET FET FET k Driver Driver Driver Driver 1 ADC PWM ...

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... FIGURE 2-9: INTERLEAVED PFC | ADC Channel ADC Channel DS70591C-page FET FET Driver Driver ADC ADC ADC PWM PWM Channel Channel Channel dsPIC33FJ32GS608 Preliminary V + OUT OUT  2010 Microchip Technology Inc. ...

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... FIGURE 2-10: PHASE-SHIFTED FULL-BRIDGE CONVERTER Gate 3 Gate 1 S1 Gate Gate 1 FET Driver S1 Gate 2  2010 Microchip Technology Inc. Gate 6 S3 Gate 4 Gate 5 Analog Ground PWM Gate 3 FET Driver PWM S3 Gate 4 Preliminary V + OUT V - OUT Gate 5 FET k 2 Driver k 1 ADC ...

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FIGURE 2-11: AC-TO-DC POWER SUPPLY WITH PFC AND THREE OUTPUTS (12V, 5V, AND 3.3V) ZVT with Current Doubler Synchronous Rectifier V _ Isolation HV BUS Barrier I ZVT FET FET Driver Driver k 4 ADC ADC Channel Channel PWM Primary ...

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... The dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC bits wide and addresses bits of user program memory space ...

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... Special MCU Features The dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 features a 17-bit by 17-bit single-cycle multiplier that is shared by both the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication ...

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... FIGURE 3-2: PROGRAMMER’S MODEL DSP Operand Registers DSP Address Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG 22 DOSTART OAB SAB DA SRH  2010 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 ...

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... CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER R-0 R-0 R/C bit 15 (2) (3) R/W-0 R/W-0 R/W-0 (2) IPL<2:0> bit 7 Legend Clearable bit R = Readable bit S = Settable bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 OA: Accumulator A Overflow Status bit ...

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... REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) ...

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... REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-1 SATA SATB SATDW bit 7 Legend Clearable bit R = Readable bit W = Writable bit 0’ = Bit is cleared ‘x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ ...

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... Arithmetic Logic Unit (ALU) The dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register ...

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... TABLE 3-1: DSP INSTRUCTIONS SUMMARY Instruction CLR ED EDAC MAC MAC MOVSAC MPY MPY MPY.N MSC FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70591C-page 42 Algebraic Operation – y – y change – – 40-bit Accumulator A 40-bit Accumulator B Saturate Adder ...

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... MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value ...

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... The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled) ...

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... Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder ...

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... NOTES: DS70591C-page 46 Preliminary  2010 Microchip Technology Inc. ...

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... The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to and permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 devices are shown in Figure 4-1. dsPIC33FJ64GS406/606/608/610 0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 ...

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... The dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). ...

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... Data Address Space The dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 CPU has a separate 16-bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space ...

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... FIGURE 4-3: DATA MEMORY MAP FOR DEVICES WITH 4 KB RAM MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 0x0FFF 0x1001 0x17FF 0x1801 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70591C-page 50 LSB 16 bits Address MSb LSb 0x0000 SFR Space ...

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... FIGURE 4-4: DATA MEMORY MAP FOR DEVICES WITH 8 KB RAM MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 0x17FF 0x1801 0x1FFF 0x2001 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF  2010 Microchip Technology Inc. LSB 16 bits ...

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... FIGURE 4-5: DATA MEMORY MAP FOR DEVICES WITH 9 KB RAM MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 0x17FF 0x1801 0x1FFF 0x2001 0x27FF 0x2801 0x2BFF 0x2C01 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70591C-page 52 LSB 16 bits Address MSb ...

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... X AND Y DATA SPACES The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths ...

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TABLE 4-1: CPU CORE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...

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TABLE 4-1: CPU CORE REGISTER MAP (CONTINUED) SFR SFR Name Bit 15 Bit 14 Bit 13 Addr XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — Legend unknown value on Reset, — ...

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... CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CNPU2 — — — — 006A Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES File SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 ...

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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES File SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF ADIF U1TXIF ...

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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES (CONTINUED) File SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr IPC21 00CE — — — — IPC23 00D2 — PWM2IP<2:0> IPC24 00D4 — PWM6IP<2:0> IPC25 00D6 — AC2IP<2:0> ...

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TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF ADIF ...

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TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES (CONTINUED) SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr IPC20 00CC — — — — IPC21 00CE — — — — IPC23 00D2 — PWM2IP<2:0> IPC24 00D4 ...

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TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF ADIF U1TXIF ...

Page 62

TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES (CONTINUED) SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr IPC20 00CC — — — — IPC21 00CE — — — — IPC23 00D2 — PWM2IP<2:0> IPC24 00D4 ...

Page 63

... TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — ADIF U1TXIF IFS1 0086 U2TXIF ...

Page 64

... TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES (CONTINUED) SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr IPC21 00CE — — — — IPC23 00D2 — PWM2IP<2:0> IPC24 00D4 — PWM6IP<2:0> IPC27 00DA — ADCP1IP<2:0> IPC28 00DC — ...

Page 65

TABLE 4-8: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — ADIF U1TXIF ...

Page 66

TABLE 4-8: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES (CONTINUED) SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr IPC21 00CE — — — — IPC23 00D2 — PWM2IP<2:0> IPC24 00D4 — PWM6IP<2:0> IPC25 00D6 — AC2IP<2:0> ...

Page 67

TABLE 4-9: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS608 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — ADIF U1TXIF IFS1 ...

Page 68

TABLE 4-9: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS608 (CONTINUED) SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr IPC21 00CE — — — — IPC23 00D2 — PWM2IP<2:0> IPC24 00D4 — PWM6IP<2:0> IPC25 00D6 — AC2IP<2:0> IPC26 ...

Page 69

TABLE 4-10: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — ADIF U1TXIF ...

Page 70

TABLE 4-10: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES (CONTINUED) SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr IPC21 00CE — — — — IPC23 00D2 — PWM2IP<2:0> IPC24 00D4 — PWM6IP<2:0> IPC25 00D6 — AC2IP<2:0> ...

Page 71

TABLE 4-11: TIMERS REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON TON — TSIDL — 0104 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON TON — ...

Page 72

TABLE 4-13: OUTPUT COMPARE REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C ...

Page 73

TABLE 4-16: HIGH-SPEED PWM REGISTER MAP Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PTCON 0400 PTEN — PTSIDL SESTAT PTCON2 0402 — — — PTPER 0404 SEVTCMP 0406 MDC 040A STCON 040E — — — ...

Page 74

TABLE 4-18: HIGH-SPEED PWM GENERATOR 2 REGISTER MAP Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON2 0440 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON2 0442 PENH PENL POLH POLL FCLCON2 0444 IFLTMOD CLSRC<4:0> PDC2 0446 PHASE2 0448 ...

Page 75

TABLE 4-19: HIGH-SPEED PWM GENERATOR 3 REGISTER MAP Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON3 0460 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON3 0462 PENH PENL POLH POLL FCLCON3 0464 IFLTMOD CLSRC<4:0> PDC3 0466 PHASE3 0468 ...

Page 76

TABLE 4-20: HIGH-SPEED PWM GENERATOR 4 REGISTER MAP Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON4 0480 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON4 0482 PENH PENL POLH POLL FCLCON4 0484 IFLTMOD CLSRC<4:0> PDC4 0486 PHASE4 0488 ...

Page 77

TABLE 4-21: HIGH-SPEED PWM GENERATOR 5 REGISTER MAP Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON5 04A0 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON5 04A2 PENH PENL POLH POLL FCLCON5 04A4 IFLTMOD CLSRC<4:0> PDC5 04A6 PHASE5 04A8 ...

Page 78

TABLE 4-22: HIGH-SPEED PWM GENERATOR 6 REGISTER MAP Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON6 04C0 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON6 04C2 PENH PENL POLH POLL FCLCON6 04C4 IFLTMOD CLSRC<4:0> PDC6 04C6 PHASE6 04C8 ...

Page 79

... TABLE 4-23: HIGH-SPEED PWM GENERATOR 7 REGISTER MAP (EXCLUDES dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES) Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON7 04E0 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON7 04E2 PENH PENL POLH POLL FCLCON7 04E4 IFLTMOD CLSRC<4:0> PDC7 04E6 PHASE7 04E8 DTR7 04EA — ...

Page 80

... TABLE 4-24: HIGH-SPEED PWM GENERATOR 8 REGISTER MAP (EXCLUDES dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES) Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON8 0500 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON8 0502 PENH PENL POLH POLL FCLCON8 0504 IFLTMOD CLSRC<4:0> PDC8 0506 PHASE8 0508 DTR8 050A — ...

Page 81

TABLE 4-25: HIGH-SPEED PWM GENERATOR 9 REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Offset PWMCON9 0520 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON9 0522 PENH PENL POLH POLL FCLCON9 0524 IFLTMOD ...

Page 82

TABLE 4-27: I2C2 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C2RCV 0210 — — — — I2C2TRN 0212 — — — — I2C2BRG 0214 — — — — I2C2CON 0216 I2CEN — I2CSIDL ...

Page 83

TABLE 4-30: SPI1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr SPI1STAT 0240 SPIEN — SPISIDL — SPI1CON1 0242 — — — DISSCK DISSDO SPI1CON2 0244 FRMEN SPIFSD FRMPOL — SPI1BUF 0248 Legend: x ...

Page 84

TABLE 4-32: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES ONLY SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr ADCON 0300 ADON — ADSIDL SLOWCLK ADPCFG 0302 PCFG15 PCFG14 PCFG13 PCFG12 ADPCFG2 0304 — ...

Page 85

TABLE 4-32: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES ONLY (CONTINUED) SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr ADCBUF22 036C ADCBUF23 036E ADCBUF24 0370 ADCBUF25 0372 Legend unknown value on ...

Page 86

TABLE 4-33: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr ADCON 0300 ADON — ADSIDL SLOWCLK ADPCFG 0302 PCFG15 PCFG14 PCFG13 PCFG12 ADPCFG2 0304 — — ...

Page 87

... TABLE 4-34: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr ADCON 0300 ADON — ADSIDL SLOWCLK ADPCFG 0302 PCFG15 PCFG14 PCFG13 PCFG12 ADSTAT 0306 — — — P12RDY ADBASE 0308 ADCPC0 ...

Page 88

TABLE 4-35: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE — — — DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A — — — — ...

Page 89

TABLE 4-36: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0600 — — CSIDL ABAT C1CTRL2 0602 — — — C1VEC 0604 — — — C1FCTRL 0606 ...

Page 90

TABLE 4-38: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0600- 061E C1BUFPNT1 0620 F3BP<3:0> C1BUFPNT2 0622 F7BP<3:0> C1BUFPNT3 0624 F11BP<3:0> C1BUFPNT4 0626 F15BP<3:0> C1RXM0SID 0630 SID<10:3> C1RXM0EID 0632 EID<15:8> ...

Page 91

TABLE 4-38: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF11EID 066E EID<15:8> C1RXF12SID 0670 SID<10:3> C1RXF12EID 0672 EID<15:8> C1RXF13SID 0674 SID<10:3> C1RXF13EID 0676 EID<15:8> C1RXF14SID 0678 SID<10:3> C1RXF14EID ...

Page 92

TABLE 4-39: ANALOG COMPARATOR CONTROL REGISTER MAP File Name ADR Bit 15 Bit 14 Bit 13 Bit 12 CMPCON1 0540 CMPON — CMPSIDL CMPDAC1 0542 — — - CMPCON2 0544 CMPON — CMPSIDL CMPDAC2 0546 — — - CMPCON3 0548 ...

Page 93

... RC12 LATC 02D4 LATC15 LATC14 LATC13 LATC12 Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-45: PORTC REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TRISC 02D0 ...

Page 94

... ODCE 02E6 — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-49: PORTE REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TRISE 02E0 — ...

Page 95

... ODCF 02EE — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-52: PORTF REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TRISF 02E8 — ...

Page 96

... ODCG 02F6 — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-55: PORTG REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TRISG 02F0 — ...

Page 97

TABLE 4-57: NVM REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Name NVMCON 0760 WR WREN WRERR — NVMKEY 0766 — — — — Legend unknown value on Reset, — = unimplemented, read as ...

Page 98

TABLE 4-60: PMD REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr PMD1 0770 T5MD T4MD T3MD T2MD PMD2 0772 — — — — PMD3 0774 — — — — PMD4 0776 ...

Page 99

... PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD PMD7 077C — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-64: PMD REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr PMD1 ...

Page 100

... SOFTWARE STACK In addition to its use as a working register, the W15 register in the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-6 ...

Page 101

... TABLE 4-65: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset (Register Indexed) Register Indirect with Literal Offset 4.3.3 MOVE AND ACCUMULATOR INSTRUCTIONS ...

Page 102

... Modulo Addressing Modulo Addressing mode is a method used to provide an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code typical in many DSP algorithms. ...

Page 103

... MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. Address boundaries check for addresses equal to: • The upper boundary addresses for incrementing buffers • The lower boundary addresses for decrementing buffers ...

Page 104

... FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE b15 b14 b13 b12 b11 b10 b9 b8 b15 b14 b13 b12 b11 b10 b9 b8 TABLE 4-66: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address DS70591C-page 104 Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value ...

Page 105

... Interfacing Program and Data Memory Spaces The dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces ...

Page 106

... FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION (1) Program Counter (2) Table Operations (1) Program Space Visibility (Remapping) User/Configuration Space Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. ...

Page 107

... DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data ...

Page 108

... READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H) ...

Page 109

... In-Circuit Serial Programming™ (ICSP™) programming capability • Run-Time Self-Programming (RTSP) ICSP allows a dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming ...

Page 110

... RTSP Operation The dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 Flash program mem- ory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instruc- tions time, and to program one row or one word at a time ...

Page 111

... REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER (1) (1) R/SO-0 R/W-0 R/W-0 WR WREN WRERR bit 15 (1) U-0 R/W-0 U-0 — ERASE — bit 7 Legend Settable Only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation ...

Page 112

... REGISTER 5-2: NVMKEY: NON-VOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 — — — bit 15 W-0 W-0 W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register bits (write-only) ...

Page 113

... PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY One row of program Flash memory can be programmed at a time. To achieve this necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. Read eight rows of program (512 instructions) and store in data RAM. ...

Page 114

... EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 MOV W0, NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 MOV W0, TBLPAG MOV #0x6000, W0 ...

Page 115

... RESETS Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Reset” (DS70192) in the “dsPIC33F/PIC24H Family Reference Manual”, which is avail- able from the Microchip web site (www ...

Page 116

... REGISTER 6-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...

Page 117

... System Reset The dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 families of devices have two types of Reset: • Cold Reset • Warm Reset A cold Reset is the result of a Power-on Reset (POR Brown-out Reset (BOR cold Reset, the FNOSC Configuration bits in the FOSC Configuration register select the device clock source ...

Page 118

... FIGURE 6-2: SYSTEM RESET TIMING V POR POR 1 POR Reset 2 BOR Reset SYSRST Oscillator Clock FSCM Device Status Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until V crosses the V ...

Page 119

... Power-on Reset (POR) A Power-on Reset (POR) circuit ensures the device is reset from power-on. The POR circuit is active until V crosses the V threshold and the delay POR has elapsed. The delay ensures the internal POR device bias circuits become stable. ...

Page 120

... External Reset (EXTR) The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt Trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse width will generate a Reset. Refer to Section 27.0 “Electrical Characteristics” for minimum pulse width specifications ...

Page 121

... Using the RCON Status Bits The user application can read the Reset Control (RCON) register after any device Reset to determine the cause of the Reset. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful ...

Page 122

... NOTES: DS70591C-page 122 Preliminary  2010 Microchip Technology Inc. ...

Page 123

... CPU. It has the following features: • eight processor exceptions and software traps • Seven user-selectable priority levels • Interrupt Vector Table (IVT) with up to 118 vectors • ...

Page 124

... FIGURE 7-1: dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved ...

Page 125

... TABLE 7-1: INTERRUPT VECTORS Interrupt Vector Request IVT Address Number (IQR 0x000014 9 1 0x000016 10 2 0x000018 11 3 0x00001A 12 4 0x00001C 13 5 0x00001E 14 6 0x000020 15 7 0x000022 16 8 0x000024 17 9 0x000026 18 10 0x000028 19 11 0x00002A 20 12 0x00002C 21 13 0x00002E ...

Page 126

... TABLE 7-1: INTERRUPT VECTORS (CONTINUED) Interrupt Vector Request IVT Address Number (IQR) 63-64 55-56 0x000082- 0x000084 65 57 0x000086 66 58 0x000088 67-72 59-64 0x00008A- 0x000094 73 65 0x000096 74 66 0x000098 75-77 67-69 0x00009A- 0x00009E 78 70 0x0000A0 79 71 0x0000A2 80 72 0x0000A4 ...

Page 127

... Interrupt Control and Status Registers The dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 devices implement 27 registers for the interrupt controller: • INTCON1 • INTCON2 • IFSx • IECx • IPCx • INTTREG 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2 ...

Page 128

... REGISTER 7-1: SR: CPU STATUS REGISTER R-0 R-0 R/C bit 15 (3) (3) R/W-0 R/W-0 R/W-0 (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Clearable bit R = Readable bit S = Settable bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits ...

Page 129

... REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR bit 15 R/W-0 R/W-0 R/W-0 SFTACERR DIV0ERR DMACERR bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...

Page 130

... REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred ...

Page 131

... REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 ALTIVT DISI — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit ...

Page 132

... REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 R/W-0 R/W-0 — DMA1IF ADIF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14 ...

Page 133

... REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred ...

Page 134

... REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 U2TXIF U2RXIF INT2IF bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 12 U2TXIF: UART2 Transmitter Interrupt Flag Status bit ...

Page 135

... REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 R/W-0 R/W-0 — IC4IF IC3IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ ...

Page 136

... REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 R/W-0 R/W-0 — INT4IF INT3IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ ...

Page 137

... REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 R/W-0 U-0 (1) — C1TXIF — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ ...

Page 138

... REGISTER 7-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 R/W-0 R/W-0 R/W-0 PWM2IF PWM1IF ADCP12IF bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PWM2IF: PWM2 Interrupt Flag Status bit ...

Page 139

... REGISTER 7-11: IFS6: INTERRUPT FLAG STATUS REGISTER 6 R/W-0 R/W-0 U-0 ADCP1IF ADCP0IF — bit 15 R/W-0 R/W-0 R/W-0 AC2IF PWM9IF PWM8IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ADCP1IF: ADC Pair 1 Conversion Done Interrupt Flag Status bit ...

Page 140

... REGISTER 7-12: IFS7: INTERRUPT FLAG STATUS REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — ADCP7IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ ...

Page 141

... REGISTER 7-13: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 R/W-0 R/W-0 — DMA1IE ADIE bit 15 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14 ...

Page 142

... REGISTER 7-13: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled ...

Page 143

... REGISTER 7-14: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 12 U2TXIE: UART2 Transmitter Interrupt Enable bit ...

Page 144

... REGISTER 7-15: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 R/W-0 R/W-0 — IC4IE IC3IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ ...

Page 145

... REGISTER 7-16: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 R/W-0 R/W-0 — INT4IE INT3EI bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ ...

Page 146

... REGISTER 7-17: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 R/W-0 U-0 (1) — C1TXIE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ ...

Page 147

... REGISTER 7-18: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 R/W-0 R/W-0 R/W-0 PWM2IE PWM1IE ADCP12IE bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PWM2IE: PWM2 Interrupt Enable bit ...

Page 148

... REGISTER 7-19: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 R/W-0 R/W-0 U-0 ADCP1IE ADCP0IE — bit 15 R/W-0 R/W-0 R/W-0 AC2IE PWM9IE PWM8IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ADCP1IE: ADC Pair 1 Conversion Done Interrupt Enable bit ...

Page 149

... REGISTER 7-20: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — ADCP7IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ ...

Page 150

... REGISTER 7-21: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...

Page 151

... REGISTER 7-22: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 — T2IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...

Page 152

... REGISTER 7-23: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP<2:0> bit 15 U-0 R/W-1 R/W-0 — SPI1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...

Page 153

... REGISTER 7-24: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — ADIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA1IP< ...

Page 154

... REGISTER 7-25: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP<2:0> bit 15 U-0 R/W-1 R/W-0 — MI2C1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...

Page 155

... REGISTER 7-26: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-3 Unimplemented: Read as ‘0’ ...

Page 156

... REGISTER 7-27: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 — T4IP<2:0> bit 15 U-0 R/W-1 R/W-0 — OC3IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...

Page 157

... REGISTER 7-28: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 — U2TXIP<2:0> bit 15 U-0 R/W-1 R/W-0 — INT2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...

Page 158

... REGISTER 7-29: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 R/W-1 R/W-0 — C1IP<2:0> bit 15 U-0 R/W-1 R/W-0 — SPI2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 C1IP<2:0>: ECAN1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...

Page 159

... REGISTER 7-30: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — IC3IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 IC4IP< ...

Page 160

... REGISTER 7-31: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — SI2C2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP< ...

Page 161

... REGISTER 7-32: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — INT3IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 INT4IP< ...

Page 162

... REGISTER 7-33: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — PSEMIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 QEI1IP< ...

Page 163

... REGISTER 7-34: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — U1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 U2EIP< ...

Page 164

... REGISTER 7-35: IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ ...

Page 165

... REGISTER 7-36: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 R/W-1 R/W-0 — QEI2IP<2:0> bit 15 U-0 R/W-1 R/W-0 — PSESMIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 QEI2IP<2:0>: QEI2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...

Page 166

... REGISTER 7-37: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 R/W-1 R/W-0 — ADCP10IP<2:0> bit 15 U-0 R/W-1 R/W-0 — ADCP8IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADCP10IP<2:0>: ADC Pair 10 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...

Page 167

... REGISTER 7-38: IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — ADCP12IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ADCP12IP< ...

Page 168

... REGISTER 7-39: IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 U-0 R/W-1 R/W-0 — PWM2IP<2:0> bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 PWM2IP< ...

Page 169

... REGISTER 7-40: IPC24: INTERRUPT PRIORITY CONTROL REGISTER 24 U-0 R/W-1 R/W-0 — PWM6IP<2:0> bit 15 U-0 R/W-1 R/W-0 — PWM4IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 PWM6IP<2:0>: PWM6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) • ...

Page 170

... REGISTER 7-41: IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25 U-0 R/W-1 R/W-0 — AC2IP<2:0> bit 15 U-0 R/W-1 R/W-0 — PWM8IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 AC2IP<2:0>: Analog Comparator 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) • ...

Page 171

... REGISTER 7-42: IPC26: INTERRUPT PRIORITY CONTROL REGISTER 26 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — AC4IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AC4IP< ...

Page 172

... REGISTER 7-43: IPC27: INTERRUPT PRIORITY CONTROL REGISTER 27 U-0 R/W-1 R/W-0 — ADCP1IP<2:0> bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADCP1IP< ...

Page 173

... REGISTER 7-44: IPC28: INTERRUPT PRIORITY CONTROL REGISTER 28 U-0 R/W-1 R/W-0 — ADCP5IP<2:0> bit 15 U-0 R/W-1 R/W-0 — ADCP3IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADCP5IP<2:0>: ADC Pair 5 Conversion Done Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...

Page 174

... REGISTER 7-45: IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — ADCP7IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ADCP7IP< ...

Page 175

... REGISTER 7-46: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R-0 R-0 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR< ...

Page 176

... Interrupt Setup Procedures 7.4.1 INITIALIZATION Complete the following steps to configure an interrupt source at initialization: 1. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register ...

Page 177

... DIRECT MEMORY ACCESS (DMA) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 family of devices. However not intended comprehensive refer- ence source. To complement the informa- tion in this data sheet, refer to Section 22. “Direct Memory Access (DMA)” ...

Page 178

... The DMA controller features four identical data transfer channels. Each channel has its own set of control and STATUS registers. Each DMA channel can be configured to copy data either from buffers stored in dual port DMA RAM to peripheral SFRs or from peripheral SFRs to buffers in DMA RAM. ...

Page 179

... REGISTER 8-1: DMAxCON: DMA CHANNEL x CONTROL REGISTER R/W-0 R/W-0 R/W-0 CHEN SIZE DIR bit 15 U-0 U-0 R/W-0 — — AMODE<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CHEN: Channel Enable bit 1 = Channel enabled ...

Page 180

... REGISTER 8-2: DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER R/W-0 U-0 U-0 (1) FORCE — — bit 15 U-0 R/W-1 R/W-1 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 FORCE: Force DMA Transfer bit 1 = Force a single DMA transfer (Manual mode) ...

Page 181

... REGISTER 8-3: DMAxSTA: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER A R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 STA<15:0>: Primary DMA RAM Start Address bits (source or destination) ...

Page 182

... REGISTER 8-5: DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PAD<15:0>: Peripheral Address Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided ...

Page 183

... REGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ ...

Page 184

... REGISTER 8-8: DMACS1: DMA CONTROLLER STATUS REGISTER 1 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ ...

Page 185

... REGISTER 8-9: DSADR MOST RECENT DMA RAM ADDRESS R-0 R-0 R-0 bit 15 R-0 R-0 R-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits  ...

Page 186

... NOTES: DS70591C-page 186 Preliminary  2010 Microchip Technology Inc. ...

Page 187

... OSCILLATOR CONFIGURATION Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 42. “Oscillator (Part IV)” (DS70307) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www ...

Page 188

... FIGURE 9-1: dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator (P ) OSC OSC1 POSCCLK ( OSC2 POSCMD<1:0> FRC Oscillator TUN<5:0> ÷ 16 LPRC Oscillator Secondary Oscillator (S OSC SOSCO LPOSCEN SOSCI Reference Clock Generation POSCCLK ÷ OSC REFCLKO ROSEL RODIV<3:0> Auxiliary Clock Generation ...

Page 189

... CPU Clocking System The dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 devices provide six system clock options: • Fast RC (FRC) Oscillator • FRC Oscillator with PLL • Primary (XT, HS, or EC) Oscillator • Primary Oscillator with PLL • Low-Power RC (LPRC) Oscillator • FRC Oscillator with Postscaler • ...

Page 190

... TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Fast RC Oscillator with Divide-by-N (FRCDIVN) Fast RC Oscillator with Divide-by-16 (FRCDIV16) Low-Power RC Oscillator (LPRC) Secondary Oscillator (SOSC) Primary Oscillator (HS) with PLL (HSPLL) Primary Oscillator (XT) with PLL (XTPLL) Primary Oscillator (EC) with PLL (ECPLL) ...

Page 191

... FIGURE 9-2: dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 PLL BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) Note 1: This frequency range must be satisfied at all times. 9.2 Auxiliary Clock Generation The auxiliary clock generation is used for a peripherals that need to operate at a frequency unrelated to the system clock such as a PWM or ADC ...

Page 192

... REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-y R-y — COSC<2:0> bit 15 R/W-0 U-0 R-0 CLKLOCK — LOCK bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...

Page 193

... REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-1 ROI DOZE<2:0> bit 15 R/W-0 R/W-1 U-0 PLLPOST<1:0> — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 ...

Page 194

... REGISTER 9-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) ...

Page 195

... REGISTER 9-4: OSCTUN: OSCILLATOR TUNING REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN< ...

Page 196

... REGISTER 9-5: ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER R/W-0 R-0 R/W-1 ENAPLL APLLCK SELACLK bit 15 R/W-0 R/W-0 U-0 ASRCSEL FRCSEL — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ENAPLL: Auxiliary PLL Enable bit ...

Page 197

... REGISTER 9-6: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 ROON — ROSSLP bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROON: Reference Oscillator Output Enable bit ...

Page 198

... Applications are free to switch among any of the four clock sources (primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ32GS406/606/608/ 610 and dsPIC33FJ64GS406/606/608/610 devices have a safeguard lock built into the switch process. Note: Primary oscillator mode has three different ...

Page 199

... Instruction-Based Power-Saving Modes The dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 devices have two spe- cial power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution. Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assem- Modes” ...

Page 200

... IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 10.5 “ ...